JP2017506430A - スケーリングされたレイアウト設計におけるダミーゲートのアース - Google Patents

スケーリングされたレイアウト設計におけるダミーゲートのアース Download PDF

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JP2017506430A
JP2017506430A JP2016549575A JP2016549575A JP2017506430A JP 2017506430 A JP2017506430 A JP 2017506430A JP 2016549575 A JP2016549575 A JP 2016549575A JP 2016549575 A JP2016549575 A JP 2016549575A JP 2017506430 A JP2017506430 A JP 2017506430A
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gate
contact
active
stacked
aligned
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JP2017506430A5 (https=
Inventor
スタンリー・スンチュル・ソン
ジョンゼ・ワン
オーサン・クウォン
カーン・リム
ジョン・ジェンホン・ジュ
シャンドン・チェン
フーア・ヴァン
レイモンド・ジョージ・ステファニー
チョ・フェイ・イェプ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/959—Connectability characteristics, i.e. diffusion and polysilicon geometries
    • H10D84/966—Gate electrode terminals or contacts

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2016549575A 2014-02-14 2015-01-08 スケーリングされたレイアウト設計におけるダミーゲートのアース Pending JP2017506430A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461940011P 2014-02-14 2014-02-14
US61/940,011 2014-02-14
US14/274,184 2014-05-09
US14/274,184 US9379058B2 (en) 2014-02-14 2014-05-09 Grounding dummy gate in scaled layout design
PCT/US2015/010667 WO2015122974A1 (en) 2014-02-14 2015-01-08 Grounding dummy gate in scaled layout design

Publications (2)

Publication Number Publication Date
JP2017506430A true JP2017506430A (ja) 2017-03-02
JP2017506430A5 JP2017506430A5 (https=) 2018-02-01

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JP2016549575A Pending JP2017506430A (ja) 2014-02-14 2015-01-08 スケーリングされたレイアウト設計におけるダミーゲートのアース

Country Status (5)

Country Link
US (1) US9379058B2 (https=)
EP (1) EP3105782B1 (https=)
JP (1) JP2017506430A (https=)
CN (1) CN105981157B (https=)
WO (1) WO2015122974A1 (https=)

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US20160005822A1 (en) * 2014-07-01 2016-01-07 Qualcomm Incorporated Self-aligned via for gate contact of semiconductor devices
US10361195B2 (en) * 2014-09-04 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor device with an isolation gate and method of forming
US9496394B2 (en) 2014-10-24 2016-11-15 Globalfoundries Inc. Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
US9570573B1 (en) * 2015-08-10 2017-02-14 Globalfoundries Inc. Self-aligned gate tie-down contacts with selective etch stop liner
US9935100B2 (en) * 2015-11-09 2018-04-03 Qualcomm Incorporated Power rail inbound middle of line (MOL) routing
US10153351B2 (en) 2016-01-29 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
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US9548366B1 (en) 2016-04-04 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self aligned contact scheme
US10141256B2 (en) * 2016-04-21 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and layout design thereof
CN107452680B (zh) 2016-06-01 2020-05-05 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US9837351B1 (en) * 2016-06-07 2017-12-05 International Business Machines Corporation Avoiding gate metal via shorting to source or drain contacts
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
KR102308779B1 (ko) * 2017-04-10 2021-10-05 삼성전자주식회사 이종 컨택들을 구비하는 집적 회로 및 이를 포함하는 반도체 장치
US10269636B2 (en) 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US10651284B2 (en) * 2017-10-24 2020-05-12 Globalfoundries Inc. Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
US10600866B2 (en) 2018-02-01 2020-03-24 Qualcomm Incorporated Standard cell architecture for gate tie-off
KR102516878B1 (ko) 2018-07-26 2023-03-31 삼성전자주식회사 집적회로 소자
US10832963B2 (en) 2018-08-27 2020-11-10 International Business Machines Corporation Forming gate contact over active free of metal recess
US10950732B2 (en) * 2018-09-21 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US11335596B2 (en) 2018-10-30 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Selective deposition for integrated circuit interconnect structures
US11056537B2 (en) * 2019-03-27 2021-07-06 International Business Machines Corporation Self-aligned gate contact integration with metal resistor
US11164782B2 (en) 2020-01-07 2021-11-02 International Business Machines Corporation Self-aligned gate contact compatible cross couple contact formation
US12199161B2 (en) 2020-12-16 2025-01-14 Intel Corporation Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication
US12237388B2 (en) 2020-12-16 2025-02-25 Intel Corporation Transistor arrangements with stacked trench contacts and gate straps
US11723194B2 (en) 2021-03-05 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit read only memory (ROM) structure
US11929314B2 (en) * 2021-03-12 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures including a fin structure and a metal cap
US11862625B2 (en) 2021-07-01 2024-01-02 Nxp Usa, Inc. Area-efficient ESD protection inside standard cells
US12230684B2 (en) 2021-07-26 2025-02-18 Samsung Electronics Co., Ltd. Integrated circuit with continuous active region and raised source/drain region
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EP3105782B1 (en) 2018-08-01
US9379058B2 (en) 2016-06-28
WO2015122974A1 (en) 2015-08-20
EP3105782A1 (en) 2016-12-21
CN105981157B (zh) 2020-12-08
CN105981157A (zh) 2016-09-28
US20150235948A1 (en) 2015-08-20

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