TWI668728B - 用作互連之虛擬閘極及其製法 - Google Patents

用作互連之虛擬閘極及其製法 Download PDF

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TWI668728B
TWI668728B TW105105404A TW105105404A TWI668728B TW I668728 B TWI668728 B TW I668728B TW 105105404 A TW105105404 A TW 105105404A TW 105105404 A TW105105404 A TW 105105404A TW I668728 B TWI668728 B TW I668728B
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gate structure
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文惠 王
永漢 金萊恩
林斯 詹
傑森 肯特尼
利 尚
賽歐沃 納莫
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美商格羅方德半導體公司
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Abstract

揭露一種用作互連之虛擬閘極製程及其製法。實施例包括：在半導體基板上於單元邊界處形成虛擬閘極結構，各虛擬閘極結構包含一組側壁間隔件及設於該等側壁間隔件之間的蓋層；移除在第一虛擬閘極結構之第一側上之第一側壁間隔件或第一蓋層的至少一部分，以及在該第一虛擬閘極結構上方形成第一閘極接觸溝槽；以及以金屬填充該第一閘極接觸溝槽以形成第一閘極接觸。

Description

用作互連之虛擬閘極及其製法
本揭露係關於半導體裝置之製造，且具體而言，係關於減少金屬1(「M1」)擁塞(Metal 1 congestion)的製程。本揭露尤其可應用於針對10及7奈米(nm)及以上之技術節點的半導體裝置。
半導體裝置係使用於大量電子裝置中，例如電腦、手機等等。半導體裝置包含積體電路，其藉由沉積許多類型之薄膜材料於半導體晶圓上方且圖案化該薄膜材料以形成積體電路而形成在半導體晶圓上。半導體產業之一個目標係持續縮小電路之尺寸。然而，當電路之單元尺寸以先進的技術節點縮小尺度時，M1設計中之擁塞變得具有挑戰性。具體而言，使邏輯單元庫致能而沒有改善解析度(例如，使用極紫外光(EUV))會使得給定的元件軌跡庫(例如，9軌跡)中的M1設計困難。
如第1圖所示，一般使用虛擬閘極結構以定義淺溝槽隔離(STI)區域。具體而言，複數個閘極結構101a,101b係形成在基板100上方。閘極結構111係虛擬閘極結 構，用以定義於單元區域之邊緣103處之STI區域102。凹穴110係鄰近虛擬閘極結構111而形成。凹穴104係藉由蝕刻通過介電層105及層間介電質109而產生於實際閘極結構101a,101b中，且蓋層(cap)係形成在實際閘極結構101a,101b的側壁間隔件106,107之間。蓋層係於實際閘極結構101a,101b中的側壁間隔件106,107之間產生凹部113的蝕刻期間移除。凹穴110係鄰近虛擬閘極結構111形成。閘極結構101a,101b係形成在源極/汲極區域108之間。虛擬閘極結構111保持蓋層115。
第2圖說明一種習知積體電路佈線，其具有設置在二相鄰單元201,202之間的STI區域102。STI區域102係藉由位於單元201之邊緣處的虛擬閘極結構111、以及單元202之邊緣處的虛擬閘極結構111而定義。M1層包含區段203、205和207。如圖所示，由於擁塞，M1層需要三種不同顏色以供可印性。雖然虛擬閘極結構係一般用於定義STI區域，但其不足以減緩M1設計中之擁塞問題。
因此存在用於藉由緩解M1設計中之擁塞(例如，釋放空間)而不須另外的處理步驟以改進M1設計圖案化的方法及其裝置的需要。
本揭露之一種態樣係將M1線路之一部分移動至虛擬閘極電極以釋放供M1圖案化的空間。閘極接觸能用以縮短通至主動區域(例如，源極及汲極區域)的虛擬閘極及接觸而不改變現有處理技術。
本揭露之額外態樣及其它特徵將於描述中提出，以下及部分之該描述對所屬技術領域中具有通常知識者而言在審視下文後將會清楚明白，或者可從本揭露之實施習得。本揭露之優點可如所附申請專利範圍中特定指出者而實現並獲得。
依據本揭露，藉由一種方法可部分達到某些技術功效，該方法包含：在半導體基板上於單元邊界處形成虛擬閘極結構，各虛擬閘極結構包含一組側壁間隔件及設於該等側壁間隔件之間的蓋層；移除在第一虛擬閘極結構之第一側上之第一側壁間隔件或第一蓋層的至少一部分，且在該第一虛擬閘極結構上方形成第一閘極接觸溝槽；以及以金屬填充該第一閘極接觸溝槽以形成第一閘極接觸。
本揭露之態樣包含移除在第二虛擬閘極結構之第二側上的第二側壁間隔件或第二蓋層，且在該第二虛擬閘極結構上方形成第二閘極接觸溝槽；以及以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充該第一及該第二閘極接觸溝槽。其它態樣包含於該半導體基板之PFET側上形成該第一虛擬閘極結構；以及於該半導體基板之NFET側上形成該第二虛擬閘極結構。另外態樣包含於第一淺溝槽隔離(STI)區域上方形成該第一虛擬閘極結構；以及於第二STI區域上方形成該第二虛擬閘極結構。又其它態樣包含於該第一及第二虛擬閘極結構上形成該第一及第二閘極接觸作為厚或移動的閘極接觸。進一步態樣包含形成低介電 係數材料或矽氮化物(SiN)之該第一及第二側壁間隔件或第一及第二蓋層，其中，移除該第一及第二側壁間隔件或第一及第二蓋層包括：蝕刻在該第一虛擬閘極結構之第一側上的該第一側壁間隔件，且蝕刻在該第二虛擬閘極結構之第二側上的該第二側壁間隔件。另一態樣包含該低介電係數材料係矽氧碳氮化物(SiOCN)。進一步態樣包含於該第一及第二閘極接觸上方設置金屬化層。又其它態樣包含連接該第一虛擬閘極結構之第一源極/汲極結構與該第二虛擬閘極結構之第二源極/汲極結構。額外態樣包含在該第一與第二虛擬閘極結構之間形成至少一個實際閘極結構。另一態樣包含該至少一個實際閘極結構係設置在源極區域與汲極區域之間。
本揭露之另一態樣係一種裝置，包括：半導體基板；複數個實際閘極結構，係設置在該半導體基板上方；金屬化層，係設置在該等實際閘極結構上方；以及第一虛擬閘極結構，係包含在該第一虛擬閘極結構之第一側上之單一側壁間隔件以及在該第一虛擬閘極結構上方的第一閘極接觸，該第一閘極接觸連接至第二側上之源極/汲極區域。
態樣包含；第二虛擬閘極結構，其係包含在該第二虛擬閘極結構之第二側上的單一側壁間隔件；以及第二閘極接觸，其係在該第二虛擬閘極結構上方，該第二閘極接觸連接至第二側上的源極/汲極區域。其它態樣包含以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充的該第一 及第二閘極接觸。又其它態樣包含形成於第一及第二淺溝槽隔離區域上方的該第一及第二虛擬閘極結構。進一步態樣包含形成在該半導體基板之PFET區域中的該第一虛擬閘極結構，以及形成在該半導體基板之NFET區域中的該第二虛擬閘極結構；以及連接NFET源極/汲極區域與PFET源極/汲極區域的該第一或第二虛擬閘極結構。其它態樣包含形成於單元之第一邊緣處的該第一虛擬閘極結構，及形成於該單元之第二邊緣處的該第二虛擬閘極結構。
本揭露之另一態樣係一種方法，其包含：在半導體基板上於單元邊界處形成虛擬閘極結構，各虛擬閘極結構包含一組側壁間隔件及設於該等側壁間隔件之間的蓋層；藉由同時移除在第一虛擬閘極結構之第一側上的第一側壁間隔件，且蝕刻該第一虛擬閘極結構上方的第一閘極接觸溝槽，並移除在第二虛擬閘極結構之第二側上的第二側壁間隔件，且蝕刻該第二虛擬閘極結構上方的第二閘極接觸溝槽，而形成第一及第二擴張閘極接觸溝槽；形成在該第一及第二虛擬閘極結構之間的實際閘極結構；以及以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充該第一及第二擴張閘極接觸溝槽，以分別連接該第一及第二閘極接觸與第一及第二源極/汲極區域。
本揭露之態樣包含在該半導體基板之PFET側上形成該第一虛擬閘極結構；以及在該半導體基板之NFET側上形成該第二虛擬閘極結構。其它態樣包含在第一淺溝槽隔離(STI)區域上方形成該第一虛擬閘極結構；以 及在第二淺溝槽隔離(STI)區域上方形成該第二虛擬閘極結構。
本揭露之另外態樣及技術功效對於所屬技術領域中具有通常知識者而言將從下文詳細描述而輕而易舉變得清楚明白，其中，本揭露之實施例藉由進行本揭露之深思最佳模式說明的方式而簡化描述。正如將理解的，本揭露能具有其它及不同之實施例，且能在完全不悖離本揭露下具有各種顯而易見態樣中之修飾的數種細節。因此，圖式及描述係實際視為例示性，而非限制性。
100‧‧‧基板
101a、101b、111‧‧‧閘極結構
102、412、413‧‧‧淺溝槽隔離(STI)區域
103‧‧‧邊緣
104、110‧‧‧凹穴
105‧‧‧介電層
106、107‧‧‧側壁間隔件
108‧‧‧源極/汲極區域
109、402‧‧‧層間介電質(ILD)
113‧‧‧凹部
115‧‧‧蓋層
201、202、501、502‧‧‧單元
203、205、207‧‧‧區段
400‧‧‧基板
402‧‧‧ILD
401a、401b、401c、401d‧‧‧實際閘極結構
408、410‧‧‧主動區域
411、416‧‧‧虛擬閘極結構
414、415、417、418、601、602‧‧‧閘極接觸
500a、500b、600‧‧‧積體電路佈線
503‧‧‧電源軌
504‧‧‧虛擬閘極電極
505‧‧‧導孔
506‧‧‧金屬
507/508‧‧‧源極/汲極
603‧‧‧源極/汲極接觸
本揭露藉由示例方式說明，而非藉由限制方式，圖式所附之圖示及其相同符號係對應類似組件，且其中：第1圖示意說明使用虛擬閘極結構以定義STI區域之習知製程的剖面圖；第2圖示意說明於相鄰單元之邊緣處使用虛擬閘極結構以定義STI區域之習知積體電路佈線；第3圖示意說明依據例示實施例之虛擬閘極結構的閘極接觸蝕刻之剖面圖；第4圖示意說明依據例示實施例之PFET及NFET區域中的虛擬閘極圖案之閘極接觸蝕刻的剖面圖；第5A及5B圖示意說明依據例示實施例之積體電路佈線；以及第6圖示意說明依據例示實施例之積體電 路佈線。
在以下描述中，為了說明，提出各種特定細節以提供例示實施例之通透瞭解。然而，顯然例示實施例可無需這些特定細節或以等效配置而實施。在其他情況下，為了免於不必要地混淆例示實施例，已知結構及裝置係以方塊圖顯示。另外，除了另有指出，表示用於說明書及申請專利範圍中的组成部分、反應條件等等之數量、比例及數值特性的所有數字係應理解在所有情況下藉由詞語「約」加以修飾。
本揭露對付並解決在先進技術節點中縮小單元尺寸所遇到之M1設計拥塞之當前問題。藉由使用虛擬閘極作為互連而不須額外的處理步驟，空間在M1設計佈線中能被釋放。在更多空間變得可以取得之後，M1之顏色能被重新分配且提升可印性。
對所屬技術領域中具有通常知識者而言，藉由下列實施方式，其它進一步的態樣、特徵及技術功效將變得顯而易見，其中僅藉由說明所思及之最佳模式而顯示並描述較佳實施例。本揭露能有其它及不同的實施例，而其數項細節能在各種明顯態樣中進行修飾。因此，圖式及描述應在本質上視為例示性，而非限制性。
請注意第3圖，舉例而言，複數個閘極結構101a,101b係形成於基板100上方。閘極結構111係形成於單元區域之邊緣處的虛擬閘極結構。為了形成閘極接觸， 藉由蝕刻通過氧化層/介電層105及層間介電質(ILD)109以及蓋層115(第1圖)而產生凹穴110於虛擬閘極結構111上方。凹穴110的形成亦移除最接近該單元區域之邊緣的蓋層115及側壁間隔件且僅留下虛擬閘極結構111之其中一個側壁間隔件。各實際閘極結構101a,101b係形成於源極/汲極區域108之間。各虛擬閘極將僅具有一個源極/汲極區域於一側而其它側係空的。
第4圖示意性說明在執行金屬填充步驟以產生金屬閘極結構之後的單元之PFET及NFET區域中的複數個閘極結構之剖面圖。在蝕刻介電質、ILD 402及一部分或全部的蓋層115(第1圖)以形成閘極接觸溝槽的期間，PFET區域中之虛擬閘極結構411的單元邊緣側上之側壁間隔件及蓋層會被移除而僅留下一個側壁間隔件。在相同的蝕刻步驟期間，移除在NFET區域中之虛擬閘極結構416的相對單元側上之側壁間隔件及蓋層會被移除而僅留下一個側壁間隔件。用於形成閘極接觸溝槽及用於移除各虛擬閘極的其中一個側壁間隔件之蝕刻步驟係氮化物類型蝕刻。而且，在相同的蝕刻期間，亦形成用於實際閘極結構401a,401b(PFET側)之閘極接觸溝槽，但實際閘極結構401a,401b仍保留有側壁間隔件組。而且，在相同的蝕刻期間，亦形成用於實際閘極結構401c,401d(NFET側)的閘極接觸溝槽，但實際閘極結構401c,401d仍保留有側壁間隔件組。
用於虛擬閘極結構411,416之閘極接觸溝槽係以金屬414,417填充以分別形成在PFET及NFET區域 之邊緣處的閘極結構之閘極接觸。再者，用於實際閘極結構401a,401b,401c,401d之接觸溝槽亦以金屬418填充。對主動區域(即，源極/汲極區域)408之接觸係以形成於PFET區域中的鄰接STI區域412上方的閘極接觸414連接。類似地，對主動區域(即，源極/汲極區域)410之接觸係以形成於NFET區域中的鄰接STI區域413上方的閘極接觸417連接。在各414,415,418,417中之金屬係相同。金屬層415接著係在藉由例如化學機械平坦化(CMP)之平坦化技術的溝槽填充之後移除。金屬化層能在該CMP之後形成。
請注意第5A圖，其說明積體電路佈線500a。單元501,502係設置於電源軌503之間。當虛擬閘極電極504及通向源極/汲極區域之導孔505係在第5A圖之圓圈區域中連接時，在例如506處需要M1。金屬506係使用導孔505以連接源極汲極505至508。
第5B圖說明具有虛擬閘極之積體電路佈線500b，該虛擬閘極藉由形成連接至單元501,502之圓圈區域中的源極/汲極507之厚或移動(shifted)的閘極接觸505而用作互連。在507與508之間的連接係藉由虛擬閘極及移動的閘極接觸505而建立。不再需要金屬線。由於虛擬閘極用作互連，在更多空間變得可用之後，M1之顏色可被重新分配。相較於第5A圖中之佈線可改善可印性。
請注意第6圖，其說明積體電路佈線600其中厚或移動的閘極接觸601,602係形成在虛擬閘極結構 上，且連接至源極/汲極接觸603。因此，M1顏色已被重新分配。
本揭露之實施例能達到數種技術效果，例如藉由使用虛擬閘極作為互連而減緩在M1設計佈線中的擁塞。依據本揭露之實施例所形成之裝置在例如微處理器、智慧型手機、行動電話、手機、機上盒、DVD錄影機及播放器、汽車導航、印表機和周邊、網路和通訊設備、遊戲系統及數位相機的各種產業應用上享有多種用途。因此，本揭露在使用虛擬閘極作為互連(特別是10nm、7nm及以上之技術節點)以製造任何各種類型的高度集成之半導體裝置上享有產業應用性。
在先前描述中，本揭露係參照其具體例示實施例而描述。然而，顯然在不悖離如申請專利範圍所闡述的本揭露之廣泛精神及範疇下可作出各種修飾及改變。因此，本說明書及圖式係視為例示性而非限制性。應理解的是，本揭露能使用各種其它組合和實施例且能在如本文表示之發明內容的範疇內作出任何改變或修飾。

Claims (16)

  1. 一種製造半導體裝置之方法，該方法係包括：在半導體基板上於單元邊界處形成虛擬閘極結構，各虛擬閘極結構包含一組側壁間隔件及設於該等側壁間隔件之間的蓋層；移除在第一虛擬閘極結構之第一側上之第一側壁間隔件或第一蓋層的至少一部分，且在該第一虛擬閘極結構上方形成第一閘極接觸溝槽；以金屬填充該第一閘極接觸溝槽以形成第一閘極接觸；移除在第二虛擬閘極結構之第二側上的第二側壁間隔件或第二蓋層，且在該第二虛擬閘極結構上方形成第二閘極接觸溝槽；以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充該第一及該第二閘極接觸溝槽；以及在該第一虛擬閘極結構與第二虛擬閘極結構之間形成至少一個實際閘極結構。
  2. 如申請專利範圍第1項所述之方法，係包括：於該半導體基板之PFET側上形成該第一虛擬閘極結構；以及於該半導體基板之NFET側上形成該第二虛擬閘極結構。
  3. 如申請專利範圍第2項所述之方法，更包括：於第一淺溝槽隔離(STI)區域上方形成該第一虛擬 閘極結構；以及於第二淺溝槽隔離(STI)區域上方形成該第二虛擬閘極結構。
  4. 如申請專利範圍第1項所述之方法，係包括於該第一虛擬閘極結構及第二虛擬閘極結構上形成該第一閘極接觸作為厚或移動的閘極接觸。
  5. 如申請專利範圍第4項所述之方法，更包括形成低介電係數材料或矽氮化物(SiN)之該第一及第二側壁間隔件或第一及第二蓋層，其中，移除該第一及第二側壁間隔件或第一及第二蓋層包括：蝕刻在該第一虛擬閘極結構之該第一側上的該第一側壁間隔件，以及蝕刻在該第二虛擬閘極結構之該第二側上的該第二側壁間隔件。
  6. 如申請專利範圍第5項所述之方法，其中，該低介電係數材料係矽氧碳氮化物(SiOCN)。
  7. 如申請專利範圍第1項所述之方法，更包括：於該第一閘極接觸上方設置金屬化層。
  8. 如申請專利範圍第1項所述之方法，更包括：連接該第一虛擬閘極結構之第一源極/汲極結構與該第二虛擬閘極結構之第二源極/汲極結構。
  9. 如申請專利範圍第1項所述之方法，其中，該至少一個實際閘極結構係設置在源極區域與汲極區域之間。
  10. 一種半導體裝置，係包括： 半導體基板；複數個實際閘極結構，係設置在該半導體基板上方；金屬化層，係設置在該等實際閘極結構上方；第一虛擬閘極結構，係包含在該第一虛擬閘極結構之第一側上之單一側壁間隔件以及在該第一虛擬閘極結構上方的第一閘極接觸，該第一閘極接觸連接第二側上之源極/汲極區域；第二虛擬閘極結構，係包含在該第二虛擬閘極結構之第二側上的單一側壁間隔件，及第二閘極接觸，係在該第二虛擬閘極結構上方，該第二閘極接觸連接至第二側上的源極/汲極區域，其中，該等實際閘極結構係形成於該第一虛擬閘極結構和第二虛擬閘極結構之間；其中，該金屬化層設置在該第一及第二閘極接觸上方，其中，該第一虛擬閘極結構係形成在該半導體基板之PFET區域中，且該第二虛擬閘極結構係形成在該半導體基板之NFET區域中；以及該第一或第二虛擬閘極結構係連接NFET源極/汲極區域與PFET源極/汲極區域。
  11. 如申請專利範圍第10項所述之半導體裝置，其中，該第一及第二閘極接觸係以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充。
  12. 如申請專利範圍第10項所述之半導體裝置，其中，該第一及第二虛擬閘極結構係形成於第一及第二淺溝槽隔離區域上方。
  13. 如申請專利範圍第10項所述之半導體裝置，其中：該第一虛擬閘極結構係形成於單元之第一邊緣處，及該第二虛擬閘極結構係形成於該單元之第二邊緣處。
  14. 一種製造半導體裝置之方法，該方法係包括：在半導體基板上於單元邊界處形成虛擬閘極結構，各虛擬閘極結構包含一組側壁間隔件及設於該等側壁間隔件之間的蓋層；藉由同時移除在第一虛擬閘極結構之第一側上的第一側壁間隔件，且蝕刻該第一虛擬閘極結構上方的第一閘極接觸溝槽，並移除在第二虛擬閘極結構之第二側上的第二側壁間隔件，且蝕刻該第二虛擬閘極結構上方的第二閘極接觸溝槽，而形成第一及第二擴張閘極接觸溝槽；形成在該第一及第二虛擬閘極結構之間的實際閘極結構；以及以鎢、鎢合金、銅、鋁銅合金或矽銅合金填充該第一及第二擴張閘極接觸溝槽，以分別連接第一及第二源極/汲極區域與第一及第二閘極接觸。
  15. 如申請專利範圍第14項所述之方法，係包括：在該半導體基板之PFET側上形成該第一虛擬閘極 結構；以及在該半導體基板之NFET側上形成該第二虛擬閘極結構。
  16. 如申請專利範圍第14項所述之方法，係包括：在第一淺溝槽隔離(STI)區域上方形成該第一虛擬閘極結構；以及在第二淺溝槽隔離(STI)區域上方形成該第二虛擬閘極結構。
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