CN106252275B - 用作互连的虚拟栅极及其制法 - Google Patents

用作互连的虚拟栅极及其制法 Download PDF

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CN106252275B
CN106252275B CN201610404954.8A CN201610404954A CN106252275B CN 106252275 B CN106252275 B CN 106252275B CN 201610404954 A CN201610404954 A CN 201610404954A CN 106252275 B CN106252275 B CN 106252275B
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gate structure
dummy gate
method described
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CN106252275A (zh
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王文辉
R·R-H·金
L·江
J·坎托内
孙磊
S·南
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GlobalFoundries US Inc
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Abstract

本发明涉及一种用作互连的虚拟栅极及其制法。实施例包括：在半导体基板上于单元边界处形成虚拟栅极结构，各虚拟栅极结构包含一组侧壁间隔件及设于该侧壁间隔件之间的盖层；移除在第一虚拟栅极结构的第一侧上的第一侧壁间隔件或第一盖层的至少一部分，以及在该第一虚拟栅极结构上方形成第一栅极接触沟槽；以及以金属填充该第一栅极接触沟槽以形成第一栅极接触。

Description

用作互连的虚拟栅极及其制法
技术领域
本揭露关于半导体装置的制造，且具体而言，关于减少金属1(「M1」)拥塞(Metal 1congestion)的制程。本揭露尤其可应用于针对10及7纳米(nm)及以上的技术节点的半导体装置。
背景技术
半导体装置使用于大量电子装置中，例如电脑、手机等等。半导体装置包含集成电路，其藉由沉积许多类型的薄膜材料于半导体晶圆上方且图案化该薄膜材料以形成集成电路而形成在半导体晶圆上。半导体产业的一个目标是持续缩小电路的尺寸。然而，当电路的单元尺寸以先进的技术节点缩小尺度时，M1设计中的拥塞变得具有挑战性。具体而言，使逻辑单元库致能而没有改善解析度(例如，使用极紫外光(EUV))会使得给定的元件轨迹库(例如，9轨迹)中的M1设计困难。
如图1所示，一般使用虚拟栅极结构以定义浅沟槽隔离(STI)区域。具体而言，多个栅极结构101a,101b形成在基板100上方。栅极结构111为虚拟栅极结构，用以定义单元区域的边缘103处的STI区域102。凹穴110邻近虚拟栅极结构111而形成。凹穴104藉由蚀刻通过介电层105及层间介电质109而产生于实际栅极结构101a,101b中，且盖层(cap)形成在实际栅极结构101a,101b的侧壁间隔件106,107之间。盖层于实际栅极结构101a,101b中的侧壁间隔件106,107之间产生凹部113的蚀刻期间移除。凹穴110邻近虚拟栅极结构111形成。栅极结构101a,101b形成在源极/漏极区域108之间。虚拟栅极结构111保持盖层115。
图2说明一种习知集成电路布线，其具有设置在二相邻单元201,202之间的STI区域102。STI区域102藉由位于单元201的边缘处的虚拟栅极结构111、以及单元202的边缘处的虚拟栅极结构111而定义。M1层包含区段203,205和207。如图所示，由于拥塞，M1层需要三种不同颜色以供可印性。虽然虚拟栅极结构一般用于定义STI区域，但其不足以减缓M1设计中的拥塞问题。
因此存在用于藉由缓解M1设计中的拥塞(例如，释放空间)而不须另外的处理步骤以改进M1设计图案化的方法及其装置的需要。
发明内容
本揭露的一种态样将M1线路的一部分移动至虚拟栅极电极以释放供M1图案化的空间。栅极接触能用以缩短通至主动区域(例如，源极及漏极区域)的虚拟栅极及接触而不改变现有处理技术。
本揭露的额外态样及其它特征将于描述中提出，以下及部分的描述对所属技术领域的技术人员而言在审视下文后将会清楚明白，或者可从本揭露的实施习得。本揭露的优点可如权利要求书中特定指出者而实现并获得。
依据本揭露，藉由一种方法可部分达到某些技术功效，该方法包含：在半导体基板上于单元边界处形成虚拟栅极结构，各虚拟栅极结构包含一组侧壁间隔件及设于该等侧壁间隔件之间的盖层；移除在第一虚拟栅极结构的第一侧上的第一侧壁间隔件或第一盖层的至少一部分，且在该第一虚拟栅极结构上方形成第一栅极接触沟槽；以及以金属填充该第一栅极接触沟槽以形成第一栅极接触。
本揭露的态样包含移除在第二虚拟栅极结构的第二侧上的第二侧壁间隔件或第二盖层，且在该第二虚拟栅极结构上方形成第二栅极接触沟槽；以及以钨、钨合金、铜、铝铜合金或硅铜合金填充该第一及该第二栅极接触沟槽。其它态样包含于该半导体基板的PFET侧上形成该第一虚拟栅极结构；以及于该半导体基板的NFET侧上形成该第二虚拟栅极结构。另外态样包含于第一浅沟槽隔离(STI)区域上方形成该第一虚拟栅极结构；以及于第二STI区域上方形成该第二虚拟栅极结构。又其它态样包含于该第一及第二虚拟栅极结构上形成该第一及第二栅极接触作为厚或移动的栅极接触。进一步态样包含形成低介电系数材料或硅氮化物(SiN)的该第一及第二侧壁间隔件或第一及第二盖层，其中，移除该第一及第二侧壁间隔件或第一及第二盖层包括：蚀刻在该第一虚拟栅极结构的第一侧上的该第一侧壁间隔件，且蚀刻在该第二虚拟栅极结构的第二侧上的该第二侧壁间隔件。另一态样包含该低介电系数材料是硅氧碳氮化物(SiOCN)。进一步态样包含于该第一及第二栅极接触上方设置金属化层。又其它态样包含连接该第一虚拟栅极结构的第一源极/漏极结构与该第二虚拟栅极结构的第二源极/漏极结构。额外态样包含在该第一与第二虚拟栅极结构之间形成至少一个实际栅极结构。另一态样包含该至少一个实际栅极结构设置在源极区域与漏极区域之间。
本揭露的另一态样是一种装置，包括：半导体基板；多个实际栅极结构，设置在该半导体基板上方；金属化层，设置在该实际栅极结构上方；以及第一虚拟栅极结构，包含在该第一虚拟栅极结构的第一侧上的单一侧壁间隔件以及在该第一虚拟栅极结构上方的第一栅极接触，该第一栅极接触连接至第二侧上的源极/漏极区域。
态样包含：第二虚拟栅极结构，其包含在该第二虚拟栅极结构的第二侧上的单一侧壁间隔件；以及第二栅极接触，其在该第二虚拟栅极结构上方，该第二栅极接触连接至第二侧上的源极/漏极区域。其它态样包含以钨、钨合金、铜、铝铜合金或硅铜合金填充的该第一及第二栅极接触。又其它态样包含形成于第一及第二浅沟槽隔离区域上方的该第一及第二虚拟栅极结构。进一步态样包含形成在该半导体基板的PFET区域中的该第一虚拟栅极结构，以及形成在该半导体基板的NFET区域中的该第二虚拟栅极结构；以及连接NFET源极/漏极区域与PFET源极/漏极区域的该第一或第二虚拟栅极结构。其它态样包含形成于单元的第一边缘处的该第一虚拟栅极结构，及形成于该单元的第二边缘处的该第二虚拟栅极结构。
本揭露的另一态样是一种方法，其包含：在半导体基板上于单元边界处形成虚拟栅极结构，各虚拟栅极结构包含一组侧壁间隔件及设于该等侧壁间隔件之间的盖层；藉由同时移除在第一虚拟栅极结构的第一侧上的第一侧壁间隔件，且蚀刻该第一虚拟栅极结构上方的第一栅极接触沟槽，并移除在第二虚拟栅极结构的第二侧上的第二侧壁间隔件，且蚀刻该第二虚拟栅极结构上方的第二栅极接触沟槽，而形成第一及第二扩张栅极接触沟槽；形成在该第一及第二虚拟栅极结构之间的实际栅极结构；以及以钨、钨合金、铜、铝铜合金或硅铜合金填充该第一及第二扩张栅极接触沟槽，以分别连接该第一及第二栅极接触与第一及第二源极/漏极区域。
本揭露的态样包含在该半导体基板的PFET侧上形成该第一虚拟栅极结构；以及在该半导体基板的NFET侧上形成该第二虚拟栅极结构。其它态样包含在第一浅沟槽隔离(STI)区域上方形成该第一虚拟栅极结构；以及在第二浅沟槽隔离(STI)区域上方形成该第二虚拟栅极结构。
本揭露的另外态样及技术功效对于所属技术领域的技术人员而言将从下文详细描述而轻而易举变得清楚明白，其中，本揭露的实施例藉由进行本揭露的深思最佳模式说明的方式而简化描述。正如将理解的，本揭露能具有其它及不同的实施例，且能在完全不悖离本揭露下具有各种显而易见态样中的修饰的数种细节。因此，图式及描述实际视为例示性，而非限制性。
附图说明
本揭露藉由示例方式说明，而非藉由限制方式，图式所附的图示及其相同符号对应类似组件，且其中：
图1示意说明使用虚拟栅极结构以定义STI区域之习知制程的剖面图；
图2示意说明于相邻单元之边缘处使用虚拟栅极结构以定义STI区域之习知集成电路布线；
图3示意说明依据例示实施例之虚拟栅极结构的栅极接触蚀刻之剖面图；
图4示意说明依据例示实施例之PFET及NFET区域中的虚拟栅极图案之栅极接触蚀刻的剖面图；
图5A及5B示意说明依据例示实施例之集成电路布线；以及
图6示意说明依据例示实施例之集成电路布线。
符号说明
100 基板
101a、101b、111 栅极结构
102、412、413 浅沟槽隔离(STI)区域
103 边缘
104、110 凹穴
105 介电层
106、107 侧壁间隔件
108 源极/漏极区域
109、402 层间介电质(ILD)
113 凹部
115 盖层
201、202、501、502 单元
203、205、207 区段
400 基板
402 ILD
401a、401b、401c、401d 实际栅极结构
408、410 主动区域
411、416 虚拟栅极结构
414、415、417、418、601、602 栅极接触
500a、500b、600 集成电路布线
503 电源轨
504 虚拟栅极电极
505 导孔
506 金属
507/508 源极/漏极
603 源极/漏极接触。
具体实施方式
在以下描述中，为了说明，提出各种特定细节以提供例示实施例之通透了解。然而，显然例示实施例可无需这些特定细节或以等效配置而实施。在其他情况下，为了免于不必要地混淆例示实施例，已知结构及装置以方块图显示。另外，除了另有指出，表示用于说明书及权利要求书中的组成部分、反应条件等等的数量、比例及数值特性的所有数字应理解在所有情况下藉由词语「约」加以修饰。
本揭露对付并解决在先进技术节点中缩小单元尺寸所遇到的M1设计拥塞的当前问题。藉由使用虚拟栅极作为互连而不须额外的处理步骤，空间在M1设计布线中能被释放。在更多空间变得可以取得之后，M1的颜色能被重新分配且提升可印性。
对所属技术领域的技术人员而言，藉由下列实施方式，其它进一步的态样、特征及技术功效将变得显而易见，其中仅藉由说明所思及的最佳模式而显示并描述较佳实施例。本揭露能有其它及不同的实施例，而其数项细节能在各种明显态样中进行修饰。因此，图式及描述应在本质上视为例示性，而非限制性。
请注意图3，举例而言，多个栅极结构101a,101b形成于基板100上方。栅极结构111形成于单元区域的边缘处的虚拟栅极结构。为了形成栅极接触，藉由蚀刻通过氧化层/介电层105及层间介电质(ILD)109以及盖层115(图1)而产生凹穴110于虚拟栅极结构111上方。凹穴110的形成亦移除最接近该单元区域的边缘的盖层115及侧壁间隔件且仅留下虚拟栅极结构111的其中一个侧壁间隔件。各实际栅极结构101a,101b形成于源极/漏极区域108之间。各虚拟栅极将仅具有一个源极/漏极区域于一侧而其它侧是空的。
图4示意性说明在执行金属填充步骤以产生金属栅极结构之后的单元的PFET及NFET区域中的多个栅极结构的剖面图。在蚀刻介电质、ILD 402及一部分或全部的盖层115(图1)以形成栅极接触沟槽的期间，PFET区域中的虚拟栅极结构411的单元边缘侧上的侧壁间隔件及盖层会被移除而仅留下一个侧壁间隔件。在相同的蚀刻步骤期间，移除在NFET区域中的虚拟栅极结构416的相对单元侧上的侧壁间隔件及盖层会被移除而仅留下一个侧壁间隔件。用于形成栅极接触沟槽及用于移除各虚拟栅极的其中一个侧壁间隔件的蚀刻步骤系氮化物类型蚀刻。而且，在相同的蚀刻期间，亦形成用于实际栅极结构401a,401b(PFET侧)的栅极接触沟槽，但实际栅极结构401a,401b仍保留有侧壁间隔件组。而且，在相同的蚀刻期间，亦形成用于实际栅极结构401c,401d(NFET侧)的栅极接触沟槽，但实际栅极结构401c,401d仍保留有侧壁间隔件组。
用于虚拟栅极结构411,416的栅极接触沟槽是以金属414,417填充以分别形成在PFET及NFET区域的边缘处的栅极结构的栅极接触。再者，用于实际栅极结构401a,401b,401c,401d的接触沟槽亦以金属418填充。对主动区域(即，源极/漏极区域)408的接触是以形成于PFET区域中的邻接STI区域412上方的栅极接触414连接。类似地，对主动区域(即，源极/漏极区域)410的接触是以形成于NFET区域中的邻接STI区域413上方的栅极接触417连接。在各414,415,418,417中的金属相同。金属层415接着在藉由例如化学机械平坦化(CMP)的平坦化技术的沟槽填充之后移除。金属化层能在该CMP之后形成。
请注意图5A，其说明集成电路布线500a。单元501,502设置于电源轨503之间。当虚拟栅极电极504及通向源极/漏极区域的导孔505在图5A的圆圈区域中连接时，在例如506处需要M1。金属506使用导孔505以连接源极漏极505至508。
图5B说明具有虚拟栅极的集成电路布线500b，该虚拟栅极藉由形成连接至单元501,502的圆圈区域中的源极/漏极507的厚(fat)的或移动(shifted)的栅极接触505而用作互连。在507与508之间的连接藉由虚拟栅极及移动的栅极接触505而建立。不再需要金属线。由于虚拟栅极用作互连，在更多空间变得可用之后，M1的颜色可被重新分配。相较于图5A中的布线可改善可印性。
请注意图6，其说明集成电路布线600其中厚或移动的栅极接触601,602形成在虚拟栅极结构上，且连接至源极/漏极接触603。因此，M1颜色已被重新分配。
本揭露的实施例能达到数种技术效果，例如藉由使用虚拟栅极作为互连而减缓在M1设计布线中的拥塞。依据本揭露的实施例所形成的装置在例如微处理器、智慧型手机、行动电话、手机、机上盒、DVD录影机及播放器、汽车导航、印表机和周边、网路和通讯设备、游戏系统及数位相机的各种产业应用上享有多种用途。因此，本揭露在使用虚拟栅极作为互连(特别是10nm、7nm及以上的技术节点)以制造任何各种类型的高度集成的半导体装置上享有产业应用性。
在先前描述中，本揭露参照其具体例示实施例而描述。然而，显然在不悖离权利要求书所阐述的本揭露的广泛精神及范畴下可作出各种修饰及改变。因此，本说明书及图式视为例示性而非限制性。应理解的是，本揭露能使用各种其它组合和实施例且能在如本文表示的发明内容的范畴内作出任何改变或修饰。

Claims (12)

1.一种制作半导体装置的方法，该方法包括：
在半导体基板上于单元边界处形成虚拟栅极结构，各虚拟栅极结构包含一组侧壁间隔件及设于该侧壁间隔件之间的盖层；
移除在第一虚拟栅极结构的第一侧上的第一侧壁间隔件或第一盖层的至少一部分，且在该第一虚拟栅极结构上方形成第一栅极接触沟槽；
移除在第二虚拟栅极结构的第二侧上的第二侧壁间隔件或第二盖层，且在该第二虚拟栅极结构上方形成第二栅极接触沟槽；
以金属填充该第一栅极接触沟槽以形成第一栅极接触以连接具有第一源极/漏极结构的该第一虚拟栅极结构；
以钨、钨合金、铜、铝铜合金或硅铜合金填充该第二栅极接触沟槽以形成第二栅极接触；以及
在该第一与第二虚拟栅极结构之间形成至少一个实际栅极结构。
2.根据权利要求1所述的方法，包括：
在该半导体基板的PFET侧上形成该第一虚拟栅极结构；以及
在该半导体基板的NFET侧上形成该第二虚拟栅极结构。
3.根据权利要求2所述的方法，更包括：
在第一浅沟槽隔离(STI)区域上方形成该第一虚拟栅极结构；以及
在第二浅沟槽隔离(STI)区域上方形成该第二虚拟栅极结构。
4.根据权利要求1所述的方法，包括在该第一及第二虚拟栅极结构上形成该第一栅极接触及第二栅极接触作为移动的栅极接触。
5.根据权利要求4所述的方法，更包括形成低介电系数材料或硅氮化物(SiN)的该第一及第二侧壁间隔件或第一及第二盖层，其中，移除该第一及第二侧壁间隔件或第一及第二盖层包括：
蚀刻在该第一虚拟栅极结构的该第一侧上的该第一侧壁间隔件，以及
蚀刻在该第二虚拟栅极结构的该第二侧上的该第二侧壁间隔件。
6.根据权利要求5所述的方法，其中，该低介电系数材料为硅氧碳氮化物(SiOCN)。
7.根据权利要求1所述的方法，更包括：
在该第一栅极接触及第二栅极接触上方设置金属化层。
8.根据权利要求1所述的方法，更包括：
连接该第一虚拟栅极结构的该第一源极/漏极结构与该第二虚拟栅极结构的第二源极/漏极结构。
9.根据权利要求1所述的方法，其中，该至少一个实际栅极结构设置在源极区域与漏极区域之间。
10.一种制作半导体装置的方法，该方法包括：
在半导体基板上于单元边界处形成虚拟栅极结构，各虚拟栅极结构包含一组侧壁间隔件及设于该侧壁间隔件之间的盖层；
藉由移除在第一虚拟栅极结构的第一侧上的第一侧壁间隔件且蚀刻该第一虚拟栅极结构上方的第一栅极接触沟槽，同时移除在第二虚拟栅极结构的第二侧上的第二侧壁间隔件且蚀刻该第二虚拟栅极结构上方的第二栅极接触沟槽，而形成第一及第二扩张栅极接触沟槽；
形成在该第一及第二虚拟栅极结构之间的实际栅极结构；以及
以钨、钨合金、铜、铝铜合金或硅铜合金填充该第一及第二扩张栅极接触沟槽以形成第一及第二栅极接触，以分别连接具有第一及第二源极/漏极区域的第一及第二虚拟栅极结构。
11.根据权利要求10所述的方法，包括：
在该半导体基板的PFET侧上形成该第一虚拟栅极结构；以及
在该半导体基板的NFET侧上形成该第二虚拟栅极结构。
12.根据权利要求10所述的方法，包括：
在第一浅沟槽隔离(STI)区域上方形成该第一虚拟栅极结构；以及
在第二浅沟槽隔离(STI)区域上方形成该第二虚拟栅极结构。
CN201610404954.8A 2015-06-12 2016-06-08 用作互连的虚拟栅极及其制法 Active CN106252275B (zh)

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