JP2017228659A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017228659A JP2017228659A JP2016123869A JP2016123869A JP2017228659A JP 2017228659 A JP2017228659 A JP 2017228659A JP 2016123869 A JP2016123869 A JP 2016123869A JP 2016123869 A JP2016123869 A JP 2016123869A JP 2017228659 A JP2017228659 A JP 2017228659A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- stress
- semiconductor device
- expansion member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 234
- 239000002184 metal Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 229910000679 solder Inorganic materials 0.000 claims abstract description 55
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 25
- 238000003780 insertion Methods 0.000 claims description 41
- 230000037431 insertion Effects 0.000 claims description 41
- 230000002093 peripheral effect Effects 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
【解決手段】半導体装置100は、半導体素子1と、回路基板2と、金属配線3A〜3Fと、膨張部材5を備える。回路基板2は、上面21と、上面21に対向する下面22とを有する。金属配線3A〜3Fは、上面21及び下面22の少なくとも一方に形成される。半導体素子1において、少なくとも2つの接続端子が、回路基板2の上面21に対向するように配置された端子形成面13に形成される。膨張部材5は、半導体素子1の端子形成面13に固定され、半導体素子1の線膨張係数よりも大きい線膨張係数を有し、少なくとも2つの接続端子のうち互いに隣り合う2つの接続端子よりも大きいサイズを有する。
【選択図】図1
Description
図1は、本発明の第1の実施の形態に係る半導体装置100の構成を示す側面断面図である。図2は、図1に示す回路基板2の底面図である。図3は、図1に示す半導体素子1の底面図である。
図9は、本発明の第2の実施の形態に係る半導体装置200の構成を示す側面断面図である。図10は、図9に示す回路基板2の平面図である。図9及び図10に示す半導体装置200が上記第1の実施の形態に係る半導体装置100と異なる点は、半導体装置200が、膨張部材5に代えて、挿入部材7と膨張部材8とを備える点である。
1 半導体素子
2 回路基板
3A〜3F 金属配線
4 はんだ
5,8 膨張部材
7 挿入部材
11 筐体
12A〜12F 接続端子
13 端子形成面
Claims (7)
- 第1の面と、前記第1の面に対向する第2の面とを有する回路基板と、
前記第1の面及び前記第2の面の少なくとも一方に形成される少なくとも2つの金属配線と、
前記第1の面に対向するように配置された端子形成面において、少なくとも2つの接続端子が形成されている半導体素子と、
前記少なくとも2つの接続端子の各々と前記少なくとも2つの金属配線の各々とを電気的に接続するはんだと、
前記半導体素子の前記端子形成面に固定され、前記半導体素子の線膨張係数よりも大きい線膨張係数を有し、前記少なくとも2つの接続端子のうち互いに隣り合う2つの接続端子の間隔よりも大きいサイズを有する膨張部材と、
を備える半導体装置。 - 請求項1に記載の半導体装置であって、
前記膨張部材が、10〜33×10−6(1/K)の範囲内の線膨張係数を有する半導体装置。 - 請求項2に記載の半導体装置であって、
前記膨張部材は、前記端子形成面に形成された前記少なくとも2つの接続端子を囲む環状形状を有する半導体装置。 - 請求項1ないし請求項3のいずれかに記載の半導体装置であって、
前記膨張部材において前記第1の面に対向する面は、前記第1の面と接触し、
前記膨張部材は、前記回路基板と相対的に移動可能である半導体装置。 - 請求項1に記載の半導体装置であって、
前記膨張部材は、前記金属配線の線膨張係数よりも大きい線膨張係数を有し、
前記膨張部材において前記第1の面に対向する面は、前記第1の面に接触する接触面と、前記第1の面に接触しない非接触面とを有する半導体装置。 - 請求項5に記載の半導体装置であって、さらに、
前記第1の面と前記非接触面との間に挿入され、前記膨張部材の線膨張係数よりも小さい線膨張係数を有する挿入部材、
を備える半導体装置。 - 請求項5に記載の半導体装置であって、
前記膨張部材は、前記端子形成面と対向する面に固定され、
前記挿入部材が前記第1の面と前記非接触面との間に配置される半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016123869A JP6702019B2 (ja) | 2016-06-22 | 2016-06-22 | 半導体装置 |
US15/623,943 US10211135B2 (en) | 2016-06-22 | 2017-06-15 | Semiconductor device |
CN201710474001.3A CN107527872A (zh) | 2016-06-22 | 2017-06-21 | 半导体装置 |
EP17177033.2A EP3261416A1 (en) | 2016-06-22 | 2017-06-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016123869A JP6702019B2 (ja) | 2016-06-22 | 2016-06-22 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2017228659A true JP2017228659A (ja) | 2017-12-28 |
JP2017228659A5 JP2017228659A5 (ja) | 2019-02-28 |
JP6702019B2 JP6702019B2 (ja) | 2020-05-27 |
Family
ID=59101324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016123869A Expired - Fee Related JP6702019B2 (ja) | 2016-06-22 | 2016-06-22 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10211135B2 (ja) |
EP (1) | EP3261416A1 (ja) |
JP (1) | JP6702019B2 (ja) |
CN (1) | CN107527872A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108925039A (zh) * | 2018-06-25 | 2018-11-30 | 维沃移动通信有限公司 | 移动终端、电路板组件及电路板组件的制备方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11631635B2 (en) * | 2020-01-09 | 2023-04-18 | International Business Machines Corporation | Flex prevention mechanical structure such as a ring for large integrated circuit modules and packages and methods of manufacture using same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008311584A (ja) * | 2007-06-18 | 2008-12-25 | Elpida Memory Inc | 半導体パッケージの実装構造 |
JP2012199314A (ja) * | 2011-03-18 | 2012-10-18 | Seiko Epson Corp | 半導体装置、印刷装置、及び製造方法 |
JP2014107490A (ja) * | 2012-11-29 | 2014-06-09 | Kyocera Corp | 電子素子収納用パッケージおよび電子装置 |
WO2015045089A1 (ja) * | 2013-09-27 | 2015-04-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5678356U (ja) * | 1979-11-12 | 1981-06-25 | ||
US5852326A (en) * | 1990-09-24 | 1998-12-22 | Tessera, Inc. | Face-up semiconductor chip assembly |
JPH0897319A (ja) | 1994-09-29 | 1996-04-12 | Toshiba Corp | 電子部品用パッケージ |
JP2000022034A (ja) | 1998-07-01 | 2000-01-21 | Hitachi Ltd | 電子回路装置の接続構造 |
US6734540B2 (en) | 2000-10-11 | 2004-05-11 | Altera Corporation | Semiconductor package with stress inhibiting intermediate mounting substrate |
JP3860000B2 (ja) * | 2001-09-07 | 2006-12-20 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6852926B2 (en) * | 2002-03-26 | 2005-02-08 | Intel Corporation | Packaging microelectromechanical structures |
JP4058642B2 (ja) | 2004-08-23 | 2008-03-12 | セイコーエプソン株式会社 | 半導体装置 |
DE102009009586A1 (de) * | 2009-02-19 | 2010-08-26 | Emitec Gesellschaft Für Emissionstechnologie Mbh | Thermoelektrische Vorrichtung |
-
2016
- 2016-06-22 JP JP2016123869A patent/JP6702019B2/ja not_active Expired - Fee Related
-
2017
- 2017-06-15 US US15/623,943 patent/US10211135B2/en not_active Expired - Fee Related
- 2017-06-21 CN CN201710474001.3A patent/CN107527872A/zh active Pending
- 2017-06-21 EP EP17177033.2A patent/EP3261416A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008311584A (ja) * | 2007-06-18 | 2008-12-25 | Elpida Memory Inc | 半導体パッケージの実装構造 |
JP2012199314A (ja) * | 2011-03-18 | 2012-10-18 | Seiko Epson Corp | 半導体装置、印刷装置、及び製造方法 |
JP2014107490A (ja) * | 2012-11-29 | 2014-06-09 | Kyocera Corp | 電子素子収納用パッケージおよび電子装置 |
WO2015045089A1 (ja) * | 2013-09-27 | 2015-04-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108925039A (zh) * | 2018-06-25 | 2018-11-30 | 维沃移动通信有限公司 | 移动终端、电路板组件及电路板组件的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
JP6702019B2 (ja) | 2020-05-27 |
US20170372990A1 (en) | 2017-12-28 |
EP3261416A1 (en) | 2017-12-27 |
US10211135B2 (en) | 2019-02-19 |
CN107527872A (zh) | 2017-12-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101060862B1 (ko) | 인터포저 및 그의 제조방법 | |
KR101376264B1 (ko) | 적층형 패키지 및 그 제조 방법 | |
US11476199B2 (en) | Package structure | |
EP2400823A1 (en) | Circuit board, circuit board assembly, and semiconductor device | |
JP2013211407A (ja) | 半導体モジュール | |
JP2009071251A (ja) | フリップチップbga基板 | |
JP6702019B2 (ja) | 半導体装置 | |
JP2008227020A (ja) | 電子部品の実装構造 | |
US20190254164A1 (en) | Circuit board, method of manufacturing circuit board, and electronic device | |
CN107818963B (zh) | 半导体装置及半导体装置的制造方法 | |
JP2001230515A (ja) | 電子部品の実装体、電子部品の実装体の製造方法、および実装体の二次実装構造。 | |
KR100752672B1 (ko) | 신뢰성 있는 범프 접속 구조를 갖는 인쇄 회로 기판 및 그제조방법, 및 이를 이용한 반도체 패키지 | |
JP6319477B1 (ja) | モジュール、モジュール製造方法、パッケージ | |
JP2007123545A (ja) | 半導体装置およびその製造方法 | |
JP5217014B2 (ja) | 電力変換装置およびその製造方法 | |
JP5489454B2 (ja) | 積層型半導体パッケージ | |
JP2005123569A (ja) | ウエハの印刷配線基板への実装方法 | |
JP2008277691A (ja) | 両面実装回路基板に対する電子部品の実装構造、半導体装置、及び両面実装半導体装置の製造方法 | |
JP4128722B2 (ja) | 回路基板および電子機器 | |
JP5401498B2 (ja) | 電子装置 | |
JP2005303209A (ja) | ハイブリッドモジュール | |
JP2011035242A (ja) | 多層プリント基板 | |
JP2008300498A (ja) | 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法 | |
JPH11340362A (ja) | 実装基板 | |
JP2006032531A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190118 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190520 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200204 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200131 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200326 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200407 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200420 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6702019 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |