JP2017200292A - 信号伝達回路 - Google Patents
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- B60L2210/00—Converter types
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- B60L2240/00—Control parameters of input or output; Target parameters
- B60L2240/40—Drive Train control parameters
- B60L2240/52—Drive Train control parameters related to converters
- B60L2240/525—Temperature of converter or components thereof
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- B60L2240/00—Control parameters of input or output; Target parameters
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- B60L2240/52—Drive Train control parameters related to converters
- B60L2240/526—Operating parameters
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- B60L2240/00—Control parameters of input or output; Target parameters
- B60L2240/40—Drive Train control parameters
- B60L2240/52—Drive Train control parameters related to converters
- B60L2240/527—Voltage
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- B60L2240/00—Control parameters of input or output; Target parameters
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- B60L2240/52—Drive Train control parameters related to converters
- B60L2240/529—Current
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- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
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- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
- H02P29/02—Providing protection against overload without automatic interruption of supply
- H02P29/024—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
- H02P29/02—Providing protection against overload without automatic interruption of supply
- H02P29/024—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
- H02P29/0241—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load the fault being an overvoltage
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Abstract
【解決手段】駆動回路Dp1〜Dp3,Dn1〜Dn3が検知した異常を表す異常信号を、前記複数の駆動回路Dp1〜Dp3,Dn1〜Dn3から制御装置40へ、複数の磁気カプラMp1〜Mp3,Mn1〜Mn3を介して伝達する信号伝達回路において、複数の磁気カプラMp1〜Mp3,Mn1〜Mn3から異常信号が入力され、複数の駆動回路Dp1〜Dp3,Dn1〜Dn3のうち少なくとも1つが異常を検知した場合に、ハイ状態及びロー状態の二値の一方を表す二値信号によって異常の発生を表す信号を出力する論理回路30を備え、論理回路30の出力は、制御装置40に入力されている。
【選択図】 図5
Description
以下、「電源システム」に適用される「信号伝達回路」をハイブリッド車に適用した実施形態について、図面を参照しつつ説明する。
第2実施形態の磁気カプラMp1〜Mp3,Mn1〜Mn3は、駆動回路Dp1〜Dp3,Dn1〜Dn3から異常を表す異常信号が入力された場合に、それぞれロー状態の信号を出力する。さらに、第2実施形態の論理回路30Aは、AND回路を用いることで、磁気カプラMp1〜Mp3,Mn1〜Mn3の少なくとも1つから異常信号が入力された場合に、制御装置40に対してロー状態の信号を出力する。
第3実施形態の構成を図7に示す。図5に示す第1実施形態の構成と比較すると、本実施形態の論理回路30Bは、「第4の論理素子」であるOR回路On3を備えている。OR回路On3には、磁気カプラMn3の出力と、接地電圧とが入力されている。また、OR回路On3の出力は、OR回路On2に入力されている。これにより、OR回路On3は、磁気カプラMn3の出力をそのままOR回路On2に出力する。
第4実施形態の構成を図8に示す。図6に示す第2実施形態の構成と同様に、第4実施形態の論理回路30Cは、AND回路を備えている。さらに、「第4の論理素子」であるAND回路An3を設けている。
第5実施形態の構成を図10に示す。本実施形態では、磁気カプラMp1〜Mp3がOR回路Op1,Op2から構成される第1の論理回路30Dによって直列接続され、磁気カプラMn1〜Mn3がOR回路On1,On2から構成される第2の論理回路30Eによって直列接続されている。そして、論理回路30D,30Eの出力がそれぞれ独立して制御装置40に入力される。
・OR回路Op1〜Op3,On1,On2の入力側のプルアップを省略する構成としてもよい。OR回路Op1〜Op3,On1,On2の入力側のプルアップを省略する構成では、磁気カプラMp1〜Mp3,Mn1〜Mn3が、駆動回路Dp1〜Dp3,Dn1〜Dn3が異常を検知していない場合、ロー状態の信号を出力し続けなくともよい。
Claims (10)
- 複数の半導体スイッチング素子(SWp1〜SWp3,SWn1〜SWn3)をそれぞれ駆動するとともに、互いに絶縁された複数の駆動回路(Dp1〜Dp3,Dn1〜Dn3)を有する電源システム(INV)に適用され、
前記複数の半導体スイッチング素子にそれぞれ対応する異常を表す異常信号を、前記複数の駆動回路がそれぞれ設けられた1次側の領域から2次側の受信装置(40)へ、複数の絶縁素子(Mp1〜Mp3,Mn1〜Mn3)を介して伝達する信号伝達回路において、
前記複数の絶縁素子は、前記2次側の所定の基準電圧を基準にして、前記異常信号をそれぞれ伝達するものであって、
前記2次側において、前記複数の絶縁素子から前記異常信号が入力され、前記複数の半導体スイッチング素子の少なくとも1つに対応する異常が生じた場合に、異常の発生を表す所定信号を出力する論理回路(30)を備え、
前記論理回路が出力する前記所定信号は、前記受信装置に入力されていることを特徴とする信号伝達回路。 - 前記論理回路は、複数の論理素子(Op1〜Op3,On1,On2,Ap1〜Ap3,An1,An2)を有し、
前記複数の論理素子は、対応する1の前記絶縁素子の出力と、隣り合う1の前記論理素子の出力とが入力される1又は複数の第1の論理素子(Op1〜Op3,On1,Ap1〜Ap3,An1)を含み、
前記第1の論理素子は、出力が前記受信装置に入力される1の第2の論理素子(Op3,Ap3)を含み、
前記複数の論理素子は、対応する2の前記絶縁素子の出力が入力される1の第3の論理素子(On2,An2)を含むことを特徴とする請求項1に記載の信号伝達回路。 - 前記複数の論理素子は、第4の論理素子(On3)を含み、
前記第1の論理素子は、対応する1の前記絶縁素子とともにモジュール化されており、
前記第3の論理素子に対応する2の前記絶縁素子のうち、第1の前記絶縁素子は、前記第3の論理素子とともにモジュール化されており、第2の前記絶縁素子は、前記第4の論理素子とともにモジュール化されるとともに、前記第4の論理素子は、第2の前記絶縁素子の出力をそのまま前記第3の論理素子に対して出力することを特徴とする請求項2に記載の信号伝達回路。 - 前記論理回路として、複数の論理素子(Ap1〜Ap3,An1〜An3)を有し、
前記複数の論理素子は、対応する1の前記絶縁素子の出力と、隣り合う1の前記論理素子の出力とが入力される1又は複数の第1の論理素子(Ap1〜Ap3,An1)を含み、
前記第1の論理素子は、出力が前記受信装置に入力される1の第2の論理素子(Ap3)を含み、
前記複数の論理素子は、対応する2の前記絶縁素子の出力が入力される1の第3の論理素子(An2)と、対応する1の前記絶縁素子の出力と、前記第2の論理素子の出力とが入力される1の第4の論理素子(An3)と、を含み、
前記受信装置は、前記駆動回路に前記半導体スイッチング素子の駆動を指令する駆動指令信号を出力する制御装置であり、
前記絶縁素子は、前記制御装置から対応する前記駆動回路へ駆動指令信号を伝達するものであって、
前記絶縁素子は、対応する前記論理素子の出力に応じて、前記制御装置から対応する前記駆動回路への駆動指令信号の伝達を停止することを特徴とする請求項1に記載の信号伝達回路。 - 前記論理素子は、前記対応する1の絶縁素子とともに、それぞれモジュール化されていることを特徴とする請求項4に記載の信号伝達回路。
- 全ての前記論理素子において、前記第2の論理素子は、対応する前記絶縁素子と前記受信装置との距離が最も近いものであることを特徴とする請求項2乃至5のいずれか1項に記載の信号伝達回路。
- 前記論理回路は、入力がプルダウン又はプルアップされており、前記絶縁素子と前記論理素子との接続、又は、前記論理素子同士の接続において開異常が生じた場合、異常の発生を表す前記所定信号を出力することを特徴とする請求項2乃至6のいずれか1項に記載の信号伝達回路。
- 前記論理回路は、入力がプルダウン又はプルアップされており、前記絶縁素子の出力が停止した場合、異常の発生を表す前記所定信号を出力することを特徴とする請求項1乃至7のいずれか1項に記載の信号伝達回路。
- 前記絶縁素子は、磁気結合型の絶縁素子であることを特徴とする請求項1乃至8のいずれか1項に記載の信号伝達回路。
- 前記複数の半導体スイッチング素子は、インバータ装置(INV)を構成するものであり、直列接続された上アームスイッチング素子(SWp1〜SWp3)と、下アームスイッチング素子(SWn1〜SWn3)とのいずれか一方であって、
前記論理回路として、
複数の前記上アームスイッチング素子に対応する前記複数の絶縁素子から前記異常信号が入力され、複数の前記上アームスイッチング素子の少なくとも1つに対応する異常が生じた場合、異常の発生を表す前記所定信号を出力する第1の論理回路(30A)と、
複数の前記下アームスイッチング素子に対応する前記複数の絶縁素子から前記異常信号が入力され、複数の前記下アームスイッチング素子の少なくとも1つに対応する異常が生じた場合、異常の発生を表す前記所定信号を出力する第2の論理回路(30B)と、
を有し、
前記第1の論理回路の出力、及び、前記第2の論理回路の出力は、それぞれ前記受信装置に入力されていることを特徴とする請求項1乃至9のいずれか1項に記載の信号伝達回路。
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