JP2017195255A - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP2017195255A JP2017195255A JP2016083935A JP2016083935A JP2017195255A JP 2017195255 A JP2017195255 A JP 2017195255A JP 2016083935 A JP2016083935 A JP 2016083935A JP 2016083935 A JP2016083935 A JP 2016083935A JP 2017195255 A JP2017195255 A JP 2017195255A
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Abstract
【解決手段】電力変換装置1の半導体モジュール11は、互いに並列接続され且つ同一のリードフレーム16に設けられたIGBT14及びMOSFET15を備え、リードフレーム16においてIGBT14及びMOSFET15のいずれか一方である第1スイッチング素子の通電経路から外れた位置に他方である第2スイッチング素子が配置されるように構成されている。
【選択図】図3
Description
互いに並列接続され且つ同一のリードフレーム(16,17)に設けられたIGBT(14)及びMOSFET(15)を備え、
上記リードフレームにおいて上記IGBT及び上記MOSFETのいずれか一方である第1スイッチング素子の通電経路から外れた位置に他方である第2スイッチング素子が配置されるように構成されている、半導体モジュール(11)にある。
IGBT(14)及びMOSFET(15)が互いに並列接続されるとともに、電源(B)の高電位側ライン(Lp)と低電位側ライン(Ln)との間に直列に接続され且つ同一のリードフレーム(16,17)に設けられた複数の半導体素子対を備え、
上記複数の半導体素子対に含まれる複数の上記IGBT及び複数の上記MOSFETのいずれか一方である複数の第1スイッチング素子が他方である複数の第2スイッチング素子よりも先に駆動されるとともに、上記複数の半導体素子対のうち上記高電位側ラインと交流出力ライン(Lo)との間に配置される半導体素子対について上記第1スイッチング素子を経由して上記高電位側ラインと上記交流出力ラインとの間に形成される通電経路(Pc)から外れた位置に上記第2スイッチング素子が配置され、上記複数の半導体素子対のうち上記低電位側ラインと上記交流出力ラインとの間に配置される半導体素子対について上記第1スイッチング素子を経由して上記低電位側ラインと上記交流出力ラインとの間に形成される通電経路から外れた位置に上記第2スイッチング素子が配置されるように構成されている、半導体モジュール(111)にある。
なお、特許請求の範囲及び課題を解決する手段に記載した括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものであり、本発明の技術的範囲を限定するものではない。
図1及び図2に示されるように、実施形態1の電力変換装置1は、半導体積層ユニット10及び制御回路基板30を含む複数の要素を備えている。これら複数の要素はケース1aによって区画された空間に収容されている。ケース1aは、軽量且つ高度な寸法精度が要求される自動車部品であり、アルミニウムを使用したアルミダイカスト製法によって作製されている。
また、この熱的影響を抑えることによって、IGBT14及びMOSFET15のそれぞれの性能が向上し、その分、各スイッチング素子の素子サイズを小さくできる。
実施形態2の電力変換装置2は、実施形態1の電力変換装置1に対して、IGBT14及びMOSFET15からなる半導体素子対の数が異なる。即ち、電力変換装置2の半導体モジュール111は、IGBT14及びMOSFET15からなる半導体素子対を2つ備えている。この半導体モジュール111は、IGBT14及びMOSFET15が互いに並列接続された2つの半導体素子対を備えており、これら2つの半導体素子対が電源Bの高電位側ラインLpと低電位側ラインLnとの間に直列に接続されている。この半導体モジュール111は、「2in1モジュール」と称呼される。この半導体モジュール111は、図5中の1つ上アームモジュール11Hと1つの下アームモジュール11Lとを組み合わせた構成を有する。
なお、必要に応じて、3つ以上の半導体素子対を備えた半導体モジュールを採用することもできる。
その他の構成は、実施形態1と同様である。
また、サブ素子である2つのMOSFET15,15を順次経由して高電位側ラインLpと低電位側ラインLnとの間に形成される通電経路に比べてメイン素子である2つのIGBT14,14を順次経由して高電位側ラインLpと低電位側ラインLnとの間に形成される通電経路の方が短くインダクタンスが小さいため、IGBT14によるスイッチング損失を低く抑えることができ、IGBT14の素子サイズを小さくできる。
その他、実施形態1と同様の作用効果を奏する。
11,111 半導体モジュール
11p P端子(第1端子)
11n N端子(第2端子)
11o O端子
14 IGBT
15 MOSFET
16,17 リードフレーム
20 冷却器
24 冷媒流路
B 電源
F,Fa,Fb,Fc,Fd 冷媒の流れ
Lp 高電位側ライン
Ln 低電位側ライン
Lo 交流出力ライン
Pa,Pb,Pc,Pd 通電経路
Claims (9)
- 互いに並列接続され且つ同一のリードフレームに設けられたIGBT及びMOSFETを備え、
上記リードフレームにおいて上記IGBT及び上記MOSFETのいずれか一方である第1スイッチング素子の通電経路から外れた位置に他方である第2スイッチング素子が配置されるように構成されている、半導体モジュール。 - 上記リードフレームから互いに平行に延出した第1端子及び第2端子を備え、
上記IGBT及び上記MOSFETは、上記第1端子及び上記第2端子の延出方向と交差する方向に並んで配置されている、請求項1に記載の半導体モジュール。 - 上記第1スイッチング素子が上記第2スイッチング素子よりも先に駆動されるとともに、上記第1スイッチング素子を経由して上記第1端子と上記第2端子との間に形成される通電経路の長さが、上記第2スイッチング素子を経由して上記第1端子と上記第2端子との間に形成される通電経路の長さを下回るように構成されている、請求項1または2に記載の半導体モジュール。
- 上記リードフレームに対向して延びる冷媒流路を有する冷却器が取付けられ、先に駆動される上記第1スイッチング素子は、上記冷却器の上記冷媒流路における冷媒の流れに対して上記第2スイッチング素子よりも下流側に配置されないように構成されている、請求項3に記載の半導体モジュール。
- 先に駆動される上記第1スイッチング素子は、上記冷却器の上記冷媒流路における冷媒の流れに対して上記第2スイッチング素子よりも上流側に配置されるように構成されている、請求項4に記載の半導体モジュール。
- IGBT及びMOSFETが互いに並列接続されるとともに、電源の高電位側ラインと低電位側ラインとの間に直列に接続され且つ同一のリードフレームに設けられた複数の半導体素子対を備え、
上記複数の半導体素子対に含まれる複数の上記IGBT及び複数の上記MOSFETのいずれか一方である複数の第1スイッチング素子が他方である複数の第2スイッチング素子よりも先に駆動されるとともに、上記複数の半導体素子対のうち上記高電位側ラインと交流出力ラインとの間に配置される半導体素子対について上記第1スイッチング素子を経由して上記高電位側ラインと上記交流出力ラインとの間に形成される通電経路から外れた位置に上記第2スイッチング素子が配置され、上記複数の半導体素子対のうち上記低電位側ラインと上記交流出力ラインとの間に配置される半導体素子対について上記第1スイッチング素子を経由して上記低電位側ラインと上記交流出力ラインとの間に形成される通電経路から外れた位置に上記第2スイッチング素子が配置されるように構成されている、半導体モジュール。 - 上記複数の第1スイッチング素子を順次経由して上記高電位側ラインと上記低電位側ラインとの間に形成される通電経路の長さが、上記複数の第2スイッチング素子を順次経由して上記高電位側ラインと上記低電位側ラインとの間に形成される通電経路の長さを下回るように構成されている、請求項6に記載の半導体モジュール。
- 上記リードフレームに対向して延びる冷媒流路を有する冷却器が取付けられ、上記複数の半導体素子対のそれぞれにおいて先に駆動される上記第1スイッチング素子が上記冷却器の上記冷媒流路における冷媒の流れに対して上記第2スイッチング素子よりも下流側に配置されないように構成されている、請求項6または7に記載の半導体モジュール。
- 上記第1スイッチング素子がSi系材料によって構成された上記IGBTであり、上記第2スイッチング素子がワイドギャップ半導体材料によって構成された上記MOSFETである、請求項1〜8のいずれか一項に記載の半導体モジュール。
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