JP2017135364A - 印刷回路基板およびこれを具備した電子素子パッケージ - Google Patents

印刷回路基板およびこれを具備した電子素子パッケージ Download PDF

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Publication number
JP2017135364A
JP2017135364A JP2016237943A JP2016237943A JP2017135364A JP 2017135364 A JP2017135364 A JP 2017135364A JP 2016237943 A JP2016237943 A JP 2016237943A JP 2016237943 A JP2016237943 A JP 2016237943A JP 2017135364 A JP2017135364 A JP 2017135364A
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Japan
Prior art keywords
insulating layer
circuit pattern
connection pad
electronic device
buried
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Pending
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JP2016237943A
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English (en)
Japanese (ja)
Inventor
チョイ ジェ−ホーン
Jae-Hoon Choi
チョイ ジェ−ホーン
バエク ヨン−ホ
Yong-Ho Baek
バエク ヨン−ホ
ボン カン−ウーク
Kang-Wook Bong
ボン カン−ウーク
リー ジェ−イァン
Jae-Ean Lee
リー ジェ−イァン
キム イエ−ジェオン
Yejeong Kim
キム イエ−ジェオン
キム サン−クン
Sung Koon Kim
キム サン−クン
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of JP2017135364A publication Critical patent/JP2017135364A/ja
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2016237943A 2016-01-29 2016-12-07 印刷回路基板およびこれを具備した電子素子パッケージ Pending JP2017135364A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2016-0011533 2016-01-29
KR1020160011533A KR102582421B1 (ko) 2016-01-29 2016-01-29 인쇄회로기판 및 이를 구비한 전자소자 패키지

Publications (1)

Publication Number Publication Date
JP2017135364A true JP2017135364A (ja) 2017-08-03

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ID=59503013

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JP2016237943A Pending JP2017135364A (ja) 2016-01-29 2016-12-07 印刷回路基板およびこれを具備した電子素子パッケージ

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JP (1) JP2017135364A (ko)
KR (1) KR102582421B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019102522A1 (ja) * 2017-11-21 2019-05-31 株式会社Ｆｕｊｉ ３次元積層電子デバイスの製造方法及び３次元積層電子デバイス
CN110867421A (zh) * 2019-12-23 2020-03-06 无锡青栀科技有限公司 一种集成电路封装结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200142730A (ko) * 2019-06-13 2020-12-23 삼성전기주식회사 인쇄회로기판
KR102609302B1 (ko) 2019-08-14 2023-12-01 삼성전자주식회사 반도체 패키지의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010024233A1 (ja) * 2008-08-27 2010-03-04 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
JP2014049476A (ja) * 2012-08-29 2014-03-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP2015103535A (ja) * 2013-11-21 2015-06-04 イビデン株式会社 プリント配線板
WO2015099684A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Package on package architecture and method for making

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165741A (ja) 2010-02-05 2011-08-25 Renesas Electronics Corp 半導体装置およびその製造方法
KR20120007839A (ko) * 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8531021B2 (en) 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
KR20150092881A (ko) * 2014-02-06 2015-08-17 엘지이노텍 주식회사 인쇄회로기판, 패키지 기판 및 이의 제조 방법
KR101565690B1 (ko) * 2014-04-10 2015-11-03 삼성전기주식회사 회로기판, 회로기판 제조방법, 전자부품 패키지 및 전자부품 패키지 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010024233A1 (ja) * 2008-08-27 2010-03-04 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
JP2014049476A (ja) * 2012-08-29 2014-03-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP2015103535A (ja) * 2013-11-21 2015-06-04 イビデン株式会社 プリント配線板
WO2015099684A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Package on package architecture and method for making

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019102522A1 (ja) * 2017-11-21 2019-05-31 株式会社Ｆｕｊｉ ３次元積層電子デバイスの製造方法及び３次元積層電子デバイス
JPWO2019102522A1 (ja) * 2017-11-21 2020-11-26 株式会社Ｆｕｊｉ ３次元積層電子デバイスの製造方法及び３次元積層電子デバイス
US11458722B2 (en) 2017-11-21 2022-10-04 Fuji Corporation Three-dimensional multi-layer electronic device production method
CN110867421A (zh) * 2019-12-23 2020-03-06 无锡青栀科技有限公司 一种集成电路封装结构

Also Published As

Publication number Publication date
KR102582421B1 (ko) 2023-09-25
KR20170090772A (ko) 2017-08-08

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