JP2016529693A5 - - Google Patents

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Publication number
JP2016529693A5
JP2016529693A5 JP2016520772A JP2016520772A JP2016529693A5 JP 2016529693 A5 JP2016529693 A5 JP 2016529693A5 JP 2016520772 A JP2016520772 A JP 2016520772A JP 2016520772 A JP2016520772 A JP 2016520772A JP 2016529693 A5 JP2016529693 A5 JP 2016529693A5
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JP
Japan
Prior art keywords
solder
solder pad
metal layer
layer
layer portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016520772A
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English (en)
Japanese (ja)
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JP2016529693A (ja
JP6762871B2 (ja
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Publication date
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Priority claimed from PCT/IB2014/061968 external-priority patent/WO2014207590A2/en
Publication of JP2016529693A publication Critical patent/JP2016529693A/ja
Publication of JP2016529693A5 publication Critical patent/JP2016529693A5/ja
Application granted granted Critical
Publication of JP6762871B2 publication Critical patent/JP6762871B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2016520772A 2013-06-24 2014-06-05 平坦化によってはんだパッド形態差を低減する方法 Active JP6762871B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361838457P 2013-06-24 2013-06-24
US61/838,457 2013-06-24
PCT/IB2014/061968 WO2014207590A2 (en) 2013-06-24 2014-06-05 Reducing solder pad topology differences by planarization

Publications (3)

Publication Number Publication Date
JP2016529693A JP2016529693A (ja) 2016-09-23
JP2016529693A5 true JP2016529693A5 (enExample) 2017-06-08
JP6762871B2 JP6762871B2 (ja) 2020-09-30

Family

ID=51022931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016520772A Active JP6762871B2 (ja) 2013-06-24 2014-06-05 平坦化によってはんだパッド形態差を低減する方法

Country Status (7)

Country Link
US (1) US9935069B2 (enExample)
EP (1) EP3014653B1 (enExample)
JP (1) JP6762871B2 (enExample)
KR (1) KR102257933B1 (enExample)
CN (1) CN105308732B (enExample)
TW (2) TW201816905A (enExample)
WO (1) WO2014207590A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3671861A1 (en) * 2018-12-17 2020-06-24 Nexperia B.V. Semiconductor device and electrical contact
US12622284B2 (en) 2023-02-21 2026-05-05 International Business Machines Corporation Solder volume for flip-chip bonding

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56142656A (en) * 1980-04-09 1981-11-07 Fujitsu Ltd Semiconductor device
JP3171477B2 (ja) * 1992-02-26 2001-05-28 株式会社東芝 半導体装置
US5465152A (en) * 1994-06-03 1995-11-07 Robotic Vision Systems, Inc. Method for coplanarity inspection of package or substrate warpage for ball grid arrays, column arrays, and similar structures
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
JPH09312295A (ja) * 1996-03-21 1997-12-02 Matsushita Electric Ind Co Ltd バンプ形成体及びバンプの形成方法
JPH1013007A (ja) 1996-03-29 1998-01-16 Ngk Spark Plug Co Ltd 半田バンプを有する配線基板及びその製造方法及び平坦化治具
JP3244001B2 (ja) * 1996-07-08 2002-01-07 松下電器産業株式会社 ワークの実装方法
US6652764B1 (en) 2000-08-31 2003-11-25 Micron Technology, Inc. Methods and apparatuses for making and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates
JP2002134545A (ja) * 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd 半導体集積回路チップ及び基板、並びにその製造方法
TWI244129B (en) 2002-10-25 2005-11-21 Via Tech Inc Bonding column process
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
JP4140548B2 (ja) * 2004-04-15 2008-08-27 松下電器産業株式会社 バンプ形成装置およびバンプ形成方法
JP2006066689A (ja) * 2004-08-27 2006-03-09 Optrex Corp 半導体素子及びバンプ電極の平坦化方法
TWI317154B (en) * 2006-07-03 2009-11-11 Phoenix Prec Technology Corp Circuit board structure having conductive bumps and method for fabricating conductive bumps on the circuit board structure
KR101079946B1 (ko) * 2006-11-28 2011-11-04 파나소닉 주식회사 전자 부품 실장 구조체와 그 제조 방법
US20080217183A1 (en) * 2007-03-09 2008-09-11 Sriram Muthukumar Electropolishing metal features on a semiconductor wafer
US7800239B2 (en) * 2007-12-14 2010-09-21 Semiconductor Components Industries, Llc Thick metal interconnect with metal pad caps at selective sites and process for making the same
JP2010003793A (ja) * 2008-06-19 2010-01-07 Fujitsu Ltd 配線基板、ポスト電極の転写用基板及び電子機器
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
TWI411075B (zh) * 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
CN101958389A (zh) * 2010-07-30 2011-01-26 晶科电子（广州）有限公司 一种硅基板集成有功能电路的led表面贴装结构及其封装方法
US8536701B2 (en) * 2011-05-03 2013-09-17 Industrial Technology Research Institute Electronic device packaging structure
CN102931111B (zh) * 2012-11-08 2015-06-10 南通富士通微电子股份有限公司 半导体封装结构的形成方法

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