JP2016514419A5 - - Google Patents

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Publication number
JP2016514419A5
JP2016514419A5 JP2015561411A JP2015561411A JP2016514419A5 JP 2016514419 A5 JP2016514419 A5 JP 2016514419A5 JP 2015561411 A JP2015561411 A JP 2015561411A JP 2015561411 A JP2015561411 A JP 2015561411A JP 2016514419 A5 JP2016514419 A5 JP 2016514419A5
Authority
JP
Japan
Prior art keywords
retention
register
voltage source
circuit
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015561411A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016514419A (ja
Filing date
Publication date
Priority claimed from US13/787,666 external-priority patent/US8975934B2/en
Application filed filed Critical
Publication of JP2016514419A publication Critical patent/JP2016514419A/ja
Publication of JP2016514419A5 publication Critical patent/JP2016514419A5/ja
Pending legal-status Critical Current

Links

JP2015561411A 2013-03-06 2014-02-26 低リークリテンションレジスタトレイ Pending JP2016514419A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/787,666 2013-03-06
US13/787,666 US8975934B2 (en) 2013-03-06 2013-03-06 Low leakage retention register tray
PCT/US2014/018811 WO2014137714A1 (en) 2013-03-06 2014-02-26 Low leakage retention register tray

Publications (2)

Publication Number Publication Date
JP2016514419A JP2016514419A (ja) 2016-05-19
JP2016514419A5 true JP2016514419A5 (enExample) 2017-03-02

Family

ID=50240107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015561411A Pending JP2016514419A (ja) 2013-03-06 2014-02-26 低リークリテンションレジスタトレイ

Country Status (6)

Country Link
US (2) US8975934B2 (enExample)
EP (1) EP2965424A1 (enExample)
JP (1) JP2016514419A (enExample)
KR (1) KR20150128801A (enExample)
CN (1) CN105027438B (enExample)
WO (1) WO2014137714A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8975934B2 (en) 2013-03-06 2015-03-10 Qualcomm Incorporated Low leakage retention register tray
US9401711B2 (en) * 2014-11-14 2016-07-26 International Business Machines Corporation Driver output with dynamic switching bias
JP6378142B2 (ja) * 2015-07-08 2018-08-22 株式会社東芝 フリップフロップ回路
US10340899B2 (en) * 2017-02-28 2019-07-02 Texas Instruments Incorporated High performance low retention mode leakage flip-flop

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166985A (en) 1999-04-30 2000-12-26 Intel Corporation Integrated circuit low leakage power circuitry for use with an advanced CMOS process
JP3460713B2 (ja) * 2002-01-11 2003-10-27 株式会社日立製作所 半導体装置
CN1679109B (zh) * 2002-08-28 2011-06-15 Nxp股份有限公司 减小状态保持电路功耗的方法、状态保持电路以及电子器件
US7170327B2 (en) 2003-06-27 2007-01-30 Intel Corporation System and method for data retention with reduced leakage current
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7164301B2 (en) 2005-05-10 2007-01-16 Freescale Semiconductor, Inc State retention power gating latch circuit
US7639056B2 (en) * 2005-05-26 2009-12-29 Texas Instruments Incorporated Ultra low area overhead retention flip-flop for power-down applications
JP4339826B2 (ja) * 2005-07-19 2009-10-07 株式会社ルネサステクノロジ 電子装置
KR100900785B1 (ko) * 2007-05-14 2009-06-02 주식회사 하이닉스반도체 반도체 소자의 내부전압 발생기 및 발생방법
US7652513B2 (en) 2007-08-27 2010-01-26 Texas Instruments Incorporated Slave latch controlled retention flop with lower leakage and higher performance
KR20090027042A (ko) 2007-09-11 2009-03-16 주식회사 동부하이텍 리텐션 기능을 갖는 ｍｔｃｍｏｓ 플립플롭
KR100925394B1 (ko) * 2008-09-25 2009-11-09 주식회사 하이닉스반도체 반도체 메모리 장치
KR101541706B1 (ko) * 2009-01-19 2015-08-05 삼성전자주식회사 온도 감지 발진 회로 및 이를 포함하는 반도체 메모리 장치
KR101612298B1 (ko) 2009-03-13 2016-04-14 삼성전자주식회사 파워 게이팅 회로 및 이를 포함하는 집적 회로
IT1397487B1 (it) * 2010-01-18 2013-01-16 St Microelectronics Pvt Ltd Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo
US8381163B2 (en) * 2010-11-22 2013-02-19 Advanced Micro Devices, Inc. Power-gated retention flops
US8355277B2 (en) * 2011-01-19 2013-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Biasing circuit and technique for SRAM data retention
US8975934B2 (en) 2013-03-06 2015-03-10 Qualcomm Incorporated Low leakage retention register tray

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