IT1397487B1 - Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo - Google Patents

Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo

Info

Publication number
IT1397487B1
IT1397487B1 ITBS2010A000005A ITBS20100005A IT1397487B1 IT 1397487 B1 IT1397487 B1 IT 1397487B1 IT BS2010A000005 A ITBS2010A000005 A IT BS2010A000005A IT BS20100005 A ITBS20100005 A IT BS20100005A IT 1397487 B1 IT1397487 B1 IT 1397487B1
Authority
IT
Italy
Prior art keywords
retention
data
flop circuit
low consumption
consumption flip
Prior art date
Application number
ITBS2010A000005A
Other languages
English (en)
Inventor
Abhishek Jain
Pankaj Rohilla
Andrea Mario Veggetti
Original Assignee
St Microelectronics Pvt Ltd
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Pvt Ltd, St Microelectronics Srl filed Critical St Microelectronics Pvt Ltd
Priority to ITBS2010A000005A priority Critical patent/IT1397487B1/it
Priority to EP10197058.0A priority patent/EP2348634B1/en
Priority to US13/008,588 priority patent/US8330518B2/en
Publication of ITBS20100005A1 publication Critical patent/ITBS20100005A1/it
Priority to US13/689,476 priority patent/US8570085B2/en
Application granted granted Critical
Publication of IT1397487B1 publication Critical patent/IT1397487B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dc Digital Transmission (AREA)
ITBS2010A000005A 2010-01-18 2010-01-18 Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo IT1397487B1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
ITBS2010A000005A IT1397487B1 (it) 2010-01-18 2010-01-18 Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo
EP10197058.0A EP2348634B1 (en) 2010-01-18 2010-12-27 Low consumption flip-flop circuit with data retention and method thereof
US13/008,588 US8330518B2 (en) 2010-01-18 2011-01-18 Low consumption flip-flop circuit with data retention and method thereof
US13/689,476 US8570085B2 (en) 2010-01-18 2012-11-29 Low consumption flip-flop circuit with data retention and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITBS2010A000005A IT1397487B1 (it) 2010-01-18 2010-01-18 Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo

Publications (2)

Publication Number Publication Date
ITBS20100005A1 ITBS20100005A1 (it) 2011-07-19
IT1397487B1 true IT1397487B1 (it) 2013-01-16

Family

ID=42269623

Family Applications (1)

Application Number Title Priority Date Filing Date
ITBS2010A000005A IT1397487B1 (it) 2010-01-18 2010-01-18 Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo

Country Status (3)

Country Link
US (2) US8330518B2 (it)
EP (1) EP2348634B1 (it)
IT (1) IT1397487B1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9283334B2 (en) 2011-11-23 2016-03-15 Northgate Technologies Inc. System for identifying the presence and correctness of a medical device accessory
CN103795393B (zh) 2012-10-26 2018-12-11 恩智浦美国有限公司 状态保持电源门控单元
US8975934B2 (en) * 2013-03-06 2015-03-10 Qualcomm Incorporated Low leakage retention register tray
US9172379B1 (en) * 2014-09-26 2015-10-27 Altera Corporation Efficient controllers and implementations for elastic buffers
US9312834B1 (en) 2015-01-08 2016-04-12 Freescale Semiconductors,Inc. Low leakage flip-flop circuit
US9641160B2 (en) 2015-03-02 2017-05-02 Intel Corporation Common N-well state retention flip-flop
US10340899B2 (en) * 2017-02-28 2019-07-02 Texas Instruments Incorporated High performance low retention mode leakage flip-flop
KR102460575B1 (ko) * 2017-12-21 2022-10-31 에스케이하이닉스 주식회사 증폭 회로, 이를 이용하는 주파수 분주 회로, 반도체 장치 및 반도체 시스템
US20210184657A1 (en) * 2019-12-11 2021-06-17 Silicon Laboratories Inc. Apparatus for Asynchronous Latch with Improved Performance and Associated Methods
US11152921B1 (en) * 2021-03-17 2021-10-19 Qualcomm Incorporated Systems and methods for control signal latching in memories

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030188241A1 (en) * 2002-03-29 2003-10-02 International Business Machines Corporation CMOS low leakage power-down data retention mechanism
ATE335276T1 (de) * 2002-08-28 2006-08-15 Koninkl Philips Electronics Nv Verfahren zur verringerung der stromaufnahme in einer zustandshalteschaltung, zustandshalteschaltung und elektronische einrichtung
US6850103B2 (en) * 2002-09-27 2005-02-01 Texas Instruments Incorporated Low leakage single-step latch circuit
US6762638B2 (en) * 2002-10-16 2004-07-13 International Business Machines Corporation Circuit for preserving data in a flip-flop and a method of use
US6775180B2 (en) * 2002-12-23 2004-08-10 Intel Corporation Low power state retention
US7183825B2 (en) * 2004-04-06 2007-02-27 Freescale Semiconductor, Inc. State retention within a data processing system
US7187205B2 (en) * 2005-02-25 2007-03-06 Freescale Semiconductor, Inc. Integrated circuit storage element having low power data retention and method therefor
KR100692590B1 (ko) * 2005-02-25 2007-03-13 삼성전자주식회사 분수-ｎ 주파수 합성 장치를 위한 시그마-델타 변조기의 안정화 장치 및 방법
US7138842B2 (en) 2005-04-01 2006-11-21 Freescale Semiconductor, Inc. Flip-flop circuit having low power data retention
US7639056B2 (en) 2005-05-26 2009-12-29 Texas Instruments Incorporated Ultra low area overhead retention flip-flop for power-down applications
JP4846272B2 (ja) * 2005-06-07 2011-12-28 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US7652513B2 (en) * 2007-08-27 2010-01-26 Texas Instruments Incorporated Slave latch controlled retention flop with lower leakage and higher performance
US7583121B2 (en) * 2007-08-30 2009-09-01 Freescale Semiconductor, Inc. Flip-flop having logic state retention during a power down mode and method therefor
JP2009060560A (ja) * 2007-09-04 2009-03-19 Fujitsu Microelectronics Ltd マスタスレーブ回路及びその制御方法
US7710177B2 (en) * 2007-09-12 2010-05-04 Freescale Semiconductor, Inc. Latch device having low-power data retention
US7791389B2 (en) * 2008-01-30 2010-09-07 Freescale Semiconductor, Inc. State retaining power gated latch and method therefor
US8271226B2 (en) * 2008-06-26 2012-09-18 Cadence Design Systems, Inc. Testing state retention logic in low power systems
US7961502B2 (en) * 2008-12-04 2011-06-14 Qualcomm Incorporated Non-volatile state retention latch

Also Published As

Publication number Publication date
EP2348634A1 (en) 2011-07-27
ITBS20100005A1 (it) 2011-07-19
US20110176653A1 (en) 2011-07-21
US20130088272A1 (en) 2013-04-11
US8570085B2 (en) 2013-10-29
EP2348634B1 (en) 2014-03-19
US8330518B2 (en) 2012-12-11

Similar Documents

Publication Publication Date Title
IT1397487B1 (it) Circuito a flip-flop a basso consumo con ritenzione del dato, e relativo metodo
HK1218329A1 (zh) 型糖尿病生物標誌物及其用途
EP2867834A4 (en) MANAGEMENT AND PARTICULAR ORIENTATION OF INVENTORY WITH INCREASED IMAGE
EP2939078A4 (en) BATTERY PRESERVATION AND USE OF DATA
PT2991944T (pt) Substrato dotado de um empilhamento de propriedades térmicas
IL243652A0 (en) Architecture computing with peripherals
EP2986211A4 (en) DISTINCTION BETWEEN CENTRAL AND OBSTRUCTIVE SLEEP APNEA
HK1213286A1 (zh) 具有集成照明的反應器
EP2840574A4 (en) MEMORY SWITCHING WITH BISTABLE CIRCUIT AND NON-VOLATILE ELEMENT
GB201317148D0 (en) Computer game with physics element
IL230288A0 (en) A sensor with reduced energy consumption
PL3072308T3 (pl) Miernik zużycia z korekcją błędów
HK1215975A1 (zh) 數據組裝、傳送和存儲
EP2845097A4 (en) MODIFIED JVM WITH APPLICATION DOMAINS WITH MULTIPLE OWNERS AND MEMORY MANAGEMENT
EP2973591A4 (en) Crdm with separate scram latch engagement and locking
GB2529573B (en) Circuit card assembly with thermal energy removal
HK1201991A1 (en) Integrated circuit stack with low profile contacts
EP3060117A4 (en) Electronic management of sleep related data
EP2701239A4 (en) CONNECTION STRUCTURE WITH USB INTERFACE AND DATA CARD
GB201603947D0 (en) Document-based search with facet information
EP2973592A4 (en) Crdm with separate scram latch engagement and locking
ITTO20130670A1 (it) Substrato cellulosico con proprieta' antifiamma e relativo procedimento di produzione
GB2527010B (en) A primary memory module with a record of usage history and applications of the primary memory module to a computer system
EP3014033A4 (en) Roll-out structure with self-tightening feature
EP2650890A4 (en) CAPACITOR, HOUSER FOR CAPACITOR, AND SUBSTRATE WITH CIRCUIT