JP2016510954A5 - - Google Patents

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Publication number
JP2016510954A5
JP2016510954A5 JP2016500312A JP2016500312A JP2016510954A5 JP 2016510954 A5 JP2016510954 A5 JP 2016510954A5 JP 2016500312 A JP2016500312 A JP 2016500312A JP 2016500312 A JP2016500312 A JP 2016500312A JP 2016510954 A5 JP2016510954 A5 JP 2016510954A5
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JP
Japan
Prior art keywords
feature
substrate
negative
layer
negative feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016500312A
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English (en)
Japanese (ja)
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JP2016510954A (ja
JP6311003B2 (ja
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Publication date
Priority claimed from US13/838,602 external-priority patent/US8896112B2/en
Application filed filed Critical
Publication of JP2016510954A publication Critical patent/JP2016510954A/ja
Publication of JP2016510954A5 publication Critical patent/JP2016510954A5/ja
Application granted granted Critical
Publication of JP6311003B2 publication Critical patent/JP6311003B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2016500312A 2013-03-15 2014-02-20 マルチチップモジュール（ｍｃｍ）及びそれを作製するための方法並びにシステム Active JP6311003B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/838,602 US8896112B2 (en) 2013-03-15 2013-03-15 Multi-chip module with self-populating positive features
US13/838,602 2013-03-15
PCT/US2014/017389 WO2014149338A1 (en) 2013-03-15 2014-02-20 Multi-chip module with self-populating positive features

Publications (3)

Publication Number Publication Date
JP2016510954A JP2016510954A (ja) 2016-04-11
JP2016510954A5 true JP2016510954A5 (enExample) 2017-03-02
JP6311003B2 JP6311003B2 (ja) 2018-04-11

Family

ID=50240013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016500312A Active JP6311003B2 (ja) 2013-03-15 2014-02-20 マルチチップモジュール（ｍｃｍ）及びそれを作製するための方法並びにシステム

Country Status (6)

Country Link
US (1) US8896112B2 (enExample)
EP (1) EP2973670B1 (enExample)
JP (1) JP6311003B2 (enExample)
CN (1) CN105144359B (enExample)
TW (1) TWI549255B (enExample)
WO (1) WO2014149338A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
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US9496238B2 (en) 2015-02-13 2016-11-15 Advanced Semiconductor Engineering, Inc. Sloped bonding structure for semiconductor package
US9470855B1 (en) * 2015-08-11 2016-10-18 Oracle International Corporation Self-assembled vertically aligned multi-chip module
US9773741B1 (en) * 2016-08-17 2017-09-26 Qualcomm Incorporated Bondable device including a hydrophilic layer
US20200234928A1 (en) * 2019-01-17 2020-07-23 Applied Materials, Inc. Semiconductor plasma processing equipment with wafer edge plasma sheath tuning ability

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US5681634A (en) * 1995-02-15 1997-10-28 Matsushita Electric Industrial Co., Ltd. Optical information medium, and method and apparatus for fabricating the same
US6114221A (en) * 1998-03-16 2000-09-05 International Business Machines Corporation Method and apparatus for interconnecting multiple circuit chips
US6965166B2 (en) 1999-02-24 2005-11-15 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure
US6645432B1 (en) * 2000-05-25 2003-11-11 President & Fellows Of Harvard College Microfluidic systems including three-dimensionally arrayed channel networks
US7086134B2 (en) * 2000-08-07 2006-08-08 Shipley Company, L.L.C. Alignment apparatus and method for aligning stacked devices
US20020196440A1 (en) * 2000-12-14 2002-12-26 Steinberg Dan A. Structure for aligning chips in stacked arrangement
KR100662491B1 (ko) * 2000-12-27 2007-01-02 엘지.필립스 엘시디 주식회사 면발광 램프 및 그 제조방법
US6974604B2 (en) 2001-09-28 2005-12-13 Hrl Laboratories, Llc Method of self-latching for adhesion during self-assembly of electronic or optical components
US7870788B2 (en) * 2002-01-25 2011-01-18 Kinemetrics, Inc. Fabrication process and package design for use in a micro-machined seismometer or other device
KR100383383B1 (en) * 2002-06-22 2003-05-16 Fionix Inc Method for fabricating optical fiber block
US6874950B2 (en) * 2002-12-17 2005-04-05 International Business Machines Corporation Devices and methods for side-coupling optical fibers to optoelectronic components
US8426720B2 (en) * 2004-01-09 2013-04-23 Industrial Technology Research Institute Micro thermoelectric device and manufacturing method thereof
FR2878843B1 (fr) * 2004-12-02 2007-07-20 Saint Gobain Substrat protege contre les pollutions organiques
US7592707B2 (en) 2005-10-03 2009-09-22 Sun Microsystems, Inc. Method and apparatus for facilitating proximity communication and power delivery
JP4640643B2 (ja) * 2005-11-08 2011-03-02 日本電気硝子株式会社 光ファイバアレイ用基板及びその製造方法
CN100541784C (zh) * 2005-11-10 2009-09-16 沈育浓 堆叠式半导体芯片封装体
US7550846B2 (en) 2005-12-21 2009-06-23 Palo Alto Research Center Conductive bump with a plurality of contact elements
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US8384630B2 (en) * 2007-05-31 2013-02-26 Nthdegree Technologies Worldwide Inc Light emitting, photovoltaic or other electronic apparatus and system
US7893531B2 (en) * 2007-09-28 2011-02-22 Oracle America, Inc. Integrated-circuit package for proximity communication
US8076178B2 (en) * 2007-09-28 2011-12-13 Oracle America, Inc. Self-assembly of micro-structures
US7651021B2 (en) 2007-12-28 2010-01-26 Intel Corporation Microball attachment using self-assembly for substrate bumping
JP2009175504A (ja) * 2008-01-25 2009-08-06 Fujifilm Corp 光ファイバ構造体
JP2011044496A (ja) 2009-08-19 2011-03-03 Panasonic Corp 半導体デバイス及びそれを用いた半導体装置
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US8487429B2 (en) * 2009-09-22 2013-07-16 Oracle America, Inc. Assembly of multi-chip modules using sacrificial features
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