TWI549255B - 具有自填充正特徵之多晶片模組 - Google Patents
具有自填充正特徵之多晶片模組 Download PDFInfo
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- TWI549255B TWI549255B TW103107240A TW103107240A TWI549255B TW I549255 B TWI549255 B TW I549255B TW 103107240 A TW103107240 A TW 103107240A TW 103107240 A TW103107240 A TW 103107240A TW I549255 B TWI549255 B TW I549255B
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Classifications
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Description
本揭示發明通常相關於多晶片模組(MCM)及用於製造MCM的技術。更具體地說,本揭示發明相關於包括藉由使用親水及疏水層自填充至基板中之負特徵中的正特徵的MCM。
工程師最近已建議使用多晶片模組(MCM)以積集半導體晶片的3維(3D)堆疊。與此種MCM關聯的主要挑戰係將該等晶片彼此對準。
對準晶片的一方式使用正特徵(諸如,球形球)以將MCM中的晶片之相向表面上的負特徵對(諸如,孔)機器地耦接。該等正特徵可能特別與負特徵對相配,從而將該等晶片彼此對準及耦接。
然而,將正特徵置於負特徵中可係昂貴且消耗時間的。例如,可使用取放配件技術以在製造MCM期間將正特徵置入負特徵中,但該處理典型地緩慢,可顯著地增加MCM的成本。
因此,所需要的係免於遭受上述問題的MCM及製造技術。
本揭示發明的一實施例提供包括具有第一表面之第一基板的多晶片模組(MCM)。此第一基板包括:設置在該第一表面上的第一負特徵,其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口;及設置在該等第一負特徵中的第一層,其中該第一層包括親水材料。再者,該MCM包括:設置在該等第一負特徵中之該第一層上的正特徵,其中該等正特徵凸出在該第一表面上方;及具有面對該第一表面之第二表面的第二基板,其中該第二基板包括設置在該第二表面上的第二負特徵。須注意經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口。此外,將該等第二負特徵耦接至該等正特徵,使得該第一基板機器地耦接至該第二基板。
在部分實施例中,該等正特徵包括球形球。再者,該等第一負特徵及該等第二負特徵可能包括孔。
此外,該第一層可能包括二氧化矽。
此外,該第一基板可能包括設置在圍繞該等第一負特徵之該第一表面的區域中的第二層,其中該第二層包括疏水材料。例如,該第二層可能包括聚矽氧。此第二層可能具有少於1nm的厚度。
再者,該第一基板可能包括半導體(諸如,矽)並可能具有側壁角。此側壁角可能對應於該半導體的對稱面。例如,可能從晶圓液壓切割該第一基板。
另一實施例提供包括該MCM的系統。
另一實施例可能用於製造該MCM的方法。在該方法期間,將第一負特徵界定在第一基板的第一表面上,其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口。然後,將第一層設置在該等第一負特徵中,其中該第一層包括親水材料。其次,將第二層設置在圍繞該等第一負特徵之該第一表面的區域中的第一表面上,其中該第二層包括疏水材料。再者,將正特徵放置在該等第一負特徵中的該第一層上,其中該等正特徵凸出在該第一表面上方。此外,將第二負特徵界定在第二基板之面對該第一表面的第二表面上,其中經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口。此外,將該等第二負特徵機器地耦接至該等正特徵,使得該第一基板機器地耦接至該第二基板。
在部分實施例中,在將該等第二負特徵機器地耦接至該等正特徵之前,從晶圓液壓切割該第一基板。另外,在將該等第二負特徵機器地耦接至該等正特徵之前,可能將第二層移除。
100、810‧‧‧MCM
110、114‧‧‧基板
112-1、112-2‧‧‧表面
116-1、118-1‧‧‧負特徵
120‧‧‧親水層
122‧‧‧疏水層
124-1、124-2‧‧‧正特徵
126‧‧‧側壁角
800‧‧‧系統
900‧‧‧方法
d1‧‧‧中央間隙
d2‧‧‧周圍間隙
圖1係描繪根據本揭示發明的實施例之多晶
片模組(MCM)的方塊圖。
圖2係描繪根據本揭示發明的實施例之表面張力計算的圖。
圖3係描繪根據本揭示發明的實施例之將球填充至孔中的圖。
圖4係描繪根據本揭示發明的實施例之將球填充至孔中的圖。
圖5係描繪根據本揭示發明的實施例之基板製造的圖。
圖6係描繪根據本揭示發明的實施例之圖5中的基板製造的圖。
圖7係描繪根據本揭示發明的實施例之基板的液壓切割的圖。
圖8係描繪根據本揭示發明的實施例之系統的方塊圖。
圖9係描繪根據本揭示發明的實施例之用於製造MCM的方法的流程圖。
須注意在該等圖式各處,相似參考數字參考至對應部分。再者,相同類型部分的多個實例可能以藉由破折號與實例數字分隔的共同前置數字指定。
描述多晶片模組(MCM)、包括MCM的系統、及製造MCM之技術的實施例。此MCM包括至少二基
板,該等基板藉由在該等基板之相對表面上的正及負特徵機器地耦接及對準。此等正特徵及負特徵可能相配並彼此自鎖。此等正特徵可能使用該負特徵中的親水層自填充入在該等基板之至少一者上的該等負特徵中。此親水層可能結合圍繞在該等基板之至少一者的頂表面上的該等負特徵的疏水層使用。
此機器耦接技術可能與高量製造相容。可能特別使用半導體處理技術將該等正及負特徵製造在表面上。因此,可能顯著地降低MCM的成本。
現在描述MCM的實施例。圖1呈現描繪MCM 100的方塊圖。此MCM包括,具有表面112-1的基板110,及具有面對表面112-1之表面112-2的基板114。例如,基板110及114二者可能均係晶片,或可能係其他組件。
基板110可能包括設置在表面112-1上的負特徵116,其中經給定負特徵(諸如,負特徵116-1)凹陷在表面112-1下方並具有由邊緣界定的開口。相似地,基板114可能包括設置在表面112-2上的負特徵118,其中經給定負特徵(諸如,負特徵118-1)凹陷在表面112-2下方並具有由邊緣界定的開口。如圖1所描繪的,負特徵116及118可能包括孔。
再者,負特徵116可能包括親水層120,同時可能有圍繞負特徵116的選擇性疏水層122在表面112-1上。如更於下文描述的,此等層可能容許在製造MCM
100期間將正特徵124自填充入負特徵116中。正特徵124(諸如,球形球)可能部分地包括在負特徵116中。正特徵124的其餘部分可能凸出在表面112-1上方並可能與對應負特徵118相配。以此方式,正特徵124可能機器地對準(具有次微米準確性)及耦接基板110及114。
在範例實施例中,親水層120具有10nm的厚度,且選擇性疏水層122具有少於1nm的厚度(諸如,單層)。再者,親水層120可能包括二氧化矽、且選擇性疏水層122可能包括聚矽氧(諸如,聚二甲基矽氧烷或PDMS)。
在部分實施例中,正特徵124及負特徵116及118也可能電耦接基板110及114,包括:電源、接地、及/或輸入/輸出訊號。然而,在部分實施例中,電耦接係藉由與提供機器耦接之特徵分離的特徵(未圖示)提供。
須注意基板110及114的機器耦接可能係可重配對的。例如,基板110及114的機器耦接可能藉由將基板110及114拉開,或藉由溶解將基板110及114保持在一起的黏合劑而釋放。此可能容許MCM 100在製造或後續測試期間反修。然而,在部分實施例中,該機器耦接係不可重配對的。例如,正特徵124可能,至少一部分可能在MCM 100的製造及組裝期間回流。
MCM 100中的組件可能與晶圓級批次處理相容,其可能顯著地降低製造及組裝MCM 100的成本。
在範例實施例中,疏水及親水型樣可能用於實現大尺寸的球在孔中自填充,以促進MCM中的次微米晶片-對-晶片對準。可能將可能具有非親水或疏水表面(諸如,金或藍寶石)的球形對準球分散在CMOS-相容溶液中(諸如,去離子水),並可能將目標晶圓/晶片之表面上的蝕刻孔處理成具有親水表面狀況。然後,可能將去離子水-球溶液載入填充頭中。如參考圖3及4更於下文描述的,當具有分散球的去離子水量經過該等孔時,藉由掃描或液滴頭技術的任一者,與未填充孔重疊的球可能落入並可能藉由表面張力抓在親水孔中。掃描頭上或填充目標晶片上的疏水區域可能用於將去離子水-球溶液限制在預定孔內,並可能強化填充頭的引導能力及效率及防止整體暴露表面潮濕。此外,此等疏水層可能防止或減少該等球或微球體的非必要遺失或散佈。在填充後,可能將未填充球留在目標晶圓/晶片的疏水表面上。如參考圖7更於下文描述的,可能使用聚矽氧(諸如,PDMS)液壓切割基板載置及液壓切割具有附接在背側上之紫外光敏感膠帶的已填充球於孔中的晶圓,以實現免切塊晶片單切。
因此,球在孔中自填充可使用親水孔及疏水場區的組合實現。此表面張力輔助球在孔中填充技術可能在晶圓或晶片尺寸上使用,並可能提供用於製造及組裝MCM的低成本解決方案。
可估計將填充球抬出孔的平均最小力,以驗證表面張力大至足力將球保持在孔中。具體地說,圖2顯
示在親水孔內側之單一球的繪圖,其中些微水量使孔側壁及球潮濕並在填充期間將其保持在位置中。為驗證表面張力是否大至足以將球保持在孔內側,計算將球抬出孔所需要的平均最小力。平均最小力F係特別從將球抬起距離LCF所需要的能量(Elift)估計,亦即,
其中σ係去離子水的表面張力且SHIJG係球上的表面積。若F遠大於作用在球上的重力G,則表面張力大至足以將球保持在孔內側。須注意將球材料的接觸角假設為90°。若球的直徑係188μm且孔開口係216μm,經計算的最小抬起力為球上重力的183倍大。因為表面張力大到足以將球保持在孔內側,即使晶片上下翻轉,經填充球可不落出。此計算係基於填充後場景,亦即,球已座落於孔中。在填充期間,球散佈在溶液中,其與填充後場景完全不同,且沒有表面張力將彼等拉出。如先前提及的,球在孔中填充可能藉由下列方式實現:橫跨目標孔掃描填充浸在去離子水中的球;或使用所謂的「液滴頭」。在二技術中,散佈在去離子水中的疏水球可能在彼等將填充的孔上方受引導或移動。
如圖3所示,關於該掃描技術,去離子水中的球可能藉由掃描頭引導並可能橫跨該孔的表面或目標晶圓移動。當此掃描頭在孔或孔陣列上方移動時,越過未填充孔之任何部分的球可能由於來自該孔內側之水的表面張力而為該親水孔所捕捉或抓取。再者,位在疏水場區上的
球可能隨受引導的水柱移開,因此留下無障礙場區。
如圖4所示,關於液滴技術,包含球及去離子水的液滴頭可能與孔陣列對準,然後朝下移動以接觸並將球降入親水孔中。或者,液滴頭可能首先朝下移動以接觸孔晶圓的疏水場區,然後橫跨短距離橫向地掃描以發現並將球降入彼等的對應孔中。此短掃描輔助液滴技術可能將液滴頭及晶圓上的目標孔之間所需的對準精確度降低。在將球降入彼等目標孔中之後,液滴頭可能從孔移開(例如,至少數十或數百微米),使得未填充孔的球來與圍繞孔的疏水場區接觸。在此短橫向移動之後,然後可能將液滴頭從晶圓/晶片表面抬離以分斷水柱與孔晶圓。再次,此可能降低球散佈或非企圖之球遺失在目標表面上的風險。因此,不在孔內側的球可能由水柱的表面張力所保持並從晶片攜離。
除了在目標晶圓上使用型樣疏水層外,須注意可能有疏水區在面對目標晶圓之表面上的填充頭上(諸如,圖3的掃描頭或圖4的液適頭)以改善效能。除了此疏水表面外,也可能使用與填充頭及目標晶圓之間的間隙成反比的毛細管力,以將去離子水限制在填充頭上的開口周圍。藉由增加間隙,毛細管力可能減少,其可能容許將水區域化在填充頭周圍。然而,此組態可能導致多層球導引在填充頭下。此等球層可能彼此干擾並可能降低良率。因此,也可能使用具有正底開口的填充頭。特別係中央間隙d1可能小於用於防止過潮濕之相對較大的周圍間隙
d2,且因此在該等孔受填充時球過堆疊。例如,針對200μm直徑的球,d2可能約500μm。此外,可能調整填充頭使得其平行於目標晶圓的表面。此可能確保該等水導引球係在均勻毛細管力下填充。
該疏水表面改質可能藉由衝印處理製造,並可能選擇地藉由短乾蝕刻處理移除。光微影處理與衝印處理的組合可能容許經製造結構適用於批次製造,且因此適於低成本製造。如圖5及6所示,彼等呈現描繪基板之製造的圖式,該製造處理可能包括:製造具有疏水/親水型樣的孔晶圓;及以球填充孔。隨後,如圖7所示,該晶圓可能使用具有微射流通道的彈性基板液壓切割。
在圖5及6中,可能使用雙側氮化矽塗佈將負光阻旋塗在矽晶圓上,並可能使用光微影型樣化以產生光阻開口。然後,可能使用氮化物乾蝕刻以產生濕蝕刻硬遮罩。該孔陣列及切割線可能藉由光阻剝除及氫氧化四甲銨(TMAH)矽濕蝕刻產生。其次,可能將用於濕蝕刻的氮化矽硬遮罩移除,並可能藉由二氧化矽雷射強化化學氣相沈積或熱氧化的任一者將親水層(諸如,二氧化矽)形成在晶圓的表面上,並特別形成在孔內側。再者,可能藉由衝印處理將疏水PDMS寡聚合物層轉移至晶圓場區的表面上(且因此可能設置在表面上而無需使用光微影)。例如,水及PDMS寡聚合物層之間的接觸角可能約90°。因為孔係負結構,孔內側的親水表面可能在衝印處理期間不受影響。此時,具有親水孔及疏水場區的晶圓可能準備好用於
表面張力輔助球填充。
一旦球填充處理結束,疏水PDMS寡聚合物層可能藉由短乾蝕刻選擇性地大幅或完全移除。特別係該PDMS寡聚合物層在乾蝕刻之前可能具有約5-10nm的厚度,並可能在乾蝕刻之後具有單層厚度或更少。因為PDMS的乾蝕刻率遠高於二氧化矽及球(具有金或藍寶石表面)的蝕刻率,短乾蝕刻處理可能對下方的矽晶圓沒有任何副作用。在乾蝕刻後,水及矽晶圓表面之間的接觸角可能遠小於90°(亦即,該表面可能不再疏水)。因此,所有該等暴露晶圓場區,且特別係焊墊區域對後續處理清理可能係乾淨的。
在將球填充在晶圓級之後,可能使用液壓切割技術單切晶片,與習知切塊操作相反。此顯示於圖7中,其呈現描繪基板之液壓切割的圖式。特別係可能沿著晶片間的單切邊界將作為切割線的淺長蝕刻孔製造在晶圓的前側上。然後可能將具有切割線的球填充晶圓對準及載置在包含嵌入微射流通道的彈性基板的頂部上。當微流射通道內側的液壓增加時,流射通道及晶圓之間的可變形薄膜可能彎曲。此偏轉可能將均勻切割力施加在切割線下方,導致其將整體晶圓切割及分離為個別晶片。附接在晶圓背側上的紫外光敏感膠帶或黏合劑可能在切割期間用於釋放衝擊或應力,並可能在液壓切割後將晶片保持在彼等的原始位置上。在紫外光敏感膠帶上以背側紫外光曝光約10分鐘後,經分離晶片可從膠帶去除。以此方式,可將
晶片從晶圓單切而不破壞球或正特徵(亦即,不將彼等從負特徵敲出)。
參考回圖1,基板110可能具有指示從晶圓液壓切割其的特徵。特別係基板110可能包括半導體(諸如,矽)並可能具有側壁角126。此側壁角可能對應於半導體的對稱面(諸如,與90°相對的54.7°)。此外,沿著相鄰於切割線之基板110的表面的粗糙度可能少於切塊後的表面粗糙度。
具有使用在液壓切割中的微流射通道的彈性基板可能藉由將具有開口通道的底PDMS片與頂膜黏合在一起而製造。例如,具有開口通道的底片可能藉由將PDMS片成型在具有光阻通道型樣之矽基板的頂部而製造。頂PDMS膜可能藉由將PDMS旋轉塗佈在以肥皂水預處理的另一晶圓上而得到,其可能使膜的後續剝除變得容易。在二片上的氧電漿處理之後,可能將具有開口通道的底PDMS片載置在PDMS膜的頂部上。然後,具有微流射通道的PDMS基板可能藉由將二黏合片從晶圓剝除而得到。
可能將該MCM之上述實施例的一或多者包括在系統及/或電子裝置中。此顯示於圖8中,其呈現包括MCM 810之系統800的方塊圖。通常,MCM可能包括晶片模組(CM)陣列或單晶片模組(SCM),且經給定的SCM可能包括至少一基板,諸如,半導體晶粒。須注意有時將MCM稱為「巨集晶片」。此外,該基板可能使用電磁耦
合訊號的鄰近通訊(其稱為「電磁鄰近通訊」)與該MCM中的其他基板、CM、及/或SCM通訊。例如,該鄰近通訊可能包括:電容耦合訊號通訊(「電鄰近通訊」)及/或光學訊號通訊(諸如,「光學鄰近通訊」)。在部分實施例中,電磁鄰近通訊包括電感耦合訊號及/或導電耦合訊號。
此外,該MCM的實施例可能使用在各種應用中,包括:VLSI電路、通訊系統(諸如,在波長分割多工中)、儲存區域網路、資料中心、網路(諸如,區域網路)、及/或電腦系統(諸如,多核心處理器電腦系統)。例如,該MCM可能包括在耦接至刀鋒式多處理器的背板中,或該MCM可能耦接不同種類的組件(諸如,處理器、記憶體、輸入/輸出裝置、及/或周邊裝置)。在部分實施例中,該MCM實施下列功能:交換器、集線器、橋接器、及/或路由器。
須注意電腦系統800可能包括,但未受限於:伺服器、膝上型電腦、通訊裝置或系統、個人電腦、平板電腦、行動電話、工作站、大型電腦、刀鋒型電腦、娛樂電腦、資料中心、可攜式計算裝置、超級電腦、網路附接儲存(NAS)系統、儲存區域網路(SAN)系統、及/或其他電子計算裝置。再者,須注意給定的電腦系統可能在一位置或可能散佈在多個地理分散位置。
上述實施例中的MCM可能包括較少組件或額外組件。例如,可能將圖1中的負特徵116界定在沈積在
表面112-1上的層中,且此等負特徵可能凹陷在沈積於基板110上之頂層的表面下方。相似地,圖1中的正特徵124可能凸出在區域表面上方,其可能係表面112-1或沈積在基板110上之頂層的表面。因此,在上述實施例中,應將基板的表面理解成包括沈積在基板上之層的表面或該基板自身的表面。
再者,雖然將此等實施例說明成具有多個離散項目,將此等MCM及系統視為係可能存在之各種特性的功能描述而非本文描述之實施例的結構概要。因此,在此等實施例中,可能將二或多個組件組合入單一組件中及/或可能改變一或多個組件的位置。
須注意圖1中的正特徵124及圖1中的負特徵116及118可能使用添加處理(亦即,材料沈積)及/或減除處理(亦即,材料移除)界定。例如,該處理可能包括:濺鍍、各向同性蝕刻、各向異性蝕刻、光微影技術、及/或直接寫入技術。此外,此等特徵可能使用各式各樣材料製造,包括:半導體、金屬、玻璃、藍寶石、及/或二氧化矽。
現在描述方法的實施例。圖9呈現用於製造MCM,諸如,MCM 100(圖1)之方法900的流程圖。在此方法期間,將第一負特徵界定在第一基板的第一表面上(操作910),其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口。然後,將第一層設置在第一負特徵中,其中該第一層包括親水材料(操作
912)。其次,將第二層設置在圍繞第一負特徵的該第一表面之區域中的第一表面上,其中該第二層包括疏水材料(操作914)。再者,將正特徵放置在該等第一負特徵中的該第一層上(操作916),其中該等正特徵凸出在該第一表面上方。此外,將第二負特徵界定在第二基板之面對該第一表面的第二表面上(操作918),其中經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口。此外,將該等第二負特徵機器地耦接至該等正特徵(操作924),使得該第一基板機器地耦接至該第二基板。
在部分實施例中,在將第二負特徵機器地耦接至正特徵之前(操作924),可能將第二層選擇性地移除(操作920)。此外,在將第二負特徵機器地耦接至正特徵之前(操作924),可能選擇性地從晶圓液壓切割第一基板(操作922)。
在處理900的部分實施例中,有額外或較少操作。再者,操作的次序可能改變,及/或將二或多個操作組合成單一操作。
將以上描述視為致能任何熟悉本發明之人士製造及使用本揭示發明,並將其提供在特定應用及其必要條件的上下文中。再者,已僅針對說明及描述之目的於上文呈現本揭示發明之實施例的描述。不將彼等視為係徹底揭示或將本揭示發明限制在已揭示之形式。因此,許多修改及變化對熟悉本技術的從業人士將係明顯的,並可能將本文界定的通用原理施用至其他實施例及應用而不脫離本
揭示發明的精神及範圍。此外,上述實施例的討論未意圖限制本揭示發明。因此,本揭示發明無意受限於已顯示的該等實施例,而待給予與本文所揭示之該等原理及特性符合的最廣寬範圍。
100‧‧‧MCM
110、114‧‧‧基板
112-1、112-2‧‧‧表面
116-1、116-2、118-1、118-2‧‧‧負特徵
120‧‧‧親水層
122‧‧‧疏水層
124-1、124-2‧‧‧正特徵
126‧‧‧側壁角
Claims (18)
- 一種多晶片模組(MCM),包含:具有第一表面的第一基板,其中該第一基板包括:設置在該第一表面上的第一負特徵,其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口;及設置在該等第一負特徵中的第一層,其中該第一層包括親水材料;設置在該等第一負特徵中之該第一層上的正特徵,其中該等正特徵凸出在該第一表面上方;及具有面對該第一表面之第二表面的第二基板,其中該第二基板包括設置在該第二表面上的第二負特徵,其中經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口;其中將該等第二負特徵耦接至該等正特徵,使得該第一基板機器地耦接至該第二基板其中該第一基板包括半導體並具有側壁角;且其中該第一基板的該側壁角對應於該半導體的對稱面。
- 如申請專利範圍第1項的MCM,其中該等正特徵包括球形球。
- 如申請專利範圍第1項的MCM,其中該等第一負特徵及該等第二負特徵包括孔。
- 如申請專利範圍第1項的MCM,其中該第一基板 更包含設置在圍繞該等第一負特徵之該第一表面的區域中的第二層,其中該第二層包括疏水材料。
- 如申請專利範圍第4項的MCM,其中該第二層具有少於1nm的厚度。
- 如申請專利範圍第4項的MCM,其中該第二層包括聚矽氧。
- 如申請專利範圍第1項的MCM,其中該第一層包括二氧化矽。
- 一種系統,包含:處理器;記憶體,儲存組態成由該處理器執行的程式模組;及MCM,其中該MCM包括:具有第一表面的第一基板,其中該第一基板包括:設置在該第一表面上的第一負特徵,其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口;及設置在該等第一負特徵中的第一層,其中該第一層包括親水材料;設置在該等第一負特徵中之該第二層上的正特徵,其中該等正特徵凸出在該第一表面上方;及具有面對該第一表面之第二表面的第二基板,其中該第二基板包括設置在該第二表面上的第二負特徵,其中經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口;且 其中將該等第二負特徵耦接至該等正特徵,使得該第一基板機器地耦接至該第二基板其中該第一基板包括半導體並具有側壁角;且其中該第一基板的該側壁角對應於該半導體的對稱面。
- 如申請專利範圍第8項的系統,其中該等正特徵包括球形球。
- 如申請專利範圍第8項的系統,其中該等第一負特徵及該等第二負特徵包括孔。
- 如申請專利範圍第8項的系統,其中該第一基板更包含設置在圍繞該等第一負特徵之該第一表面的區域中的第二層,其中該第二層包括疏水材料。
- 如申請專利範圍第11項的系統,其中該第二層具有少於1nm的厚度。
- 如申請專利範圍第11項的系統,其中該第二層包括聚矽氧。
- 如申請專利範圍第8項的系統,其中該第一層包括二氧化矽。
- 一種用於製造MCM的方法,包含:將第一負特徵界定在第一基板的第一表面上,其中經給定的第一負特徵凹陷在該第一表面下方並具有由第一邊緣界定的第一開口;將第一層設置在該等第一負特徵中,其中該第一層包括親水材料; 將第二層設置在圍繞該等第一負特徵之該第一表面的區域中,其中該第二層包括疏水材料;將正特徵放置在該等第一負特徵中的該第一層上,其中該等正特徵凸出在該第一表面上方;將第二負特徵界定在第二基板之面對該第一表面的第二表面上,其中經給定的第二負特徵凹陷在該第二表面下方並具有由第二邊緣界定的第二開口;且將該等第二負特徵機器地耦接至該等正特徵,使得該第一基板機器地耦接至該第二基板,其中該第一基板包括半導體並具有側壁角;且其中該第一基板的該側壁角對應於該半導體的對稱面。
- 如申請專利範圍第15項的方法,其中,在將該等第二負特徵機器地耦接至該等正特徵之前,該方法更包含從晶圓液壓切割該第一基板。
- 如申請專利範圍第15項的方法,其中,在將該等第二負特徵機器地耦接至該等正特徵之前,該方法更包含移除該第二層。
- 如申請專利範圍第15項的方法,其中該等正特徵包括球形球,且該等第一負特徵及該等第二負特徵包括孔。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9496238B2 (en) | 2015-02-13 | 2016-11-15 | Advanced Semiconductor Engineering, Inc. | Sloped bonding structure for semiconductor package |
US9470855B1 (en) * | 2015-08-11 | 2016-10-18 | Oracle International Corporation | Self-assembled vertically aligned multi-chip module |
US9773741B1 (en) * | 2016-08-17 | 2017-09-26 | Qualcomm Incorporated | Bondable device including a hydrophilic layer |
US20200234928A1 (en) * | 2019-01-17 | 2020-07-23 | Applied Materials, Inc. | Semiconductor plasma processing equipment with wafer edge plasma sheath tuning ability |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030146518A1 (en) * | 1999-02-24 | 2003-08-07 | Junichi Hikita | Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface |
US6645432B1 (en) * | 2000-05-25 | 2003-11-11 | President & Fellows Of Harvard College | Microfluidic systems including three-dimensionally arrayed channel networks |
US20110278718A1 (en) * | 2010-05-17 | 2011-11-17 | Oracle International Corporation | Assembly of multi-chip modules using reflowable features |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57126139A (en) * | 1981-01-27 | 1982-08-05 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
US5006201A (en) * | 1989-11-22 | 1991-04-09 | Eastman Kodak Company | Method of making a fiber optic array |
US5681634A (en) * | 1995-02-15 | 1997-10-28 | Matsushita Electric Industrial Co., Ltd. | Optical information medium, and method and apparatus for fabricating the same |
US6114221A (en) * | 1998-03-16 | 2000-09-05 | International Business Machines Corporation | Method and apparatus for interconnecting multiple circuit chips |
US7086134B2 (en) * | 2000-08-07 | 2006-08-08 | Shipley Company, L.L.C. | Alignment apparatus and method for aligning stacked devices |
US20020196440A1 (en) * | 2000-12-14 | 2002-12-26 | Steinberg Dan A. | Structure for aligning chips in stacked arrangement |
KR100662491B1 (ko) * | 2000-12-27 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | 면발광 램프 및 그 제조방법 |
US6974604B2 (en) | 2001-09-28 | 2005-12-13 | Hrl Laboratories, Llc | Method of self-latching for adhesion during self-assembly of electronic or optical components |
US7870788B2 (en) * | 2002-01-25 | 2011-01-18 | Kinemetrics, Inc. | Fabrication process and package design for use in a micro-machined seismometer or other device |
KR100383383B1 (en) * | 2002-06-22 | 2003-05-16 | Fionix Inc | Method for fabricating optical fiber block |
US6874950B2 (en) * | 2002-12-17 | 2005-04-05 | International Business Machines Corporation | Devices and methods for side-coupling optical fibers to optoelectronic components |
US8426720B2 (en) * | 2004-01-09 | 2013-04-23 | Industrial Technology Research Institute | Micro thermoelectric device and manufacturing method thereof |
FR2878843B1 (fr) * | 2004-12-02 | 2007-07-20 | Saint Gobain | Substrat protege contre les pollutions organiques |
US7592707B2 (en) | 2005-10-03 | 2009-09-22 | Sun Microsystems, Inc. | Method and apparatus for facilitating proximity communication and power delivery |
JP4640643B2 (ja) * | 2005-11-08 | 2011-03-02 | 日本電気硝子株式会社 | 光ファイバアレイ用基板及びその製造方法 |
CN100541784C (zh) * | 2005-11-10 | 2009-09-16 | 沈育浓 | 堆叠式半导体芯片封装体 |
US7550846B2 (en) | 2005-12-21 | 2009-06-23 | Palo Alto Research Center | Conductive bump with a plurality of contact elements |
KR100723532B1 (ko) * | 2006-06-19 | 2007-05-30 | 삼성전자주식회사 | 도전성 범프 형성용 몰드, 그 몰드 제조방법, 및 그몰드를 이용한 웨이퍼에 범프 형성방법 |
US8456393B2 (en) * | 2007-05-31 | 2013-06-04 | Nthdegree Technologies Worldwide Inc | Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system |
US7893531B2 (en) * | 2007-09-28 | 2011-02-22 | Oracle America, Inc. | Integrated-circuit package for proximity communication |
US8076178B2 (en) | 2007-09-28 | 2011-12-13 | Oracle America, Inc. | Self-assembly of micro-structures |
US7651021B2 (en) | 2007-12-28 | 2010-01-26 | Intel Corporation | Microball attachment using self-assembly for substrate bumping |
JP2009175504A (ja) * | 2008-01-25 | 2009-08-06 | Fujifilm Corp | 光ファイバ構造体 |
JP2011044496A (ja) | 2009-08-19 | 2011-03-03 | Panasonic Corp | 半導体デバイス及びそれを用いた半導体装置 |
WO2011026136A1 (en) * | 2009-08-31 | 2011-03-03 | Life Technologies Corporation | Low-volume sequencing system and method of use |
US8487429B2 (en) * | 2009-09-22 | 2013-07-16 | Oracle America, Inc. | Assembly of multi-chip modules using sacrificial features |
US8188581B2 (en) | 2009-09-28 | 2012-05-29 | Oracle America, Inc. | Mechanical coupling in a multi-chip module using magnetic components |
US8218334B2 (en) * | 2010-03-09 | 2012-07-10 | Oracle America, Inc. | Multi-chip module with multi-level interposer |
US8564137B2 (en) * | 2010-11-05 | 2013-10-22 | Stmicroelectronics, Inc. | System for relieving stress and improving heat management in a 3D chip stack having an array of inter-stack connections |
US8659161B2 (en) * | 2011-06-21 | 2014-02-25 | Oracle International Corporation | Chip package with reinforced positive alignment features |
-
2013
- 2013-03-15 US US13/838,602 patent/US8896112B2/en active Active
-
2014
- 2014-02-20 CN CN201480014639.3A patent/CN105144359B/zh active Active
- 2014-02-20 JP JP2016500312A patent/JP6311003B2/ja active Active
- 2014-02-20 EP EP14709066.6A patent/EP2973670B1/en active Active
- 2014-02-20 WO PCT/US2014/017389 patent/WO2014149338A1/en active Application Filing
- 2014-03-04 TW TW103107240A patent/TWI549255B/zh active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030146518A1 (en) * | 1999-02-24 | 2003-08-07 | Junichi Hikita | Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface |
US6645432B1 (en) * | 2000-05-25 | 2003-11-11 | President & Fellows Of Harvard College | Microfluidic systems including three-dimensionally arrayed channel networks |
US20110278718A1 (en) * | 2010-05-17 | 2011-11-17 | Oracle International Corporation | Assembly of multi-chip modules using reflowable features |
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