CN105144359B - 具有自填充阳性特征的多芯片模块 - Google Patents

具有自填充阳性特征的多芯片模块 Download PDF

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CN105144359B
CN105144359B CN201480014639.3A CN201480014639A CN105144359B CN 105144359 B CN105144359 B CN 105144359B CN 201480014639 A CN201480014639 A CN 201480014639A CN 105144359 B CN105144359 B CN 105144359B
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substrate
female aspect
layer
female
positive classification
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CN105144359A (zh
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H·D·塞科
A·V·克里什纳莫西
J·E·坎宁安
张朝齐
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Oracle International Corp
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Oracle International Corp
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Abstract

描述了多芯片模块(MCM)。这种MCM包括至少两个基板，其中基板通过基板的面对的表面上的阳性特征和阴性特征机械耦合并对准。这些阳性特征和阴性特征可以彼此配对并自锁定。阳性特征可以利用阴性特征中的亲水层自填充到至少一个基板上的阴性特征中。这种亲水层可以结合包围至少一个基板的顶表面上的阴性特征的疏水层来使用。

Description

具有自填充阳性特征的多芯片模块
技术领域
本公开内容一般而言涉及多芯片模块(MCM)和用于构造MCM 的技术。更具体而言，本公开内容涉及包括阳性特征的MCM，其中 阳性特征通过利用亲水层和疏水层自填充到基板中的阴性特征中。
背景技术
工程师最近提出利用多芯片模块(MCM)来集成半导体芯片的 3维(3D)堆叠。与这种MCM关联的主要挑战是关于彼此对准芯片。
对准芯片的一种方法是用阳性特征(诸如球形滚珠)机械耦合 MCM中芯片的面对的表面上的阴性特征(诸如坑)对。特别地，阳 性特征可以与阴性特征对配对，由此彼此对准并耦合芯片。
但是，在阴性特征中定位阳性特征会是昂贵且耗时的。例如，拾 取和放置组装技术可以被用来在MCM构造期间把阳性特征放在阴性 特征中，但是该过程通常慢，这会显著增加MCM的成本。
因此，所需要的是不受上述问题困扰的MCM和构造技术。
发明内容
本公开内容的一种实施例提供了包括具有第一表面的第一基板的 多芯片模块(MCM)。这第一基板包括：布置在第一表面上的第一 阴性特征，其中给定的第一阴性特征凹入第一表面之下并且具有由第 一边缘限定的第一开口；以及布置在第一阴性特征中的第一层，其中 该第一层包括亲水材料。此外，MCM包括：布置在第一阴性特征中 第一层上的阳性特征，其中该阳性特征突出到第一表面之上；以及具 有面向第一表面的第二表面的第二基板，其中第二基板包括布置在第 二表面上的第二阴性特征。应当指出，给定的第二阴性特征凹入第二 表面之下并且具有由第二边缘限定的第二开口。此外，第二阴性特征 耦合到阳性特征，使得第一基板机械耦合到第二基板。
在一些实施例中，阳性特征包括球形滚珠。此外，第一阴性特征 和第二阴性特征可以包括坑。
此外，第一层可以包括二氧化硅。
此外，第一基板可以包括布置在第一表面上的包围第一阴性特征 的区域中的第二层，其中第二层包括疏水材料。例如，第二层可以包 括硅树脂。这个第二层可以具有小于1nm的厚度。
此外，第一基板可以包括半导体(诸如硅)，并且可以具有侧壁 角。这个侧壁角可以对应于半导体的对称平面。例如，第一基板可以 从晶片液压劈开。
另一种实施例提供了包括MCM的系统。
另一种实施例提供了用于构造MCM的方法。在该方法中，在第 一基板的第一表面上限定第一阴性特征，其中给定的第一阴性特征凹 入第一表面之下并且具有由第一边缘限定的第一开口。然后，在第一 阴性特征中布置第一层，其中该第一层包括亲水材料。接下来，在第 一表面上的包围第一阴性特征的区域中布置第二层，其中第二层包括 疏水材料。此外，在第一阴性特征中的第一层上布置阳性特征，其中 阳性特征突出到第一表面之上。此外，在第二基板的第二表面上限定 第二阴性特征，该第二表面面向第一表面，其中给定的第二阴性特征 凹入第二表面之下并且具有由第二边缘限定的第二开口。此外，第二 阴性特征机械耦合到阳性特征，使得第一基板机械耦合到第二基板。
在一些实施例中，在把第二阴性特征机械耦合到阳性特征之前， 第一基板从晶片液压劈开。此外，在把第二阴性特征机械耦合到阳性 特征之前，第二层可以被除去。
附图说明
图1是示出根据本公开内容实施例的多芯片模块(MCM)的框 图。
图2是示出根据本公开内容实施例的表面张力计算的图。
图3是示出根据本公开内容实施例在坑中填充滚珠的图。
图4是示出根据本公开内容实施例在坑中填充滚珠的图。
图5是示出根据本公开内容实施例的基板构造的图。
图6是示出根据本公开内容实施例的图5基板构造的图。
图7是示出根据本公开内容实施例的基板的液压劈开的图。
图8是示出根据本公开内容实施例的系统的框图。
图9是示出根据本公开内容实施例、用于构造MCM的方法的流 程图。
应当指出，贯穿附图，相同的标号指对应的部分。此外，相同类 型的部分的多个实例由用虚线与实例号隔开的共同前缀表示。
具体实施方式
描述了多芯片模块(MCM)的实施例，包括MCM的系统，以 及用于构造MCM的技术。这种MCM包括至少两个基板，其中基板 通过基板的面对的表面上的阳性特征和阴性特征机械耦合并对准。这 些阳性特征和阴性特征可以彼此配对并自锁定。阳性特征可以利用阴 性特征中的亲水层自填充到至少一个基板上的阴性特征中。这种亲水 层可以结合至少一个基板的顶表面上的包围阴性特征的疏水层来使用。
这种机械耦合技术可以与大批量制造兼容。特别地，阳性特征和 阴性特征可以利用半导体工艺技术在表面上构造。因此，MCM的成 本可以显著降低。
我们现在描述MCM的实施例。图1给出了说明MCM 100的框 图。这个MCM包括：具有表面112-1的基板110、具有面向表面 112-1的表面112-2的基板114。例如，基板110和114都可以是芯 片，或者可以是其它部件。
基板110可以包括布置在表面112-1上的阴性特征116，其中给 定的阴性特征(诸如阴性特征116-1)凹入表面112-1之下并且具有 由边缘限定的开口。类似地，基板114可以包括布置在表面112-2上 的阴性特征118，其中给定的阴性特征(诸如阴性特征118-1)凹入表面112-2之下并且具有由边缘限定的开口。如图1中所说明的，阴 性特征116和118可以包括坑。
此外，阴性特征116可以包括亲水层120，同时可以有可选的包 围表面112-1上阴性特征116的疏水层122。如以下进一步描述的， 这些层可以允许在MCM 100的构造期间，阳性特征124自填充到阴 性特征116中。阳性特征124(诸如球形滚珠)可以部分地包含在阴性特征116中。阳性特征124的剩余部分可以突出到表面112-1之上， 并且可以与对应的阴性特征118配对。以这种方式，阳性特征124可 以机械对准(具有亚微米的准确度)并且耦合基板110和114。
在示例性实施例中，亲水层120具有10nm的厚度，并且可选 的疏水层122具有小于1nm的厚度(诸如单层)。此外，亲水层 120可以包括二氧化硅，并且可选的疏水层122可以包括硅树脂(诸 如聚二甲基硅氧烷或者PDMS)。
在一些实施例中，阳性特征124以及阴性特征116和118还可以 电耦合基板110和114，包括：电力、接地，和/或输入/输出信号。 但是，在一些实施例中，电耦合是通过与提供机械耦合的那些特征不 同的特征(未示出)来提供的。
应当指出，基板110和114的机械耦合可以是可重新配对的。例 如，基板110和114的机械耦合可以通过把基板110和114拉开，或 者通过溶解把110和114保持到一起的粘合剂，来释放。这可以允许 MCM 100在构造期间或后续的测试期间被再加工。但是，在一些实施例中，机械耦合是不可重新配对的。例如，阳性体征124可以至少 部分地在MCM 100的构造和组装期间回流。
MCM 100中的部件可以与晶片级的批处理兼容，这可以显著降 低构造和组装MCM100的成本。
在示例性实施例中，疏水图案和亲水图案可以被用来实现大规模 的滚珠入坑的自填充，以促进MCM中亚微米的芯片到芯片对准。可 以具有非疏水或亲水表面(诸如金或蓝宝石)的球形对准滚珠可以分 散在与CMOS兼容的溶液(诸如去离子水)中，并且在目标晶片/芯 片的表面上的蚀刻坑可以被处理为具有亲水表面条件。然后，去离子 水-滚珠溶液可以装载到填充头中。如以下参考图3和4进一步描述 的，当具有分散的滚珠的去离子水穿过坑时，或者通过扫描或者通过 滴头技术，与未填充的坑重叠的滚珠可以落入其中并且可以通过表面 张力被抓在亲水坑中。扫描头上和填充目标芯片上的疏水区域可以被 用来把去离子水-滚珠溶液限定到预期的坑中，并且可以增强填充头 的导向能力和效率并且防止整个暴露表面的打湿。此外，这些疏水层 可以防止或降低滚珠或微球体的不必要丢失或散落。在填充之后，没 有未被填充的滚珠会留在目标晶片/芯片的疏水表面上。如以下参考图7进一步描述的，具有附连到背侧的紫外线敏感带的滚珠入坑填充 的晶片可以被安装并且利用硅树脂(诸如PDMS)液压劈开基板来液 压劈开，以实现无切割的芯片切单(singulation)。
因此，可以利用亲水坑和疏水现场区域的组合来实现滚珠入坑的 自填充。这种表面张力辅助的滚珠入坑填充技术可以在晶片或芯片级 使用，并且可以为构造和组装MCM提供低成本的解决方案。
可以估计把所填充的滚珠提出坑的平均最小力，以验证表面张力 大到足以把滚珠保持在坑内。具体而言，图2示出了在亲水坑内的单 个滚珠的说明，其中微量水打湿坑的侧壁和滚珠，并且在填充过程中 把滚珠保持在适当位置。为了验证表面张力是否大到足以把滚珠保持 在坑内，我们计算把滚珠提出坑所需的平均最小力。特别地，该平均 最小力F是从把滚珠提升距离LCF所需的能量(Elift)来估计的，即：
其中σ是去离子水的表面张力，并且SHIJG是滚珠上的表面积。如果 F比作用在滚珠上的重力G大得多，则表面张力大到足以把滚珠保持在坑内。应当指出，滚珠材料的接触角被假设为是90°。如果滚珠的直径是188μm并且坑的开口是216μm，则计算出的最小提升力比滚珠上的重力大183倍。因为表面张力大到足以把滚珠保持在坑内，所以，即使芯片翻过来，所填充的滚珠也不会掉出来。这种计算是基 于填充后的场景，即，滚珠已经位于坑内。在填充期间，球分散在溶 液中，这与填充后的场景完全不同，并且没有表面张力把它们拉出来。如前面所指出的，滚珠入坑填充可以通过以下来实现：跨目标坑扫描 浸入去离子水中的大量滚珠；或者利用所谓的“滴头”。在这两种技 术中，分散在去离子水中的非疏水滚珠都可以被引导或移动至它们将 填充的坑之上。
如图3中所示，对于扫描技术，去离子水中的滚珠可以由扫描头 引导，并且可以跨坑或目标晶片的表面移动。当这种扫描头在坑或坑 的阵列之上移动时，跨过未填充的坑的任何部分的滚珠会由于来自坑 内水的表面张力而被亲水坑抓住或捕捉。此外，位于疏水现场区域上 的滚珠会随着被引导的水柱移开，由此留下干净的现场区域。
如图4中所示，对于滴落技术，包含滚珠和去离子水的滴头可以 与坑阵列对准，然后向下移动，以便接触并把滚珠滴落到亲水坑中。 作为替代，滴头可以首先向下移动，以接触坑晶片的疏水现场区域， 然后可以跨短距离被侧向扫描，以找出并把滚珠滴落到其对应的坑内。 这种短扫描辅助的滴落技术会降低滴头与晶片上目标坑之间所需的对 准准确度。在把滚珠滴落到其目标坑内之后，滴头可以从坑移开(例 如，移开至少几十或几百微米)，使得未填充坑的滚珠与包围坑的疏 水现场区域接触。在这个短侧向移动之后，滴头可以从晶片/芯片表 面抬离，以便把水柱与坑晶片断开。再次，这可以减小目标表面上滚 珠散落或非预期的滚珠丢失的风险。因此，不在坑内的滚珠可以通过 水柱的表面张力被保持并带离芯片。
除了使用目标晶片上的图案疏水层，应当指出，还可以在面向目 标晶片的表面上的填充头(诸如图3的扫描头或者图4的滴头)上有 疏水区域，以改进性能。除了这个疏水表面，毛细力也可以被用来在 填充头上开口周围限定去离子水，其中毛细力与填充头和目标晶片之 间的间隙成反比。通过增加间隙，毛细力会减小，这可以允许水在填 充头周围局部化。但是，这种配置会导致多层滚珠被引导在填充头下 面。这些滚珠层会彼此干扰并且会降低产量。因此，具有阳性底部开 口的填充头也可以被使用。特别的，中心间隙d1可以小于被用来防 止过湿并且因此在坑被填充时造成滚珠的过渡堆叠的相对较大周围间 隙d2。例如，对于200μm直径的滚珠，d2可以近似为500μm。此 外，填充头可以被调节，使得它与目标晶片的表面平行。这可以确保 被水引导的滚珠在均匀的毛细力下被填充。
疏水表面修改可以经由压印工艺来构造并且可以可选地通过短干 蚀刻工艺被除去。光刻工艺连同压印工艺的组合可以允许构造好的结 构适于批量构造并且，因此，适于低成本制造。如给出说明基板构造 的图的图5和6中所示，构造过程可以包括：构造具有疏水/亲水图 案的坑晶片；并且利用滚珠填充坑。随后，如图7中所示，可以利用 带微流体通道的弹性体基板来液压劈开晶片。
在图5和6中，阴性光刻胶可以利用双侧硅-氮涂覆旋涂到硅晶 片上，并且可以利用光刻法构图，以产生光刻胶开口。然后，氮干蚀 刻可以被用来创建湿蚀刻硬掩膜。坑阵列和劈开线可以通过光刻胶分 条和四甲基氢氧(TMAH)硅湿蚀刻来产生。接下来，用于湿蚀刻的 硅-氮硬掩膜可以被除去，并且亲水层(诸如二氧化硅)可以通过或 者二氧化硅等离子体增强的化学气相沉积或者热氧化在晶片的表面上， 并且尤其是在坑的内部，形成。此外，疏水PDMS低聚物层可以通 过压印过程转移到晶片现场区域的表面上(并且，因此，可以不利用 光刻法而布置在表面上)。例如，水与PDMS低聚物层之间的接触 角可以近似为90°。因为坑是阴性结构，所以坑内的亲水表面在压印 过程中可以不受影响。在这个时候，具有亲水坑和疏水现场区域的晶 片可以准备好进行表面张力辅助的滚珠填充。
一旦滚珠填充过程完成，疏水PDMS低聚物层就可以可选地大 部分或完全被短干蚀刻除去。特别地，PDMS低聚物层可以在干蚀刻 之前具有大约5-10nm的厚度，并且可以在干蚀刻之后具有单层厚度 或更小。因为PDMS的干蚀刻率比二氧化硅和滚珠(具有金或蓝宝石表面)的蚀刻率高得多，所以短干蚀刻不会对下面的硅晶片具有任 何副作用。在干蚀刻之后，水与硅晶片的表面之间的接触角可以比 90°小得多(即，表面可以不再是疏水的)。因此，所有暴露的晶片 现场区域，并且尤其是键合衬垫区域，对于后期处理可以是干净的。
在晶片级填充滚珠之后，相对于传统的切割操作，液压劈开技术 可以被用来把芯片切单。这在图7中示出，图7给出了说明基板的液 压劈开的图。特别地，可以沿芯片之间的切单边界在晶片的前侧上构 造作为劈开线的浅而长的蚀刻坑。然后，具有劈开线的滚珠填充晶片 可以在包含嵌入式微流体通道的弹性基板的顶部对准并安装。当微流 体通道内部的液压压力增加时，流体通道与晶片之间薄的可变形膜会 弯曲。这种挠度(deflection)会在劈开线下面施加均匀的劈开力， 使得其劈开并把整个晶片分离成单独的芯片。附连到晶片背侧的紫外 线敏感带或粘合剂可以被用来在劈开期间释放冲击或应力，并且可以 在液压劈开之后保持芯片在其原始位置。在紫外线敏感带上的背侧紫 外线曝光大约10分钟之后，被分离的芯片可以从带子上拿掉。以这 种方式，芯片可以从晶片切单，而不破坏滚珠或阳性特征(即，不把 它们敲出阴性特征外)。
回过头来参考图1，基板110可以具有指示其从晶片被液压劈开 的特征。特别地，基板110可以包括半导体(诸如硅)并且可以具有 侧壁角126。这种侧壁角可以对应于半导体的对称平面(相对于90°， 诸如是54.7°)。此外，沿与劈开线相邻的基板110的表面的粗糙度 可以小于切割后表面的粗糙度。
在液压劈开中使用的、具有微流体通道的弹性体基板可以通过把 底部PDMS块与开放通道和顶部膜键合到一起来构造。例如，具有 开放通道的底部块可以通过在具有光刻胶通道图案的硅基板顶部模制 PDMS块来构造。顶部PDMS膜可以通过在利用肥皂水预先处理过 的另一个晶片上旋涂PDMS来获得，这可以使得更容易随后剥离膜。 在对两个块都进行氧等离子体处理之后，具有开放通道的底部PDMS 块可以安装在PDMS膜的顶部。然后，具有微流体通道的PDMS基 板可以通过从晶片剥离键合的两块来获得。
前面MCM的一种或多种实施例可以包括在系统和/或电子设备 中。这在图8中示出，该图给出了说明包括MCM 810的系统800的 框图。一般而言，MCM可以包括芯片模块(CM)或者单芯片模块 (SCM)的阵列，并且给定的SCM可以包括至少一个基板，诸如半 导体裸片。应当指出，MCM有时候被称为“宏芯片”。此外，基板 可以利用电磁耦合信号的接近性通信与其它基板，MCM中的CM和/ 或SCM，通信(这被称为“电磁接近性通信”)。例如，接近性通 信可以包括：电容耦合信号的通信(“电接近性通信”)和/或光学 信号的通信(诸如“光学接近性通信”)。在一些实施例中，电磁接 近性通信包括电感耦合的信号和/或传导性耦合的信号。
此外，MCM的实施例可以被用在各种应用中，包括：VLSI电 路、通信系统(诸如在波分多路复用中)、存储区域网络、数据中心、 网络(诸如局域网)和/或计算机系统(诸如多核处理器计算机系 统)。例如，MCM可以被包括在耦合到多处理器刀片的底板中，或 者MCM可以耦合不同类型的部件(诸如处理器、存储器、输入/输 出设备和/或外围设备)。在一些实施例中，MCM执行开关、集线器、 桥和/或路由器的功能。
应当指出，系统800可以包括，但不限于：服务器、膝上型计算 机、通信设备或系统、个人计算机、平板电脑、蜂窝电话、工作站、 大型计算机、刀片、企业计算机、数据中心、便携式计算设备、超级 计算机、网络附连的存储(NAS)系统、存储区域网络(SAN)系统， 和/或另一电子计算设备。此外，应当指出，给定的计算机系统可以 在一个位置，或者可以分布在多个地理上分散的位置。
前述实施例中的MCM可以包括更少部件或附加部件。例如，图 1中的阴性特征116可以在沉积在表面112-1上的层中限定，并且这 些阴性特征可以凹入沉积在基板110上的顶层的表面之下。类似地， 图1中的阳性特征124可以突出到局部表面之上，该表面可以是表面 112-1或者是沉积在基板110上的顶层的表面。因此，在前面的实施 例中，基板的表面应当被理解为包括沉积在基板上的层的表面或者基 板本身的表面。
此外，虽然这些实施例被说明为具有多个分离的项，但是这些 MCM和系统是要作为可以存在的各种特征的功能描述，而不是本文 所述实施例的结构示意图。因此，在这些实施例中，两个或更多个部 件可以组合成单个部件，和/或一个或多个部件的位置可以改变。
应当指出，图1中阳性特征124和/或图1中阴性特征116和118 可以利用加性过程(即，材料沉积)和/或消去过程(即，材料去除) 来限定。例如，过程可以包括：溅射、各向同性蚀刻、各向异性蚀刻、 光刻技术和/或直接写入技术。此外，这些特征可以利用各种不同的 材料来构造，包括：半导体、金属、玻璃、蓝宝石和/或二氧化硅。
我们现在描述方法的实施例。图9给出了说明用于构造MCM， 诸如MCM 100(图1)，的方法900的流程图。在这种方法期间， 在第一基板的第一表面上限定第一阴性特征(操作910)，其中给定 的第一阴性特征凹入第一表面之下并且具有由第一边缘限定的第一开口。然后，在第一阴性特征中布置第一层，其中第一层包括亲水材料 (操作912)。接下来，在第一表面上的包围第一阴性特征的区域中 在第一表面上布置第二层，其中第二层包括疏水材料(操作914)。 此外，在第一阴性特征中的第一层上布置阳性特征(操作916)，其 中阳性特征突出到第一表面之上。此外，在第二基板的第二表面上限 定第二阴性特征(操作918)，该第二表面面向第一表面，其中给定 的第二阴性特征凹入第二表面之下并且具有由第二边缘限定的第二开 口。此外，第二阴性特征机械耦合到阳性特征(操作924)，使得第一基板机械耦合到第二基板。
在一些实施例中，在把第二阴性特征机械耦合到阳性特征(操作 924)之前，第二层可以可选地被除去(操作920)。此外，在把第 二阴性特征机械耦合到阳性特征(操作924)之前，第一基板可以可 选地从晶片液压劈开(操作922)。
在过程900的一些实施例中，存在附加的或者更少的操作。此外， 操作的次序可以改变，和/或两个或更多个操作可以组合成单个操作。
以上描述是要使本领域任何技术人员能够制作并使用本公开内容， 并且是在特定应用及其需求的语境下提供的。此外，给出以上对本公 开内容实施例的描述仅仅是为了说明和描述。它们不是详尽的或者要 把本公开内容限定到所公开的形式。从而，许多修改和变化将对本领 域从业人员显而易见，并且，在不背离本公开内容精神和范围的情况 下，本文限定的一般原理可以适用于其它实施例和应用。此外，前面 对实施例的讨论不是要限定本公开内容。因此，本公开内容不是要局 限于所示出的实施例，而是要符合与本文所公开的原理和特征一致的 最广范围。

Claims (18)

1.一种多芯片模块MCM，包括：
具有第一表面的第一基板，其中所述第一基板包括：
布置在所述第一表面上的第一阴性特征，其中给定的第一阴性特征凹入第一表面之下并且具有由第一边缘限定的第一开口；
布置在所述第一阴性特征中的第一层，其中所述第一层包括亲水材料；及
布置在所述第一表面上的包围所述第一阴性特征的区域中的第二层，其中所述第二层包括疏水材料；
布置在所述第一阴性特征中的第一层上的阳性特征，其中所述阳性特征突出到所述第一表面之上，并且其中所述阳性特征具有非疏水表面；及
第二基板，具有面向所述第一表面的第二表面，其中所述第二基板包括布置在所述第二表面上的第二阴性特征，其中给定的第二阴性特征凹入所述第二表面之下并且具有由第二边缘限定的第二开口；及
其中所述第二阴性特征耦合到所述阳性特征，使得所述第一基板机械耦合到所述第二基板。
2.如权利要求1所述的MCM，其中所述阳性特征包括球形滚珠。
3.如权利要求1所述的MCM，其中所述第一阴性特征和第二阴性特征包括坑。
4.如权利要求1所述的MCM，其中所述第二层具有小于1nm的厚度。
5.如权利要求1所述的MCM，其中所述第二层包括硅树脂。
6.如权利要求1所述的MCM，其中所述第一层包括二氧化硅。
7.如权利要求1所述的MCM，其中所述第一基板包括半导体并且具有由第一基板的侧壁和底壁限定的侧壁角；及
其中所述第一基板的侧壁角对应于所述半导体的对称平面。
8.一种包括多芯片模块MCM的系统，包括：
处理器；
存储器，存储被配置为由所述处理器执行的程序模块，其中所述MCM包括：
具有第一表面的第一基板，其中所述第一基板包括：
布置在所述第一表面上的第一阴性特征，其中给定的第一阴性特征凹入所述第一表面之下并且具有由第一边缘限定的第一开口；
布置在所述第一阴性特征中的第一层，其中所述第一层包括亲水材料；及
布置在所述第一表面上的包围所述第一阴性特征的区域中的第二层，其中所述第二层包括疏水材料；
布置在所述第一阴性特征中的第一层上的阳性特征，其中所述阳性特征突出到所述第一表面之上，并且其中所述阳性特征具有非疏水表面；及
第二基板，具有面向所述第一表面的第二表面，其中所述第二基板包括布置在所述第二表面上的第二阴性特征，其中给定的第二阴性特征凹入所述第二表面之下并且具有由第二边缘限定的第二开口；及
其中所述第二阴性特征耦合到所述阳性特征，使得所述第一基板机械耦合到所述第二基板。
9.如权利要求8所述的系统，其中所述阳性特征包括球形滚珠。
10.如权利要求8所述的系统，其中所述第一阴性特征和第二阴性特征包括坑。
11.如权利要求8所述的系统，其中所述第二层具有小于1nm的厚度。
12.如权利要求8所述的系统，其中所述第二层包括硅树脂。
13.如权利要求8所述的系统，其中所述第一层包括二氧化硅。
14.如权利要求8所述的系统，其中所述第一基板包括半导体并且具有由第一基板的侧壁和底壁限定的侧壁角；及
其中所述第一基板的侧壁角对应于所述半导体的对称平面。
15.一种用于构造多芯片模块MCM的方法，包括：
在第一基板的第一表面上限定第一阴性特征，其中给定的第一阴性特征凹入所述第一表面之下并且具有由第一边缘限定的第一开口；
在所述第一阴性特征中布置第一层，其中所述第一层包括亲水材料；
在所述第一表面上的包围所述第一阴性特征的区域中布置第二层，其中所述第二层包括疏水材料；
在所述第一阴性特征中的第一层上布置阳性特征，其中所述阳性特征突出到所述第一表面之上，并且其中所述阳性特征具有非疏水表面；
在第二基板的第二表面上限定第二阴性特征，所述第二表面面向所述第一表面，其中给定的第二阴性特征凹入所述第二表面之下并且具有由第二边缘限定的第二开口；及
把所述第二阴性特征机械耦合到所述阳性特征，使得所述第一基板机械耦合到所述第二基板。
16.如权利要求15所述的方法，其中，在把所述第二阴性特征机械耦合到所述阳性特征之前，所述方法还包括把所述第一基板从晶片液压劈开。
17.如权利要求15所述的方法，其中，在把所述第二阴性特征机械耦合到所述阳性特征之前，所述方法还包括除去所述第二层。
18.如权利要求15所述的方法，其中所述阳性特征包括球形滚珠，并且所述第一阴性特征和第二阴性特征包括坑。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496238B2 (en) * 2015-02-13 2016-11-15 Advanced Semiconductor Engineering, Inc. Sloped bonding structure for semiconductor package
US9470855B1 (en) * 2015-08-11 2016-10-18 Oracle International Corporation Self-assembled vertically aligned multi-chip module
US9773741B1 (en) * 2016-08-17 2017-09-26 Qualcomm Incorporated Bondable device including a hydrophilic layer
US20200234928A1 (en) * 2019-01-17 2020-07-23 Applied Materials, Inc. Semiconductor plasma processing equipment with wafer edge plasma sheath tuning ability

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1964037A (zh) * 2005-11-10 2007-05-16 沈育浓 堆叠式半导体芯片封装体

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57126139A (en) * 1981-01-27 1982-08-05 Nec Home Electronics Ltd Manufacture of semiconductor device
US5006201A (en) * 1989-11-22 1991-04-09 Eastman Kodak Company Method of making a fiber optic array
US5681634A (en) * 1995-02-15 1997-10-28 Matsushita Electric Industrial Co., Ltd. Optical information medium, and method and apparatus for fabricating the same
US6114221A (en) * 1998-03-16 2000-09-05 International Business Machines Corporation Method and apparatus for interconnecting multiple circuit chips
US6965166B2 (en) 1999-02-24 2005-11-15 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure
US6645432B1 (en) * 2000-05-25 2003-11-11 President & Fellows Of Harvard College Microfluidic systems including three-dimensionally arrayed channel networks
US7086134B2 (en) * 2000-08-07 2006-08-08 Shipley Company, L.L.C. Alignment apparatus and method for aligning stacked devices
US20020196440A1 (en) * 2000-12-14 2002-12-26 Steinberg Dan A. Structure for aligning chips in stacked arrangement
KR100662491B1 (ko) * 2000-12-27 2007-01-02 엘지.필립스 엘시디 주식회사 면발광 램프 및 그 제조방법
US6974604B2 (en) 2001-09-28 2005-12-13 Hrl Laboratories, Llc Method of self-latching for adhesion during self-assembly of electronic or optical components
US7870788B2 (en) * 2002-01-25 2011-01-18 Kinemetrics, Inc. Fabrication process and package design for use in a micro-machined seismometer or other device
KR100383383B1 (en) * 2002-06-22 2003-05-16 Fionix Inc Method for fabricating optical fiber block
US6874950B2 (en) * 2002-12-17 2005-04-05 International Business Machines Corporation Devices and methods for side-coupling optical fibers to optoelectronic components
US8426720B2 (en) * 2004-01-09 2013-04-23 Industrial Technology Research Institute Micro thermoelectric device and manufacturing method thereof
FR2878843B1 (fr) * 2004-12-02 2007-07-20 Saint Gobain Substrat protege contre les pollutions organiques
US7592707B2 (en) 2005-10-03 2009-09-22 Sun Microsystems, Inc. Method and apparatus for facilitating proximity communication and power delivery
JP4640643B2 (ja) * 2005-11-08 2011-03-02 日本電気硝子株式会社 光ファイバアレイ用基板及びその製造方法
US7550846B2 (en) 2005-12-21 2009-06-23 Palo Alto Research Center Conductive bump with a plurality of contact elements
KR100723532B1 (ko) * 2006-06-19 2007-05-30 삼성전자주식회사 도전성 범프 형성용 몰드, 그 몰드 제조방법, 및 그몰드를 이용한 웨이퍼에 범프 형성방법
US8456393B2 (en) * 2007-05-31 2013-06-04 Nthdegree Technologies Worldwide Inc Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system
US8076178B2 (en) 2007-09-28 2011-12-13 Oracle America, Inc. Self-assembly of micro-structures
US7893531B2 (en) * 2007-09-28 2011-02-22 Oracle America, Inc. Integrated-circuit package for proximity communication
US7651021B2 (en) 2007-12-28 2010-01-26 Intel Corporation Microball attachment using self-assembly for substrate bumping
JP2009175504A (ja) * 2008-01-25 2009-08-06 Fujifilm Corp 光ファイバ構造体
JP2011044496A (ja) 2009-08-19 2011-03-03 Panasonic Corp 半導体デバイス及びそれを用いた半導体装置
US8934098B2 (en) * 2009-08-31 2015-01-13 Life Technologies Corporation Fast-indexing filter wheel and method of use
US8487429B2 (en) * 2009-09-22 2013-07-16 Oracle America, Inc. Assembly of multi-chip modules using sacrificial features
US8188581B2 (en) 2009-09-28 2012-05-29 Oracle America, Inc. Mechanical coupling in a multi-chip module using magnetic components
US8218334B2 (en) * 2010-03-09 2012-07-10 Oracle America, Inc. Multi-chip module with multi-level interposer
US8648463B2 (en) * 2010-05-17 2014-02-11 Oracle International Corporation Assembly of multi-chip modules with proximity connectors using reflowable features
US8564137B2 (en) * 2010-11-05 2013-10-22 Stmicroelectronics, Inc. System for relieving stress and improving heat management in a 3D chip stack having an array of inter-stack connections
US8659161B2 (en) * 2011-06-21 2014-02-25 Oracle International Corporation Chip package with reinforced positive alignment features

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1964037A (zh) * 2005-11-10 2007-05-16 沈育浓 堆叠式半导体芯片封装体

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