JP6182548B2 - 圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 - Google Patents
圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 Download PDFInfo
- Publication number
- JP6182548B2 JP6182548B2 JP2014557785A JP2014557785A JP6182548B2 JP 6182548 B2 JP6182548 B2 JP 6182548B2 JP 2014557785 A JP2014557785 A JP 2014557785A JP 2014557785 A JP2014557785 A JP 2014557785A JP 6182548 B2 JP6182548 B2 JP 6182548B2
- Authority
- JP
- Japan
- Prior art keywords
- mcm
- bridge
- tip
- compressible structure
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H01L2225/06531—Non-galvanic coupling, e.g. capacitive coupling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Wire Bonding (AREA)
- Connector Housings Or Holding Contact Members (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
分野
本開示は、概して、半導体チップを収容するマルチチップモジュール(MCM:multi-chip module)に関する。より具体的には、本開示は、MCMにおける構成要素間のアライメントを維持する圧縮可能な構造を含むMCMに関する。
集積回路(IC:integrated-circuit)技術はより小さなクリティカルディメンションを目指して小型化され続けているため、既存の相互接続技術で高帯域幅、低電力、信頼性および低コストなどの好適な通信特徴を提供することが次第に困難になりつつある。技術者および研究者らは、これらの問題に対処し、高密度で高性能な将来的システムを可能にするために、マルチチップモジュール(MCM)におけるチップの積層について研究している。
本開示の一実施形態はマルチチップモジュール(MCM)を提供する。マルチチップモジュール(MCM)は、基板、アイランドチップ、ブリッジチップおよび圧縮可能な構造を含む。基板は、第1の表面と、第1の表面において端縁によって規定される空隙とを有する。空隙の底部は、第1の表面から垂直方向にオフセットされている。さらに、アイランドチップは、第1の表面に機械的に結合された第2の表面を有し、ブリッジチップは、第2の表面に対向する第3の表面を有する。ブリッジチップは、空隙内に位置決めされ、アイランドチップに機械的に結合される。さらに、圧縮可能な構造は、空隙の底部と、ブリッジチップのうち第3の表面とは反対側にある第4の表面との間に位置決めされる。この圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含んでおり、ブリッジチップを曲げることなく第2の表面および第3の表面がほぼ同一平面上に位置するようにブリッジチップに対して力を加える。
別の実施形態は、MCMにおけるアイランドチップおよびブリッジチップのアライメントを維持するための方法を提供する。この方法の実行中、圧縮可能な構造は、MCMにおける基板の第1の表面において、端縁によって規定される空隙内に位置決めされる。ここで、圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含み、空隙の底部は第1の表面から垂直方向にオフセットされている。次いで、第3の表面と、当該第3の表面とは反対側にある第4の表面とを有するブリッジチップは、圧縮可能な構造の上において空隙内に位置決めされ、ここで、第4の表面が圧縮可能な構造に機械的に結合される。さらに、第2の表面を有するアイランドチップは、第1の表面および第3の表面に機械的に結合される。ここで、圧縮可能な構造は、ブリッジチップを曲げることなく、第2の表面および第3の表面がほぼ同一平面上に位置するように、ブリッジチップに対して力を加える。
マルチチップモジュール(MCM)、電子装置またはMCMを含むシステムの実施形態、ならびに、MCMにおけるアイランドチップおよびブリッジチップのアライメントを維持するための技術を説明する。このMCMは、部分的に重なるコネクタを用いて互いに通信するアイランドチップおよびブリッジチップを含む、対向するチップの2次元配列を備える。これらのコネクタの相対的な垂直間隔を維持するために、圧縮可能な構造は、基板に設けられてブリッジチップを収容する空隙内に位置して、ブリッジチップの裏面に対して圧縮力を加える。これらの圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含む。このようにして、MCMは、ブリッジチップを曲げることなく、アイランドチップおよびブリッジチップの対向面ならびにこれらの表面上のコネクタがほぼ同一平面上に位置することを確実にし得る。
Claims (13)
- マルチチップモジュール(MCM)であって、
第1の表面と、前記第1の表面において端縁によって規定される空隙とを有する基板を含み、前記空隙の底部は、前記第1の表面から垂直方向にオフセットされており、
第2の表面を有するアイランドチップを含み、前記アイランドチップは前記第1の表面に機械的に結合され、
前記第2の表面に対向する第3の表面を有するブリッジチップを含み、前記ブリッジチップは前記アイランドチップに機械的に結合され、前記ブリッジチップは前記空隙内に位置決めされており、
前記空隙の底部と、前記ブリッジチップのうち前記第3の表面とは反対側にある第4の表面との間に位置決めされる圧縮可能な構造を含み、
前記圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含み、
前記圧縮可能な構造は、横方向に摺動できるように前記基板から離間されており、
前記圧縮可能な構造は、前記ブリッジチップを曲げることなく、前記第2の表面および前記第3の表面がほぼ同一平面上に位置するように前記ブリッジチップに対して力を加える、MCM。 - 前記ブリッジチップは、近接通信コネクタによって前記アイランドチップに電気的に結合される、請求項1に記載のMCM。
- 前記近接通信コネクタは、容量性近接通信コネクタ、誘導性近接通信コネクタ、導電性近接通信コネクタ、および光学近接通信コネクタのうちの1つを含む、請求項2に記載のMCM。
- 前記近接通信コネクタは、マイクロスプリングコネクタを含む、請求項2に記載のMCM。
- 前記アイランドチップは、はんだによって前記第1の表面に電気的に結合される、請求項1〜4のいずれか1項に記載のMCM。
- 前記ブリッジチップは、前記第2の表面および前記第3の表面上におけるペアのネガ型特徴と、対応するペアのネガ型特徴と接合するポジ型特徴とによって前記アイランドチップに機械的に結合される、請求項1〜5のいずれか1項に記載のMCM。
- 前記ネガ型特徴は窪みを含み、前記ポジ型特徴は球形のボールを含む、請求項6に記載のMCM。
- 前記ペアのネガ型特徴は、前記ブリッジチップおよび前記アイランドチップの角部に近接している、請求項6に記載のMCM。
- 前記圧縮可能な構造は、円筒形の特徴、楕円形の隆起、および小胞状の特徴のうちの1つを含む、請求項1〜8のいずれか1項に記載のMCM。
- 前記圧縮可能な構造は、スプリング以外のものである、請求項1〜9のいずれか1項に記載のMCM。
- 前記柔軟な材料は、エラストマを含む、請求項1〜10のいずれか1項に記載のMCM。
- システムであって、
プロセッサと、
前記プロセッサによって実行されるように構成されるプログラムモジュールを格納するメモリと、
MCMとを含み、前記MCMは、
第1の表面と、前記第1の表面において端縁によって規定される空隙とを有する基板を含み、前記空隙の底部は、前記第1の表面から垂直方向にオフセットされており、
第2の表面を有するアイランドチップを含み、前記アイランドチップは前記第1の表面に機械的に結合され、
前記第2の表面に対向する第3の表面を有するブリッジチップを含み、前記ブリッジチップは前記アイランドチップに機械的に結合され、前記ブリッジチップは前記空隙内に位置決めされており、
前記空隙の底部と、前記ブリッジチップのうち前記第3の表面とは反対側にある第4の表面との間に位置決めされた圧縮可能な構造を含み、
前記圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含み、
前記圧縮可能な構造は、横方向に摺動できるように前記基板から離間されており、
前記圧縮可能な構造は、前記ブリッジチップを曲げることなく、前記第2の表面および前記第3の表面がほぼ同一平面上に位置するように前記ブリッジチップに対して力を加える、システム。 - MCMにおけるアイランドチップおよびブリッジチップのアライメントを維持するための方法であって、
前記MCMにおける基板の第1の表面において端縁によって規定される空隙に圧縮可能な構造を位置決めするステップを含み、前記圧縮可能な構造は、形状および体積が圧縮された柔軟な材料を含み、前記空隙の底部は、前記第1の表面から垂直方向にオフセットされており、
前記圧縮可能な構造の上の前記空隙において前記ブリッジチップを位置決めするステップを含み、前記ブリッジチップは、第3の表面と、前記第3の表面とは反対側にある第4の表面とを有し、前記第4の表面は、圧縮可能な構造に機械的に結合され、前記圧縮可能な構造は、横方向に摺動できるように前記基板から離間されており、
第2の表面を有するアイランドチップを前記第1の表面および前記第3の表面に機械的に結合するステップを含み、前記圧縮可能な構造は、前記ブリッジチップを曲げることなく、前記第2の表面および前記第3の表面がほぼ同一平面上に位置するようにブリッジチップに対して力を加える、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/397,593 | 2012-02-15 | ||
US13/397,593 US8742576B2 (en) | 2012-02-15 | 2012-02-15 | Maintaining alignment in a multi-chip module using a compressible structure |
PCT/US2013/026223 WO2013123259A2 (en) | 2012-02-15 | 2013-02-14 | Maintaining alignment in a multi-chip module using a compressible structure |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2015524155A JP2015524155A (ja) | 2015-08-20 |
JP2015524155A5 JP2015524155A5 (ja) | 2016-02-12 |
JP6182548B2 true JP6182548B2 (ja) | 2017-08-16 |
Family
ID=47790523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014557785A Active JP6182548B2 (ja) | 2012-02-15 | 2013-02-14 | 圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8742576B2 (ja) |
EP (1) | EP2815429B1 (ja) |
JP (1) | JP6182548B2 (ja) |
CN (1) | CN104471709B (ja) |
TW (1) | TWI550821B (ja) |
WO (1) | WO2013123259A2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9925614B2 (en) | 2004-06-01 | 2018-03-27 | Illinois Tool Works Inc. | Power source with rechargeable energy storage device |
US10092971B2 (en) | 2009-11-17 | 2018-10-09 | Iliinois Tool Works Inc. | Incremental hybrid welding systems and methods |
US10421143B2 (en) | 2009-11-17 | 2019-09-24 | Illinois Tool Works Inc. | Energy storage caddy for a welding system |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9754890B2 (en) * | 2014-02-26 | 2017-09-05 | Intel Corporation | Embedded multi-device bridge with through-bridge conductive via signal connection |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9379090B1 (en) * | 2015-02-13 | 2016-06-28 | Qualcomm Incorporated | System, apparatus, and method for split die interconnection |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9443824B1 (en) | 2015-03-30 | 2016-09-13 | Qualcomm Incorporated | Cavity bridge connection for die split architecture |
US9653428B1 (en) * | 2015-04-14 | 2017-05-16 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
TWI652778B (zh) | 2016-01-27 | 2019-03-01 | 艾馬克科技公司 | 半導體封裝以及其製造方法 |
US10497674B2 (en) | 2016-01-27 | 2019-12-03 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US10312220B2 (en) | 2016-01-27 | 2019-06-04 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9698564B1 (en) * | 2016-02-09 | 2017-07-04 | Oracle International Corporation | Hybrid integrated MCM with waveguide-fiber connector |
US9978686B1 (en) * | 2016-02-19 | 2018-05-22 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Interconnection of semiconductor devices in extreme environment microelectronic integrated circuit chips |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
KR102632563B1 (ko) | 2016-08-05 | 2024-02-02 | 삼성전자주식회사 | 반도체 패키지 |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
KR20180086804A (ko) | 2017-01-23 | 2018-08-01 | 앰코 테크놀로지 인코포레이티드 | 반도체 디바이스 및 그 제조 방법 |
US10475766B2 (en) * | 2017-03-29 | 2019-11-12 | Intel Corporation | Microelectronics package providing increased memory component density |
US20190006331A1 (en) * | 2017-06-30 | 2019-01-03 | Intel Corporation | Electronics package devices with through-substrate-vias having pitches independent of substrate thickness |
US11289424B2 (en) * | 2018-11-29 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package and method of manufacturing the same |
KR102538704B1 (ko) * | 2018-12-04 | 2023-06-01 | 에스케이하이닉스 주식회사 | 플렉시블 브리지 다이를 포함한 스택 패키지 |
US11676941B2 (en) | 2018-12-07 | 2023-06-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and fabricating method thereof |
US20200402913A1 (en) * | 2019-06-19 | 2020-12-24 | Invensas Corporation | Connecting multiple chips using an interconnect device |
US11569172B2 (en) | 2019-08-08 | 2023-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of manufacture |
KR102674087B1 (ko) * | 2019-09-06 | 2024-06-12 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐층을 포함하는 반도체 패키지 |
US11804469B2 (en) | 2020-05-07 | 2023-10-31 | Invensas Llc | Active bridging apparatus |
US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4242565C1 (de) * | 1992-12-16 | 1994-03-17 | Deutsche Aerospace | Verfahren zur Justage von Halbleiterscheiben zueinander |
JP4167443B2 (ja) * | 2002-01-30 | 2008-10-15 | 日本放送協会 | 固体撮像素子 |
US7525199B1 (en) | 2004-05-21 | 2009-04-28 | Sun Microsystems, Inc | Packaging for proximity communication positioned integrated circuits |
US7893531B2 (en) * | 2007-09-28 | 2011-02-22 | Oracle America, Inc. | Integrated-circuit package for proximity communication |
US8064224B2 (en) * | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US8531042B2 (en) * | 2009-06-30 | 2013-09-10 | Oracle America, Inc. | Technique for fabricating microsprings on non-planar surfaces |
US8487429B2 (en) | 2009-09-22 | 2013-07-16 | Oracle America, Inc. | Assembly of multi-chip modules using sacrificial features |
US8315065B2 (en) * | 2009-09-28 | 2012-11-20 | Oracle America, Inc. | Self-locking features in a multi-chip module |
US8188581B2 (en) * | 2009-09-28 | 2012-05-29 | Oracle America, Inc. | Mechanical coupling in a multi-chip module using magnetic components |
US8212354B2 (en) | 2009-12-17 | 2012-07-03 | Oracle America, Inc. | Active plastic bridge chips |
US8218334B2 (en) * | 2010-03-09 | 2012-07-10 | Oracle America, Inc. | Multi-chip module with multi-level interposer |
US8698322B2 (en) * | 2010-03-24 | 2014-04-15 | Oracle International Corporation | Adhesive-bonded substrates in a multi-chip module |
US8274149B2 (en) * | 2010-03-29 | 2012-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having a buffer structure and method of fabricating the same |
US8648463B2 (en) * | 2010-05-17 | 2014-02-11 | Oracle International Corporation | Assembly of multi-chip modules with proximity connectors using reflowable features |
-
2012
- 2012-02-15 US US13/397,593 patent/US8742576B2/en active Active
-
2013
- 2013-02-08 TW TW102105343A patent/TWI550821B/zh active
- 2013-02-14 CN CN201380009348.0A patent/CN104471709B/zh active Active
- 2013-02-14 EP EP13749252.6A patent/EP2815429B1/en active Active
- 2013-02-14 JP JP2014557785A patent/JP6182548B2/ja active Active
- 2013-02-14 WO PCT/US2013/026223 patent/WO2013123259A2/en active Application Filing
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9925614B2 (en) | 2004-06-01 | 2018-03-27 | Illinois Tool Works Inc. | Power source with rechargeable energy storage device |
US10092971B2 (en) | 2009-11-17 | 2018-10-09 | Iliinois Tool Works Inc. | Incremental hybrid welding systems and methods |
US10421143B2 (en) | 2009-11-17 | 2019-09-24 | Illinois Tool Works Inc. | Energy storage caddy for a welding system |
US11318552B2 (en) | 2009-11-17 | 2022-05-03 | Illinois Tool Works Inc. | Energy storage caddy for a welding system |
US11420283B2 (en) | 2009-11-17 | 2022-08-23 | Illinois Tool Works Inc. | Incremental hybrid welding systems and methods |
Also Published As
Publication number | Publication date |
---|---|
WO2013123259A3 (en) | 2014-11-13 |
WO2013123259A9 (en) | 2015-08-13 |
EP2815429A2 (en) | 2014-12-24 |
TWI550821B (zh) | 2016-09-21 |
TW201401480A (zh) | 2014-01-01 |
US20130207261A1 (en) | 2013-08-15 |
WO2013123259A2 (en) | 2013-08-22 |
EP2815429B1 (en) | 2021-07-07 |
CN104471709B (zh) | 2018-11-16 |
JP2015524155A (ja) | 2015-08-20 |
CN104471709A (zh) | 2015-03-25 |
US8742576B2 (en) | 2014-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6182548B2 (ja) | 圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 | |
US9281268B2 (en) | Method for fabricating multi-chip module with multi-level interposer | |
US6870271B2 (en) | Integrated circuit assembly module that supports capacitive communication between semiconductor dies | |
JP6000952B2 (ja) | 静的屈曲部を有する傾斜スタックチップパッケージ | |
TWI729073B (zh) | 電氣互連橋接技術 | |
Cunningham et al. | Integration and packaging of a macrochip with silicon nanophotonic links | |
US20150262968A1 (en) | Methods for high precision microelectronic die integration | |
TW201230289A (en) | Optical communication in a ramp-stack chip package | |
TW201532235A (zh) | 使用重建晶圓與可測試之區域陣列之微小間距的焊孔陣列〈bva〉 | |
US8164917B2 (en) | Base plate for use in a multi-chip module | |
US8975754B2 (en) | Chip package for high-count chip stacks | |
US9111943B2 (en) | Alignment structures for integrated-circuit packaging | |
US8698322B2 (en) | Adhesive-bonded substrates in a multi-chip module | |
CN105144359B (zh) | 具有自填充阳性特征的多芯片模块 | |
CN107646142A (zh) | 通过固相粘合剂和选择性转移的超薄功能性块的异构集成 | |
US8487429B2 (en) | Assembly of multi-chip modules using sacrificial features | |
TW201717327A (zh) | 具有機械式去耦合的扇入和扇出區域的晶圓級封裝 | |
EP4020038A1 (en) | Micro socket electrical couplings for dies | |
CN114660738A (zh) | 用于光子管芯中的无源对准的硅凹槽架构和制造工艺 | |
CN202886840U (zh) | 一种制作掩模版的装置 | |
US8315065B2 (en) | Self-locking features in a multi-chip module | |
CN212542410U (zh) | 扇出型晶圆级封装结构 | |
CN114300427A (zh) | 一种基于多芯片扇出型晶圆级封装的红外成像微系统 | |
CN114156188A (zh) | 扇出型晶圆级封装结构及封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151217 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20151217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161011 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161018 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161206 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170627 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170724 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6182548 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |