JP2016509810A5 - - Google Patents

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Publication number
JP2016509810A5
JP2016509810A5 JP2015556166A JP2015556166A JP2016509810A5 JP 2016509810 A5 JP2016509810 A5 JP 2016509810A5 JP 2015556166 A JP2015556166 A JP 2015556166A JP 2015556166 A JP2015556166 A JP 2015556166A JP 2016509810 A5 JP2016509810 A5 JP 2016509810A5
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JP
Japan
Prior art keywords
latches
multiplexer
data
output
latch
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JP2015556166A
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English (en)
Japanese (ja)
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JP6397829B2 (ja
JP2016509810A (ja
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Priority claimed from US13/755,056 external-priority patent/US9509317B2/en
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Publication of JP2016509810A5 publication Critical patent/JP2016509810A5/ja
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Publication of JP6397829B2 publication Critical patent/JP6397829B2/ja
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JP2015556166A 2013-01-31 2014-01-31 メタスタビリティ解決のための回転シンクロナイザ回路 Active JP6397829B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/755,056 US9509317B2 (en) 2013-01-31 2013-01-31 Rotational synchronizer circuit for metastablity resolution
US13/755,056 2013-01-31
PCT/US2014/014114 WO2014121057A1 (en) 2013-01-31 2014-01-31 Rotational synchronizer circuit for metastablity resolution

Publications (3)

Publication Number Publication Date
JP2016509810A JP2016509810A (ja) 2016-03-31
JP2016509810A5 true JP2016509810A5 (enExample) 2017-02-16
JP6397829B2 JP6397829B2 (ja) 2018-09-26

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ID=50102275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015556166A Active JP6397829B2 (ja) 2013-01-31 2014-01-31 メタスタビリティ解決のための回転シンクロナイザ回路

Country Status (5)

Country Link
US (1) US9509317B2 (enExample)
EP (1) EP2951943B1 (enExample)
JP (1) JP6397829B2 (enExample)
CN (1) CN105191205B (enExample)
WO (1) WO2014121057A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10110232B2 (en) * 2015-06-30 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiplexer and latch system
CN105607689B (zh) * 2015-12-22 2017-12-22 邓晨曦 高速多相时钟同步方法
KR102501754B1 (ko) * 2016-03-28 2023-02-20 삼성전자주식회사 불균형 멀티플렉서 및 이를 적용하는 스캔 플립플롭
US9825636B1 (en) * 2016-10-20 2017-11-21 Arm Limited Apparatus and method for reduced latency signal synchronization
US9793894B1 (en) * 2016-11-18 2017-10-17 Via Alliance Semiconductor Co., Ltd. Data synchronizer for registering a data signal into a clock domain
CN107729614A (zh) * 2017-09-18 2018-02-23 北京空间飞行器总体设计部 一种可扩展的通用功能级异步电路
US11360704B2 (en) * 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
CN112800000B (zh) * 2019-11-14 2023-07-18 海思光电子有限公司 一种电路以及电子设备
US12154634B2 (en) * 2022-02-18 2024-11-26 Infineon Technologies LLC Data path circuit and method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045801A (en) 1990-05-29 1991-09-03 The United States Of America As Represented By The Secretary Of The Air Force Metastable tolerant asynchronous interface
JPH07131302A (ja) * 1993-11-08 1995-05-19 Nec Corp レジスタ回路
US5598113A (en) 1995-01-19 1997-01-28 Intel Corporation Fully asynchronous interface with programmable metastability settling time synchronizer
US6137851A (en) 1998-02-13 2000-10-24 Agilent Technologies System and method for synchronizing a signal with respect to another signal
JP3696077B2 (ja) * 2000-11-13 2005-09-14 シャープ株式会社 電圧変換回路及びこれを備えた半導体集積回路装置
JP2002325041A (ja) * 2001-04-25 2002-11-08 Nec Corp デコード回路及び符号変換回路と方法
US6819156B1 (en) * 2001-11-26 2004-11-16 Xilinx, Inc. High-speed differential flip-flop
JP4339145B2 (ja) * 2004-02-18 2009-10-07 旭化成エレクトロニクス株式会社 同期化回路
US7656745B2 (en) * 2007-03-15 2010-02-02 Micron Technology, Inc. Circuit, system and method for controlling read latency
DE102007059554A1 (de) 2007-12-11 2009-06-25 Robert Bosch Gmbh Verfahren zur Ermittlung der Taktrate eines von einem Teilnehmer eines Kommunikationssystems empfangenen Datensignals, aktiver Sternkoppler zur Ausführung des Verfahrens und Kommunikationssystem mit einem solchen aktiven Sternkoppler

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