JP2016506620A - Motfetを有するピクセル化されたイメージャおよびその製造方法 - Google Patents
Motfetを有するピクセル化されたイメージャおよびその製造方法 Download PDFInfo
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Abstract
Description
Claims (32)
- ピクセル化されたイメージャを製作する方法であって、
底面電極層と、当該底面電極層上に堆積もしくは成長した検出素子ブランケット層とを有する基板を提供し、
前記検出素子ブランケット層を、隣接する検出素子を分離する分離溝によって検出素子のアレイに分離し、
アレイ中の各検出素子に隣接して、前記分離溝の上側に、Thin Film Transistor(TFT)を定めるゲート電極を形成し、
各TFTのゲート電極の上側に設けられたゲート誘電体層、および各TFTに隣接する検出素子を定める検出素子ブランケット層の露出した上面に金属酸化物半導体材料の層を形成し、
ゲート電極を囲む領域であって、ソース/ドレイン金属の層を前記ゲート電極の両側のS/D電極に分離する領域にわたって、各TFTの前記金属酸化物半導体材料の層に前記ソース/ドレイン金属の層を堆積する各工程を備え、
前記S/D電極の1つを構成する前記金属は、隣接する検出素子の検出素子ブランケット層の露出した上面の上側にある金属酸化物半導体材料と電気的に接触し、それによってアレイの各検知素子は前記金属酸化物半導体材料を介して隣接するTFTに電気的に接続している、方法。 - 前記ピクセル化されたイメージャは、上からの照明、下からの照明、または上および下からの照明のいずれか1つを検出するように作製される、請求項1に記載の方法。
- 前記基板および底面電極層は、検出素子の検出波長の光に対して透明(transparent)である、請求項2に記載の方法。
- 前記ゲート電極を形成する工程は、前記ゲート電極を堆積させる前に前記溝を平坦化する工程を含む、請求項1に記載の方法。
- 前記金属酸化物半導体材料の層を形成する工程は、検出素子の検出波長の光を透過させる金属酸化物半導体材料の層を形成する工程を含む、請求項1に記載の方法。
- 前記検出素子の検出波長の光を透過させる金属酸化物半導体材料の層を形成する工程における透明な金属酸化物半導体材料は、非晶質または多結晶質のいずれかである、請求項3に記載の方法。
- アレイの各検出素子に隣接するゲート電極を形成する工程は、前記分離溝の上側にデータラインおよびゲートスキャンラインを形成する工程を含む、請求項1に記載の方法。
- 前記ソース/ドレイン金属層を堆積させる工程は、ゲート電極の上側の金属酸化物半導体材料の活性領域を画定するためのエッチストップ材料の層を形成する工程を含む、請求項1に記載の方法。
- 前記エッチストップ材料の層を成形する工程は、各TFTに隣接して検出素子を定めている検出素子ブランケット層の上面に設けられた前記金属酸化物半導体材料の上面に前記エッチストップ材料の層の部分を形成する工程を含む、請求項8に記載の方法。
- 前記検出素子ブランケット層を形成する工程は、前記底面電極層に堆積されもしくは成長したp−nフォトダイオードブランケット層を形成する工程を含み、そして、前記検出素子ブランケット層を検出素子の列に分離する工程は、前記p−nフォトダイオードブランケット層を、隣接するフォトダイオードを分離する分離溝によってフォトダイオードアレイに分離する工程を含む、請求項1に記載の方法。
- 前記基板にpn接合ブランケット層を提供する工程は、p型およびn型のいずれかの導電性の1つを有する半導体材料の下層を形成し、およびpn接合を形成する他の型の導電性を有する半導体材料の上部層を形成する工程を含む、請求項10に記載の方法。
- 前記半導体材料の下部層およびその上側に上部層を形成する工程は、PINダイオードを形成するために前記下部層と前記上部層との間に真性半導体材料の層を堆積させる工程を含む、請求項11に記載の方法。
- 前記基板にpn接合ブランケット層を提供する工程は、p−i1−n−i2−p層またはn−i1−p−i2−n層いずれかのブランケット層を形成する工程を含む、請求項11に記載の方法。
- 上からの照明を底面で受けるタイプのイメージャを製作する方法であって、
基板を用意し、底面電極層を当該基板の上に形成する工程と、
前記底面電極層の上側にpn接合ブランケット層を形成するために、少なくとも下部の半導体層および上部の半導体層を前記底面電極層上に堆積させもしくは成長させる工程と、
隣接するフォトダイオードアレイを分離する分離溝によって前記pn接合ブランケット層の上部半導体層をフォトダイオードアレイに分離するため第1のマスキングを行う工程と、
前記フォトダイオードアレイを誘電材料で平坦化する工程と、
フォトダイオードアレイの各フォトダイオードに隣接するTFTを定めるゲート電極を前記分離溝の上側に形成するために2回目のマスキングを行う工程と、
フォトダイオードアレイ上にゲート誘電体層を堆積させもしくは成長させるとともに、フォトダイオードアレイの各フォトダイオードの前記上部の半導体層の上面を露出させるために、前記ゲート誘電体層の部分を取り除く3回目のマスキングを行う工程と、
各TFTのゲート電極の上側のゲート誘電体層、およびフォトダイオードアレイの各フォトダイオードの上部半導体層の露出した上面に金属酸化物半導体材料の層を堆積させもしくは成長させるため4回目のマスキングを行う工程と、
各TFTのゲート電極および各フォトダイオードの上部半導体層の露出した上面の金属酸化物半導体材料の層の上側にエッチストップ材料の層を堆積させるため5回目のマスキングを行う工程と、
ゲート電極を囲む領域であって、各TFTのソース/ドレイン金属の層をゲート電極の両側に分離する領域に各TFTにソース/ドレイン金属の層を堆積させる6回目のマスキングを行う工程とを有し、
前記ソース/ドレイン電極の1つを形成する金属は隣接するフォトダイオードの上部半導体層の露出した上面に設けられている前記金属酸化物半導体材料と電気的に接触している、方法。 - 少なくとも下部半導体層とその上の上部半導体層とを底面電極上に堆積させもしくは成長させる工程は、PINダイオードを形成するために下層と上層の間に真性半導体の材料の層を堆積させる工程を含む、請求項14に記載の方法。
- 前記pn接合ブランケット層の上部半導体層を、分離溝を用いてフォトダイオードアレイへ分離する工程は、前記真性半導体の材料の層の一部を貫いて前記分離溝を形成する工程を含む、請求項15に記載の方法。
- 各フォトダイオードに隣接してTFTを定めるゲート電極を形成する工程は、前記分離溝の上側にデータラインおよびゲートスキャンラインを形成する工程を含む、請求項14に記載の方法。
- 前記金属酸化物半導体材料の層を堆積させもしくは成長させる工程は、検出素子の検出波長に対して透明な金属酸化物半導体材料の層を形成する工程を含む、請求項14に記載の方法。
- 前記透明な金属酸化物半導体材料の層を堆積させる工程は、非晶質もしくは多結晶質のいずれかである透明な金属酸化物半導体材料を堆積させる工程を含む、請求項18に記載の方法。
- フォトダイオードアレイを前記誘電材料で平坦化する工程は、ポリマーPMGI、ポリスチレン、PMMA、もしくは他のタイプのアクリルポリマー、ポリエチレン、ポリイミド、ポリビニル・フェノール(PVP)、zeon、PET、PEN、PES、PAN、BCB、SU8、シランもしくはシロキシレーンベースの化合物、有機金属ベースの化合物、スピンオングラス、またはグラフィーム酸化物(grapheme oxides)から選ばれる1つを用いた塗布工程を含む、請求項14に記載の方法。
- ピクセル化されたイメージャを含む構造であって、
底面電極層と、前記底面電極層に堆積され、アレイの隣接する検出素子を分離する分離溝によって検出素子のアレイに分離される検出素子ブランケットの層を備える基板と、
アレイの各検出素子に隣接し、分離溝の上側にあってTFTを定めるゲート電極と、
各TFTのゲート電極の上側の誘電層、および各TFTに隣接する検出素子を定める検出素子ブランケット層の露出した上面に配置される金属酸化物半導体材料の層と、
各TFTの前記ゲート電極を囲む領域であって、ソース/ドレイン電極をゲート電極の両側に分離した領域に配置されたソース/ドレイン金属の層とを有し、
前記ソース/ドレイン電極のいずれか1つを形成する金属は、隣接する検出素子の上部層の露出した上面にある金属酸化物半導体材料と電気的に接触しており、それによってアレイの各検出素子が前記金属酸化物半導体材料を通して、隣接するTFTに電気的に接続している、構造。 - 前記検出素子ブランケット層は、下部半導体層と、その上側の上部半導体層と、下部半導体層と上部半導体層との間の真性半導体材料の層とを有し、PINダイオード検出素子を形成している、請求項21に記載の構造。
- 前記検出素子ブランケット層は、底面電極層上に配置されたp−nフォトダイオードブランケット層を含み、前記p−nフォトダイオードブランケット層は、アレイの隣接するフォトダイオードを分離する分離溝によってフォトダイオードのアレイに分離される、請求項21に記載の構造。
- 前記pn接合ブランケット層は、p型およびn型のいずれかの導電性を有する半導体材料の下層と、pn接合を形成するその逆の導電性を有する半導体材料の上部層とを含む、請求項23に記載の構造。
- 前記半導体材料の下層およびその上側の半導体材料の層を含むpn接合ブランケット層は、PINダイオードを形成する前記下層と前記上層との間の真性半導体の材料の層を更に含む、請求項24に記載の構造。
- 前記pn接合ブランケット層が、p−i1−n−i2−p層またはn−i1−p−i2−n層を構成する、請求項24に記載の構造。
- 分離溝によって各検出素子のアレイに分離される前記検出素子ブランケット層は、真性半導体の材料の層の一部にまで延びている前記分離溝を含む、請求項21に記載の構造。
- 前記分離溝の上側にあり前記各検出素子に隣接する前記ゲート電極は、前記分離溝の上側に設けられたデータラインおよびゲートスキャンラインを更に含む、請求項21に記載の構造。
- 前記ゲート電極の下側ならびに前記データラインおよびゲートスキャンラインの下側の分離溝に平坦化層が配置されている、請求項28に記載の構造。
- 前記平坦化層は、ポリマーPMGI、ポリスチレン、PMMA、もしくは他のタイプのアクリルポリマー、ポリエチレン、ポリイミド、ポリビニル・フェノール(PVP)、zeon、PET、PEN、PES、PAN、BCB、SU8、シランもしくはシロキシレーンベースの化合物、有機金属ベースの化合物、スピンオングラス、またはグラフィーム酸化物(grapheme oxides)から選ばれるいずれか1つの塗布層を含む、請求項29に記載の構造。
- 前記金属酸化物半導体材料の層は、検出素子の検出波長の光に対して透明な金属酸化物半導体材料の層を含む、請求項21に記載の構造。
- 前記透明な金属酸化物半導体材料は、非晶質もしくは多結晶質の透明な金属酸化物半導体材料である、請求項31に記載の構造。
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