JP2016500198A5 - - Google Patents

Download PDF

Info

Publication number
JP2016500198A5
JP2016500198A5 JP2015533073A JP2015533073A JP2016500198A5 JP 2016500198 A5 JP2016500198 A5 JP 2016500198A5 JP 2015533073 A JP2015533073 A JP 2015533073A JP 2015533073 A JP2015533073 A JP 2015533073A JP 2016500198 A5 JP2016500198 A5 JP 2016500198A5
Authority
JP
Japan
Prior art keywords
vias
interconnects
conductor
wall
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015533073A
Other languages
English (en)
Japanese (ja)
Other versions
JP6081600B2 (ja
JP2016500198A (ja
Filing date
Publication date
Priority claimed from US13/626,829 external-priority patent/US9054096B2/en
Application filed filed Critical
Publication of JP2016500198A publication Critical patent/JP2016500198A/ja
Publication of JP2016500198A5 publication Critical patent/JP2016500198A5/ja
Application granted granted Critical
Publication of JP6081600B2 publication Critical patent/JP6081600B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2015533073A 2012-09-25 2013-08-21 ノイズ減衰壁 Active JP6081600B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/626,829 US9054096B2 (en) 2012-09-25 2012-09-25 Noise attenuation wall
US13/626,829 2012-09-25
PCT/US2013/055993 WO2014051894A2 (en) 2012-09-25 2013-08-21 Noise attenuation wall

Publications (3)

Publication Number Publication Date
JP2016500198A JP2016500198A (ja) 2016-01-07
JP2016500198A5 true JP2016500198A5 (enExample) 2016-09-15
JP6081600B2 JP6081600B2 (ja) 2017-02-15

Family

ID=49054941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015533073A Active JP6081600B2 (ja) 2012-09-25 2013-08-21 ノイズ減衰壁

Country Status (6)

Country Link
US (1) US9054096B2 (enExample)
EP (1) EP2901478B1 (enExample)
JP (1) JP6081600B2 (enExample)
KR (1) KR102132046B1 (enExample)
CN (1) CN104704630B (enExample)
WO (1) WO2014051894A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343418B2 (en) * 2013-11-05 2016-05-17 Xilinx, Inc. Solder bump arrangements for large area analog circuitry
US10057976B1 (en) 2017-08-31 2018-08-21 Xilinx, Inc. Power-ground co-reference transceiver structure to deliver ultra-low crosstalk
US10665554B2 (en) * 2017-10-30 2020-05-26 Taiwan Semiconductor Manufacturing Company Ltd. Magnetic structure for transmission lines in a package system
CN111312692A (zh) * 2018-12-11 2020-06-19 创意电子股份有限公司 集成电路封装元件及其载板
KR20250073153A (ko) * 2022-09-22 2025-05-27 소니 세미컨덕터 솔루션즈 가부시키가이샤 반도체 패키지, 반도체 모듈, 전자 장치 및 반도체 패키지의 제조 방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03165058A (ja) 1989-11-24 1991-07-17 Mitsubishi Electric Corp 半導体装置
JPH11121643A (ja) * 1997-10-09 1999-04-30 Hitachi Ltd 半導体装置
JP3451038B2 (ja) * 1999-08-27 2003-09-29 シャープ株式会社 誘電体回路基板およびそれを含むミリ波半導体装置
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6486534B1 (en) 2001-02-16 2002-11-26 Ashvattha Semiconductor, Inc. Integrated circuit die having an interference shield
US6686649B1 (en) 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
JP4057921B2 (ja) * 2003-01-07 2008-03-05 株式会社東芝 半導体装置およびそのアセンブリ方法
WO2006004128A1 (ja) * 2004-07-06 2006-01-12 Tokyo Electron Limited 貫通基板およびインターポーザ、ならびに貫通基板の製造方法
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
KR100817070B1 (ko) * 2006-10-30 2008-03-26 삼성전자주식회사 다중 그라운드 쉴딩 반도체 패키지, 그 패키지의 제조방법 및 그 그라운드 쉴딩을 이용한 노이즈 방지방법
TWI337399B (en) * 2007-01-26 2011-02-11 Advanced Semiconductor Eng Semiconductor package for electromagnetic shielding
EP2019427B1 (en) 2007-07-27 2010-09-22 Fujitsu Semiconductor Limited Low-noise flip-chip packages and flip chips thereof
JP2009147150A (ja) * 2007-12-14 2009-07-02 Nec Electronics Corp 半導体装置
US8169059B2 (en) 2008-09-30 2012-05-01 Infineon Technologies Ag On-chip RF shields with through substrate conductors
JP5189032B2 (ja) * 2009-06-16 2013-04-24 新光電気工業株式会社 半導体装置および多層配線基板
CN102104033A (zh) * 2009-12-18 2011-06-22 中国科学院微电子研究所 三维混合信号芯片堆叠封装体及其制备方法
JP2011146519A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias

Similar Documents

Publication Publication Date Title
JP2016500198A5 (enExample)
WO2016118209A3 (en) Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
GB2523500A (en) Landing structure for through-silicon via
WO2015015319A3 (en) Architecture of spare wiring structures for improved engineering change orders
WO2015047321A8 (en) Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects
WO2010138480A3 (en) Stacked semiconductor device assembly
WO2015127207A4 (en) Method and apparatus for incorporating passive devices in an integrated passive device separate from a die
WO2014043316A3 (en) Hybrid on-chip and package antenna
EP3483932A3 (en) Ground via clustering for crosstalk mitigation
WO2012087475A3 (en) Substrate with embedded stacked through-silicon via die
WO2010144843A3 (en) Intra-die routing using through-silicon via and back side redistribution layer and associated method
WO2016209668A3 (en) Structures and methods for reliable packages
WO2011097165A3 (en) Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
JP2012009847A5 (enExample)
TW201613050A (en) Semiconductor device
WO2015130549A3 (en) Selective conductive barrier layer formation
SG11201907932UA (en) Semiconductor memory device
WO2015123426A3 (en) Integrated device comprising stacked dies on redistribution layers
JP2015012609A5 (enExample)
WO2011103266A3 (en) Shielding structure for transmission lines
JP2017507495A5 (enExample)
WO2012070821A3 (ko) 플립플롭 회로의 레이아웃 라이브러리
WO2008102326A3 (en) In-grid decoupling for ball grid array (bga) devices
JP2016513872A5 (enExample)
WO2014189983A8 (en) Charge damage protection on an interposer for a stacked die assembly