JP2016195666A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of effective use of a program and a storage area of data.SOLUTION: A main control part 41 is provided with a 1 byte RST command which designates a specific address assigned to a ROM 41b in an amount of data smaller than an address and is capable of calling a program of the designated specific address and performing the program. In an area started with one specific address in the ROM 41b, a first specific program, for example, a sub-routine of external signal off time waiting processing is stored; in an area stared with a next specific address, a second specific program, for example, a sub-routine of output port 2 output processing is stored; and in an area from after the first specific program to right before the next specific address, that is, a free space between the first specific program and the second specific program, a prescribed program equal to or smaller than the amount of data equivalent to the free space or a part of the prescribed program, for example, a sub-routine of maximum charged token number set corresponding to the amount of data in the free space is stored.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine.

  In this type of gaming machine, a program used by the gaming machine for control includes a plurality of types of main modules and common sub-modules, and is stored in the ROM. Each common submodule is stored starting from one of a plurality of specific addresses specified by a parameter having a data size smaller than the program address in the ROM, and is specified by another module, for example, by an RST instruction When an address is specified, it is called and executed. (For example, refer to Patent Document 1).

JP 2004-229938 A

  In the gaming machine described in Patent Document 1, since one of a plurality of specific addresses is stored in the ROM so that the common submodule can be called by an RST instruction, the next specific is determined from one specific address in the ROM. When the data amount of the common submodule is smaller than the capacity of the area up to the address, the ROM area from the end of the stored common submodule to the next specific address may become an empty area. The area was not used effectively.

  The present invention has been made paying attention to such problems, and an object thereof is to provide a gaming machine capable of effectively using a storage area for programs and data.

In order to solve the above problems, the gaming machine of means 1 of the present invention is:
In a gaming machine (slot machine 1) that performs a game,
Storage means (ROM 41b) to which an address capable of storing a program and specifying a storage area is assigned;
Control means (main control unit 41) for performing control according to the program stored in the storage means;
First program calling means (CALL instruction, CALLV instruction) for calling a program stored at the specified address by specifying an address;
A plurality of specific addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H) assigned at predetermined intervals (8 bytes) by specifying a parameter with a data amount smaller than the address (3-bit parameter) Second program calling means (RST instruction) for calling a program (for example, a subroutine for waiting for external signal off time) stored at a specific address corresponding to a designated parameter of
With
The storage means stores a first specific program (for example, a subroutine for waiting for external signal off time) in an area starting from one specific address, and stores the first specific program in an area starting from the specific address next to the one specific address. 2 specific programs (for example, a subroutine for output port 2 output processing) are stored, and a predetermined program (for example, maximum inserted medal number) is stored in an area after the area where the first specific program is stored and before the next specific address. It is characterized by memorizing the subroutine of set processing.
According to this feature, a program stored in a specific address corresponding to a specified parameter among a plurality of specific addresses assigned at predetermined intervals can be called by specifying a parameter having a data amount smaller than the address. Therefore, the program capacity related to the program call can be reduced. Further, an area between the first specific program stored in the area starting from one specific address and before the next specific address, that is, a space between the first specific program and the second specific program. By storing a predetermined program in the area, the area of the storage means can be used effectively.

The gaming machine of means 2 of the present invention is the gaming machine described in means 1,
The control means is characterized in that the second specific program (for example, a subroutine for addition processing) is executed following the predetermined program (for example, a subroutine for setting value display data acquisition processing).
According to this feature, the predetermined program is stored in the area before the next specific address after the area in which the first specific program is stored, and the second specific program is executed following the predetermined program, Only by calling the predetermined program by the first program calling means, it is not necessary to call the second specific program by the second program calling means after the predetermined program ends, and the program capacity related to this can be reduced.

The gaming machine of means 3 of the present invention is the gaming machine according to means 1 or means 2,
The predetermined program is other than an area (specific address area) in which the predetermined program (for example, a part of a program having a data amount larger than an empty area between the first specific program and the second specific program) is stored. A jump instruction to a program stored in the area (for example, the remaining part of the program stored in the empty area) is included.
According to this feature, since the predetermined program includes a jump instruction to a program stored in an area other than the area where the predetermined program is stored, a space between the first specific program and the second specific program By storing a part of the program having a larger amount of data than the area in the empty area as a predetermined program, the area of the storage means can be used effectively.

The gaming machine of means 4 of the present invention is the gaming machine according to any one of means 1 to means 3,
A program starting from a specific address is transferred to a program (for example, the remaining part of the port output process) stored in an area other than the area (specific address area) in which the program (for example, a part of the port output process) is stored. It is characterized by including a jump command.
According to this feature, a program starting from a specific address includes a jump instruction to a program stored in an area other than the area in which the program is stored, and therefore, more data than an area from a specific address to the next specific address. Since a large amount of program can be called by the second program calling means, even if the program has a large amount of data, the program capacity related to the call can be reduced.

A gaming machine of means 5 of the present invention is the gaming machine according to any one of means 1 to 4,
The storage means
A first storage area (game program area) for storing a game program (game program) related to the progress of the game;
A second storage area (non-game program area) in which a non-game program (non-game program) that is called by the game program and is not involved in the progress of the game is stored;
An unused area allocated to an area immediately before a rear storage area (non-game program area) allocated behind the first storage area (game program area) and the second storage area (non-game program area). Unused area 1)
It is characterized by having.
According to this feature, a first storage area that stores a game program related to the progress of the game, and a second storage area that is a program called by the game program and stores a non-game program not related to the progress of the game; Are allocated separately, and an unused area is allocated to the area before the rear storage area allocated behind the first storage area and the second storage area. The game program can be easily specified according to the difference in the storage area.
In addition, before and after the storage area is a magnitude relationship between the address values assigned to the storage area, and the smaller address is the front and the larger address is the rear. For this reason, the rear storage area allocated backward in the first storage area and the second storage area in the means 5 has a larger address value allocated in the first storage area and the second storage area. This corresponds to the storage area.
Further, any configuration may be used as long as the unused area is allocated before the rear storage area, and the front storage area, the unused area, and the rear storage area may be allocated adjacent to each other, or the front storage area and the unused area may be allocated. Another storage area may be allocated between the two.

A gaming machine of means 6 of the present invention is the gaming machine according to any one of means 1 to 5,
The control means includes an interrupt process execution means for executing a process according to an interrupt program (timer interrupt process (main)) based on the interrupt,
The gaming machine is
Address storage means (vector table) capable of storing the address of the interrupt program (timer interrupt processing (main));
Determining means for determining at startup whether or not the address stored in the address storage means (vector table) is within a predetermined range (area in which a program or the like is actually stored in the program area);
Activation restriction means for restricting activation when it is determined that the address stored in the address storage means (vector table) is not within a predetermined range (the main control unit 41 has a vector table address within a program area such as a program Do not start if it is not the actual storage area),
It is characterized by having.
According to this feature, unintended interrupt processing can be prevented in advance.

A gaming machine according to means 7 of the present invention is the gaming machine according to any one of means 1 to 6, wherein
Setting means for setting the control means (setting of various functions performed with reference to HW parameters);
Interrupt generation means (timer circuit 509) for generating an interrupt in response to the establishment of the interrupt condition;
Interrupt limiting means for limiting the generation of interrupts by the interrupt generating means;
With
The control means includes
Processing means for executing processing based on a program (game program or non-game program) after setting by the setting means;
An interrupt process execution means for executing an interrupt process (timer interrupt process (main)) based on the interrupt;
Including
The interrupt restricting means includes a first interrupt restricting means (setting for prohibition of interruption by setting at startup) and a program for restricting the generation of interrupts before processing based on a program (initial setting process) is started. And a second interrupt restricting means for restricting the generation of interrupts at the start of the processing based on (setting of prohibition of interrupts by the initial setting process).
According to this feature, it is possible to prevent an unintended interrupt from occurring.

A gaming machine according to means 8 of the present invention is the gaming machine according to any one of means 1 to 7,
A plurality of timer value storage areas (for example, 1-byte timers A to C);
When any type of timing condition is satisfied among a plurality of types of timing conditions (for example, timing conditions for 1-byte timers A to C), a timer value storage area (for example, 1-byte timer A) corresponding to the timing condition To C), a timer value storage means (main process) for storing a timer value according to the timing condition;
Timer value updating means (time counter updating process) capable of updating timer values stored in a plurality of timer value storage areas (for example, 1-byte timers A to C) at predetermined intervals (about 2.24 ms);
With
A plurality of timer value storage areas (for example, 1-byte timers A to C) are assigned consecutive addresses (804CH to 804EH) according to a predetermined rule (+1),
The timer value updating means performs a predetermined operation (specified address + 1) for an update process for updating the timer value stored in the timer value storage area corresponding to the specified address (a process for subtracting 1 from the value indicated by the pointer). It is characterized in that multiple types of timer values can be updated by repeatedly executing while changing the designated address for the timer value storage area.
According to this feature, a plurality of timer value storage areas are assigned consecutive addresses according to a predetermined rule, and an update process for updating the timer value stored in the timer value storage area corresponding to the specified address is performed in a predetermined manner. When the processing for updating multiple types of timer values is performed for each type of timer value, it is possible to update multiple types of timer values by repeatedly executing while changing the specified address for the timer value storage area. As a result, the program capacity can be reduced.
Note that consecutive addresses are assigned according to a predetermined rule means that, for example, an address that is incremented by N (N is a natural number) from the start address and the start address is assigned.
In addition, changing the designated address for the timer value storage area by performing a predetermined calculation is, for example, changing the designated address by adding or subtracting a value according to the number of processes to the current designated address, This corresponds to changing the designated address by adding or subtracting a constant to or from the reference address. At this time, the value or constant according to the number of processes may vary depending on the storage capacity of the timer value. For example, if the timer value is stored byte by byte, the value according to the number of processes is the number of processes. Depending on the number of processing, the value is 2, 4, 6,..., Depending on the number of processing. The constant is 2.

  In addition, this invention may have only the invention specific matter described in the claim of this invention, and has a structure other than this invention specific matter with the invention specific matter described in the claim of this invention. It may be a thing.

It is a front view of the slot machine of the Example to which this invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows the memory map of ROM and RAM which a main control part mounts. It is a figure which shows the detail of the memory map of ROM and RAM which a main control part mounts. It is a figure which shows the detail of the memory map of the program area in ROM mounted in the main control part. It is a figure which shows the structure of a game program and a non-game program. It is a figure which shows the relationship between a game area | region and a non-game area | region. It is a flowchart which shows the flow of a process at the time of calling a non-game program. It is a flowchart which shows the control content of the initial setting process which a main control part performs. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the main process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs. It is a flowchart which shows the control content of the command storage process which a main control part performs. It is a flowchart which shows the control content of the normal time command transmission process which a main control part performs. It is a flowchart which shows the control content of the command transmission process at the time of a power failure which a main control part performs. It is a flowchart which shows the control content of the power interruption process which a main control part performs. It is a timing chart for demonstrating the flow of control at the time of starting of a main control part and a sub-control part, and a power failure. It is a flowchart which shows the control content at the time of a main control part determining the value of a timer counter in a main process. It is a figure which shows the storage area of the timer counter in RAM. It is a flowchart which shows the control content of the time counter update process which a main control part performs.

  A mode for carrying out a gaming machine according to the present invention will be described below based on examples.

  An embodiment of a slot machine that is a gaming machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. The front door 1b is pivotally supported at the side end of the body 1a.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  A plurality of types of symbols (identification information) that can be distinguished from each other are drawn in a predetermined order on the outer peripheral portions of the reels 2L, 2C, and 2R. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided at the approximate center of the front door 1b.

  The reels 2L, 2C, and 2R are rotated by reel motors 32L, 32C, and 32R (see FIG. 3) provided in correspondence with each other, so that the symbols of the reels 2L, 2C, and 2R are continuous with the see-through window 3. On the other hand, when the reels 2L, 2C, and 2R are stopped from rotating, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols on the reels 2L, 2C, and 2R, and each symbol can be irradiated independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the front side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a transmissive liquid crystal panel in a state where no voltage is applied to the liquid crystal element, and the transmissive area 51b corresponding to the transmissive window 3 of the display area 51a and the transmissive window 3 are interposed. Thus, the reels 2L, 2C, and 2R can be visually recognized from the player side.

  As shown in FIG. 1, on the front door 1b, there are a medal insertion portion 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). Using the MAXBET switch 6 that is operated when setting the maximum bet number among the prescribed number of bets determined according to the gaming state within the range, setting of medals and bets stored as credits Settlement switch 10 that is operated when the medals used in the game are settled (the medals used for setting credits and bets are returned), start switch 7 that is operated when the game is started, and reels 2L and 2C. Stop switches 8L, 8C, and 8R that are operated when stopping the rotation of 2R are provided so as to be operable by the player.

  Further, as shown in FIG. 1, the front door 1b shows a credit indicator 11 for displaying the number of medals stored as credits, the number of medals paid out due to the occurrence of a winning, and the contents when an error occurs. An auxiliary game indicator 12 for displaying an error code or the like, 1 BETLED 14 for informing that the bet number is set to 1 by lighting, 2 BETLED 15 for informing that the bet number is set to 2, and 3 betting numbers being set A 3BET LED 16 for notifying that the game has been performed, an insertion request LED 17 for notifying that a medal can be inserted by lighting, and a start valid LED 18 for notifying that the game start operation by operating the start switch 7 is effective. , Wait (reel rotation starts because a certain period has not elapsed since the start of the previous game Waiting to have state) in wait for notifying by lighting the effect that in LED 19, a game display section 13 in the replay LED20 is provided for informing it is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 3) for notifying that the betting number setting operation by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle and right stop valid LEDs 22L, 22C and 22R (see FIG. 3) for notifying that the reel stop operation by the corresponding stop switches 8L, 8C and 8R is effective are provided inside the 8R. It has been.

  Inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting a reset operation for releasing an error state to be described later and a stop state to be described later by a predetermined key operation, and changing a set value to be described later A set value display 24 that displays the set value at that time while checking the set value, and a hit that controls to a stop state (a state in which the progress of the game is restricted until a reset operation is performed) at a predetermined trigger A stop switch 36a for selecting the validity / invalidity of the stop function, automatic control for automatic settlement processing (processing to settle (return) medals stored as credits regardless of the player's operation) at a predetermined opportunity An automatic settlement switch 36b for selecting validity / invalidity of the settlement function, and a flow path for medals inserted from the medal insertion section 4 are provided in a hopper tank 34a (described later) provided inside the housing 1a. 2) or a medal payout outlet 9 for selectively switching to one of the flow path switching solenoid 30 and the medal insertion part 4, and a medal sensor 31 for detecting a medal that has flowed to the hopper tank 34a side. A medal selector 29 having an insertion port sensor 26 for detecting insertion of a foreign object on the upstream side of the insertion medal sensor 31 and a door open detection switch 25 (see FIG. 3) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R (see FIG. 3), and the reel reference positions of the reels 2L, 2C, and 2R are respectively provided in the housing 1a. Reel unit 2 comprising detectable reel sensors 33L, 33C, 33R (see FIG. 3), external output board 1000 (see FIG. 3) for outputting an external output signal, and medal inserted from medal insertion unit 4 are stored. Hopper tank 34a, a hopper motor 34b for paying out medals stored in the hopper tank 34a from the medal payout opening 9 (see FIG. 3), and a payout sensor 34c for detecting the medals paid out by driving the hopper motor 34b (see FIG. 3). A hopper unit 34 and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full tank sensor 35a (see FIG. 3) for detecting that the stored medal is full is provided.

  As shown in FIG. 2, a function key switch 37 for switching to a setting change state or a setting confirmation state is provided on the front surface of the power supply box 100, and functions as a reset switch for canceling an error state or a stop state in normal times. In the setting change state, a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery described later, and a power source that is operated when the power is turned ON / OFF A switch 39 is provided.

  The power supply box 100 is provided inside the housing 1a, and the front door 1b can be opened by a predetermined key operation held by a store clerk or the like. The set key switch 37, the reset / setting switch 38, and the power switch 39 are operated only by a person such as a store clerk who has the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after the front door 1b is opened by key operation, only the store clerk possessing the key for operating the setting key switch 37 among the game store clerk. Operation is possible.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is used as the winning line. It has been established. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  Further, in the present embodiment, invalid lines LM1 to LM1 are set apart from the winning line LN in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols arranged in the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, the invalid line is displayed. When a combination of symbols (for example, bell-bell-bell) that is awarded when the winning line LN is aligned with any of the LM1 to LM4 is arranged, the symbols constituting a specific winning in the winning line LN It is easy to recognize that the combination is complete.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a winning combination) is displayed on the reels 2L, 2C, 2R on the winning line LN. If the game stops as a result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state on the winning line LN is stopped as a display result of each reel 2L, 2C, 2R, the gaming state according to the combination of symbols is shifted. .

  In this embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. Further, one unit of control (game control) for executing a game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

  In this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, a configuration using four or more reels may be used. In the configuration using two or more reels, a winning determination may be made based on a combination of display results derived for all two or more reels. In this embodiment, the variable display device is configured by physical reels. However, the variable display device may be configured by an image display device such as a liquid crystal display.

  In the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated and the symbols start to change, any one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped, and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. The symbols arranged within 5 frames including can be displayed on the winning line.

  Hereinafter, the reels 2L, 2C, and 2R may be simply referred to as reels unless it is necessary to distinguish between them. Further, the reel 2L may be referred to as a left reel, the reel 2C as a middle reel, and the reel 2R as a right reel. Further, an operation for stopping the reels 2L, 2C, 2R by operating the stop switches 8L, 8C, 8R may be referred to as a stop operation.

  FIG. 3 is a block diagram showing the configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the effect control board 90 are generated. To be supplied. Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input. Further, the game control board 40 includes the credit indicator 11, the game auxiliary indicator 12, 1-3 BET LEDs 14-16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, the BET switch valid LED 21, the left The middle and right stop valid LEDs 22L, 22C and 22R, the set value display 24, the flow path switching solenoid 30, the reel motors 32L, 32C and 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electrical components are connected, and are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41 that performs processing related to the progress of the game, a control clock generation circuit 42 that generates a control clock CCLK, a random number clock generation circuit 43 that generates a random number clock RCLK, and switches. A switch detection circuit 44 that captures the input detection signal and transmits it to the main control unit 41, a motor drive circuit 45 that transmits a motor drive signal (phase signal of the stepping motor) to the reel motors 32L, 32C, and 32R, and a solenoid drive signal A solenoid drive circuit 46 that transmits to the flow path switching solenoid 30, an LED drive circuit 47 that transmits LED drive signals to various displays and LEDs, and a voltage drop signal indicating that when a voltage drop is detected, the main control unit 41 The power interruption detection circuit 48 that outputs to the Source reset circuit 49 to provide the system reset signal to the main control unit 41 is mounted in an unstable state.

  FIG. 4 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 4 is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a verification block 503, a specific information storage circuit 504, an arithmetic circuit 505, and a reset / interrupt. A controller 506, a CPU (Central Processing Unit) 41a, a ROM (Read Only Memory) 41b, a RAM (Random Access Memory) 41c, a free-run counter circuit 507, random number circuits 508a and 508b, a timer circuit 509, The interrupt controller 510 includes a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decoding circuit 514.

  The reset / interrupt controller 506 is for controlling various resets and interrupt requests generated inside or outside the main control unit 41. The reset / interrupt controller 506 includes an out-of-designated area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it is detected that the user program is executed outside the designated area. The watchdog timer 506b has a function of generating a timeout signal for each set period.

  The external bus interface 501 is a bus interface having an interface function between an external bus and an internal bus of a chip constituting the main control unit 41, an address bus, a data bus, and a direction control function of each control signal. The clock circuit 502 is a circuit that generates the internal system clock SCLK by, for example, dividing the control clock CCLK by two. The verification block 503 is connected to an external verification machine and has a function of performing chip verification. The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information that is internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

  The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, the CPU 41a reads fixed data from the ROM 41b, the variable data writing operation in which the CPU 41a writes various fluctuation data to the RAM 41c and temporarily stores them, and the CPU 41a is temporarily stored in the RAM 41c. A variable data reading operation for reading out various variable data being received, a receiving operation in which the CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, etc. However, a transmission operation for outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like is also performed.

  The ROM 41b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The RAM 41c provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

  As the free-run counter circuit 507, an 8-bit free-run counter is mounted. The random number circuits 508a and 508b are circuits that generate numerical data that is a random value having a predetermined update range, such as an 8-bit random number or a 16-bit random number. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is used as a random number for internal lottery described later. The timer circuit 509 is a 16-bit programmable timer, counts down the set timer value based on the input of the control clock CCLK, and outputs an interrupt request signal to the interrupt controller when reaching 0000H. In this embodiment, the timer circuit 509 can be used to perform periodic interrupt requests and time measurement.

  The interrupt controller 510 is a circuit that controls external interrupt requests from interrupt terminals and interrupt requests from built-in peripheral circuits (for example, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). . The parallel input port 511 incorporates an 8-bit wide input-only port. Also, the parallel output port 513 provided in the main control unit 41 shown in FIG. 4 incorporates an output-only port having an 11-bit width. The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output with respect to the outside.

  The address decoding circuit 514 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. In response to the chip select signal, the internal circuit of the main control unit 41 or the external device serving as a peripheral device is selectively operated effectively and can be accessed from the CPU 41a.

  The main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41. In this embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but via the serial communication circuit 512. A configuration in which a command is transmitted to the sub-control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be employed.

  The main control unit 41 also receives detection states of various switches connected to the game control board 40 from the parallel input port 511. The main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from the parallel input port 511. Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In this embodiment, a timer interrupt process (main), which will be described later, is executed every time a time-out occurs in the timer circuit 509, that is, every fixed time interval (about 0.56 ms in this embodiment). The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  The effect control board 90 is connected to effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55. These effect devices are sub-controls described later mounted on the effect control board 90. It is driven based on control by the unit 91. In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units. Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and a liquid crystal display connected to the effect control board 90, a sub control unit 91 for effect control. 51, a display control circuit 92 for performing display control, an LED driving circuit 93 for controlling driving of the effect LED 52 and the reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53, 54, when the power is turned on or from the sub CPU 91a The reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command is not input for a certain period of time, the switch detection circuit 96 that detects the detection signal input from the switches connected to the effect control board 90, date information and time Clock device 97 for outputting time information including information, slot machine 1 The power supply voltage to be supplied is monitored, and when a voltage drop is detected, a power failure detection circuit 98 that outputs a voltage drop signal to that effect to the sub CPU 91a, and other circuits are mounted. In response to the command transmitted from the game control board 40, the CPU 91a performs various controls for performing an effect, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the input number of system clocks reaches a certain number, that is, every certain time interval (about 2 ms). Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time. The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to the set value in a lottery that affects the advantage to the player, such as an internal lottery, a navigation stock lottery, and an extra lottery to be described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed on the setting value display 24 as a display value, and the setting value can be changed by operating the reset / setting switch 38. Transition to the changed state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the set value display 24 is updated one by one (when the set value 6 is further operated, the set value 1 is set. Return). When the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned OFF, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In addition, when the setting key switch 37 is turned on and the power is turned on, the door opening detection switch 25 may detect that the front door 1b is opened, and shift to the setting change state. Well, by adopting such a configuration, it is possible to prevent unauthorized setting changes in a state where the front door 1b is not opened. Further, in the configuration that shifts to the setting change state on the condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 supports the opening of the front door 1b after shifting to the setting change state. Even if the detection is not detected, it is preferable to maintain the setting change state. Thus, even if the front door 1b is temporarily closed during the setting change, an operation for shifting to the setting change state is performed again. This is not necessary, and the setting change operation is not complicated. Further, after the transition to the setting change state, when the setting value is determined by operating the start switch 7 and then the setting key switch 37 is turned OFF, the door opening detection switch 25 detects that the front door 1b is opened. On the condition that the setting change state is terminated, it may be configured to shift to a state in which the game can proceed. Even in such a configuration, the front door 1b is not opened in an unauthorized manner. It is possible to prevent the setting from being changed.

  In order to confirm the set value, after the game is over, the setting key switch 37 may be turned on with no bet amount set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by turning the setting key switch 37 to the OFF state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  It should be noted that, after the game is over, when the setting key switch 37 is turned on with no bet amount set, the door opening detection switch 25 detects that the front door 1b is opened. In addition, a configuration for shifting to the setting confirmation state may be adopted. By adopting such a configuration, it is possible to prevent the setting value from being illegally confirmed without the front door 1b being opened. In addition, in the configuration that shifts to the setting confirmation state on the condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 supports the opening of the front door 1b after the transition to the setting confirmation state. It is preferable to maintain the setting confirmation state even if the detection to be performed is not performed. Thus, even if the front door 1b is temporarily closed during the setting confirmation, an operation for shifting to the setting confirmation state again is performed. This is not necessary and the setting confirmation operation is not complicated. Further, after shifting to the setting confirmation state, when the set key switch 37 is turned off after the set value is confirmed by operating the start switch 7, the detection corresponding to the opening of the front door 1b is performed by the door opening detection switch 25. On the condition that the setting confirmation state is terminated, it may be configured to return to a state in which the game can proceed, and even in such a configuration, the front door 1b is not opened in an unauthorized manner. It is possible to prevent the setting value from being confirmed.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interruption process (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, a power interruption process (main) for setting data for determining whether or not the data in the RAM 41c is normal at the next return is performed. Run.

  Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power interruption based on the data stored in the RAM 41c on the condition that the data in the RAM 41c is normal at the time of activation. However, if the RAM 41c data is not normal, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state, thereby disabling the progress of the game.

  The error state shifts to a normal error state that is canceled by a reset operation (operation of the reset / setting switch 38 or the reset switch 23) and the setting change state described above, and is canceled until a new setting value is set. Special error status with no error, the RAM abnormal error status is a special error status, and once it is controlled to the RAM abnormal error status, it shifts to the setting change status and is released until a new set value is set. It will not be done.

  Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interruption process (sub), and when it is determined that the voltage drop signal is detected, A power interruption process (sub) for setting data for determining whether or not the data in the RAM 91c is normal at the next return is executed.

  Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power interruption based on the data stored in the RAM 91c on the condition that the data of the RAM 91c is normal at the time of activation. However, if the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In addition, even when it is determined that the data in the RAM 91c is normal at the time of activation, the sub control unit 91 activates when receiving a setting command (described later) indicating that the setting change state has been entered from the main control unit 41. Even when a later-described return command or setting command indicating that the control state of the main control unit 41 has returned is not received even after a certain period of time has elapsed, the RAM 91c is initialized. In this case, the execution of the performance is not disabled only by initializing the RAM 91c.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The usable area in the storage area of the RAM 41c of the main control unit 41 is divided into an important work, a special work, a general work, an unused area, and a stack area, and an important work, a special work, a general work, and an unused area. Are arranged in the stack area order.

  In this embodiment, the main control unit 41 has the data in the RAM 41c when the setting key switch 37 is turned on and the data in the RAM 41c is destroyed when the setting key switch 37 is turned on. When it is not destroyed, when the setting key switch 37 is turned on and the data in the RAM 41c is destroyed, when the setting change is finished, when a specific gaming state is finished, when one game is finished, from six When the initialization condition is satisfied, four types of initializations with different areas initialized according to each initialization condition are performed.

  Initialization 0 is when the data in the RAM 41c is destroyed when the setting key switch 37 is turned off and when the data in the RAM 41c is destroyed when the setting key switch 37 is turned on. In the initialization 0, all the usable areas are initialized. Initialization 1 is initialization that is performed when data in the RAM 41c is not destroyed at the time of start-up with the setting key switch 37 being ON. In the initialization 1, other than important work and special work in the usable area. This area is initialized. Initialization 2 is initialization performed at the end of a specific gaming state. In initialization 2, a general work, an unused area, and an unused stack area are initialized among available areas. Initialization 3 is initialization performed at the end of one game. In initialization 3, an unused area and an unused stack area are initialized among the available areas. The storage area for the data indicating the set value and the game state is allocated to the special work, and when the data in the RAM 41c is not destroyed at the time of startup with the setting key switch 37 being ON, that is, the data in the RAM 41c. When the game is normal and the setting is changed, data indicating the setting value and the gaming state is held. Further, a storage area for a timer counter, which will be described later, is allocated to a special work and is held without being initialized at the end of the game or at the end of a specific gaming state.

  In the slot machine 1 of the present embodiment, a prescribed number of bets that can be set according to the gaming state is determined, and the game is performed on the condition that the prescribed number of bets determined according to the gaming state is set. Can be started. In the present embodiment, the winning line LN is activated when a specified number of bets according to the gaming state are set.

  In this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line is activated (in the present embodiment, all the pay lines are always activated. A winning combination is obtained when a combination of symbols called “combinations” is arranged on the winning line. The combination may be a combination of the same symbols or a combination including different symbols.

  The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c. Of these winning flags, the winning flags for the small role and the replaying role are valid only in the game in which the flag is set, and are invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combinations permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, whether or not the main control unit 41 allows the winning of each combination described above before the display results of all the reels 2L, 2C, and 2R are derived (specifically, the start switch 7 At the time of detection). In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value generated by the random number circuit 508b and stored in the random number value register of the random number circuit 508b is set as the lottery work assigned to the RAM 41c. And, for each combination determined according to the gaming state, according to the numerical data stored in the lottery work and the number of determination values of each combination determined according to the current gaming state, the number of bets and the set value A determination is made as to whether or not winning is permitted.

  In the internal lottery, the number of judgment values determined in accordance with the internal lottery target, the current gaming state, and the set value are sequentially assigned to the random number for internal lottery (numerical data stored in the lottery work). When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described. The main control unit 41 refers to the table index and table creation data stored in the ROM 41b when the reel starts to rotate and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In this embodiment, a value of 0 to 4 is determined as the number of sliding symbols, and it is possible to stop the reel by drawing in a maximum of 4 symbols after detecting a stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In this embodiment, if any of the winning combinations is won, when the stop operation is performed, the winning combination can be stopped on the winning line within a drawing range of up to four frames. If possible, control is performed to align and stop, and the winning combination that has not been won is controlled to be stopped without being aligned in the drawing range of a maximum of 4 frames. When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the maximum on the winning line when the stop operation is performed If it is possible to align and stop the winning roles in the 4-frame pull-in range, control will be performed to align them and stop them, and the winning roles will be selected on the winning line within the maximum 4-frame pull-in range. If it is not possible to withdraw, if a special role that has been elected within the draw range of up to 4 frames can be aligned and stopped on the winning line, it will be controlled and stopped. Control to stop without aligning in the drawing range of 4 frames will be performed. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. In the case where a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn, and the small combination is not aligned on the winning line at the same time as the special combination. Also, when a special role and a small role are elected at the same time, priority is given to the control of aligning the special role on the winning line over the small role, and only when the special role cannot be drawn, the small role is placed on the winning line. You may perform control to align.

  Also, in this embodiment, when the special role and the replaying role are won at the same time, such as when the replaying role is won while the special role has been carried over from before the previous game, the stop operation is performed. In this case, the control is performed so that the symbols of the re-gamer are aligned and stopped on the winning line within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not arranged on the winning line at the same time as the re-playing combination.

  In this embodiment, the reel stop control is performed by using a stop control table that can specify the number of sliding frames for each timing at which the stop operation is performed. A configuration that performs stop control by specifying the stop position from the table and stopping the reel at the specified stop position, and searching for a stop position that can be stopped when the stop operation is performed without using the stop control table or the stop position table. A configuration that performs stop control that identifies and stops the reel at the specified stop position, stop control using the stop control table, stop control using the stop position table, and can be stopped without using the stop control table or the stop position table A configuration that uses stop control by searching and specifying the stop position together, and a configuration that performs stop control by partially changing the stop control table and stop position table. It may be.

  In the present embodiment, the main control unit 41 measures the game time, which is the time elapsed from the start of the reel rotation every time the reel starts rotating after the game starts. After a game is over, when a specified number of bets are set by inserting medals, etc., and the game start operation is enabled, the reel start of the previous game is started. If the game time that has started counting from the time is more than the specified time (4.1 seconds in this embodiment), that is, if the specified time has elapsed since the reel rotation start time of the previous game, no wait is generated. At that time, the reel for the game in the game is started to rotate. On the other hand, after the end of one game, when a predetermined number of bets are set by inserting medals, etc., and when the game start operation is enabled, the reel rotation of the previous game is started. If the game time that started timing from the time is less than the specified time, that is, if the specified time has not elapsed since the start of reel rotation of the previous game, a wait is generated and the reel starts rotating at that time. First, it waits until the game time that has started timing from the reel rotation start time of the previous game reaches the specified time, and starts rotating the reel when it reaches the specified time.

  In the present embodiment, the main control unit 41 performs control to output an external output signal indicating a gaming state, an error occurrence state, and the like. These external output signals are output to a hall device such as a hall computer via the information output terminal board of the game shop (hall) where the external output board 1000 and the slot machine 1 are installed.

  The main control unit 41 has a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals awarded to the player due to the occurrence of winning, and the gaming state is RB (regular bonus). RB signal indicating the effect, BB signal indicating that the gaming state is BB (big bonus), RT signal indicating that RT2 is in progress, door opening signal indicating that the front door 1b is open, which will be described later A setting change signal indicating the transition to the setting change mode, an insertion error signal indicating an abnormality of the medal selector, and a payout error signal indicating an abnormality of the hopper unit 34 are output.

  The external output board 1000 is provided with a relay circuit, a parallel / serial conversion circuit, a terminal for each output signal, and a connector to be electrically connected to the circuit of the information providing terminal board. Of the signals output from the game control board 40, the medal IN signal, the medal OUT signal, the RB signal, and the BB signal are directly output as pulse signals to the information providing terminal board via the relay circuit. On the other hand, the door opening signal, setting change signal, input error signal, and payout error signal are converted into security signals, which are serial signals that can be individually identified by the parallel-serial conversion circuit, and information is provided. Output to the terminal board.

  Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In the present embodiment, the main control unit 41 sends, to the sub-control unit 91, a throw-in number command, a credit command, a gaming state command, an internal winning command, a reel acceleration information command, a stop operation time command, a sliding frame number command, a stop A plurality of types of commands including a command, a game end command, a winning number command, a payout start command, a payout end command, a standby command, a stop command, an error command, a return command, a setting command, a setting confirmation command, and a door command are transmitted.

  The inserted number command is a command that can specify the number of inserted medals, that is, the number of medals used for setting the number of bets, and is a state from the end of the game (after changing the setting) to the start of the game. Or, when a prescribed number of bets is not set, a medal is inserted, or when the bet number is set by operating the MAXBET switch 6. The inserted number command is transmitted when the betting number setting operation is performed, so that it is possible to specify that the betting number setting operation has been performed by receiving the inserted number command. The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The game state command is a command that can specify the game state of the game, and is transmitted when the start switch 7 is operated to start the game. The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game and after the gaming state command is transmitted. Since the game state command and the internal winning command are transmitted when the start switch 7 is operated and the game starts, it is possible to specify that the game is started by operating the start switch 7 by receiving these commands. It is.

  The reel acceleration information command is a command that can specify that the rotation of the reel starts with the progress of the game, and is transmitted when the rotation of the reel starts with the progress of the game. The stop operation command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the area number of the stop operation position of the corresponding reel. Sent every time the accompanying stop control is performed. The sliding frame number command is a command that can specify whether the reel to be stopped is a left reel, a middle reel, or a right reel, and the number of sliding frames to be moved from when the corresponding reel is stopped until it stops. Each time stop control associated with the stop operation of each reel is performed, the corresponding stop operation command is transmitted after being transmitted. The stop command is a command that can specify whether the reel to be stopped is a left reel, a middle reel, or a right reel, and the area number of the stop position of the corresponding reel. Stop control associated with the stop operation of each reel Is transmitted after the corresponding sliding frame number command is transmitted. With the stop operation command, the sliding frame number command, and the stop command, it is possible to specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and accompanying the stop operation of each reel Since it is transmitted every time stop control is performed, by receiving these commands, it is possible to specify that one of the reels has been stopped and the reel to be stopped.

  The game end command is a command that can specify that the game has ended, and is transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. The winning number command is a command that can specify a combination of symbols arranged on the winning line LN, whether or not a winning is received, a type of winning, and a payout number of medals at the time of winning. The player stops the third stop reel. This is when the stop switch is pressed and released, and is transmitted after the game end command is transmitted. Both the game end command and the winning number command are transmitted when the player depresses the stop switch to release the third stop reel and releases the stop switch. It is possible to specify that all operations necessary to advance one game have been completed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The stand-by command is a command indicating a transition to the stand-by state. When one game is over and the bet amount is not set and the estimated end time (60 seconds in this embodiment) has passed, It is transmitted after the payout of medals by the settlement (including medals used for setting the number of bets) is completed and a payout end command is transmitted.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted. An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption. The setting command is a command indicating the start or end of the setting change state and the setting value after the setting change. At the time of transition to the setting change state, a setting command indicating the start of the setting change state is transmitted, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. . The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of setting confirmation is transmitted when entering the setting confirmation state, and the setting confirmation end is indicated when the setting confirmation state ends. A confirmation command is sent.

  The door command is a command indicating the detection state of the door opening detection switch 25, that is, ON (open state) / OFF (closed state), and the command queue is empty when a predetermined condition is satisfied (when normal command transmission processing is executed). Sent).

  Of these commands, commands other than the door command are generated in the main process, temporarily stored in the command queue provided in the RAM 41c, and then the normal time command transmission process of the timer interrupt process (main), the command transmission at the time of power interruption Sent in processing. On the other hand, the door command is generated when no command is stored in the command queue in the normal command transmission process, temporarily stored in the command queue provided in the RAM 41c, and transmitted in the normal command transmission process. The

  Next, the control of the effect which the sub control part 91 performs based on the command which the main control part 41 transmits with respect to the sub control part 91 is demonstrated. When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices. In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED 55, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  Whether the detection state of the door opening detection switch 25 has changed from OFF (closed state) to ON (open state) based on the detection state of the door opening detection switch 25 specified from the door command. If it is determined whether or not it has changed from OFF (closed state) to ON (open state), a door opening notification for notifying that the front door 1b is being opened is executed.

  FIG. 5 is an address map of the memory area used by the main control unit 41. As shown in FIG. 5, the memory area used by the main control unit 41 includes a memory area (0000H to 7FFFH) allocated to the ROM 41b and a memory area (8000H to FFFFH) allocated to the RAM 41c.

  The memory area of the ROM 41b includes a program / data area (0000H to 26FFH) in which programs and fixed data are stored, a ROM comment area (2700H to 277FH) in which arbitrary data such as a title and version of the program can be set, and a later description. Parameters for setting the hardware table of the vector table area (2780H to 27A7H) in which the upper address of the subroutine of the CALLV instruction to be executed and the start address of the timer interrupt process (main) are set, and the internal function of the main control unit 41 HW parameter area (27A8H to 27FFH) in which is set, and an unused area (2800H to 7FFFH) where access is prohibited.

  The memory area of the RAM 41c includes an available area (8000H to 81FFH) that can be used as a work, and an internal function register area (9000H to 9000H) that stores a group of registers for controlling each function installed in the main control unit 41. 9080H) and unused areas (8200H to 8FFFH, 9081H to FFFFH) where access is prohibited.

  The parameters set in the HW parameter area in the ROM 41b include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) and the final address (HRAMEND) of the RAM area for which access is prohibited.

  FIG. 6 is an address map of the program / data area in the ROM 41b of the main control unit 41 and the usable area in the RAM 41c.

  As shown in FIG. 6A, the program / data area in the ROM 41b includes a game program area in which a game program related to the progress of the game is stored, a game data area in which game data used by the game program is stored, It includes a use area 1, a non-game program area in which a non-game program not related to the progress of the game is stored, a non-game data area in which non-game data used by the non-game program is stored, and an unused area 2. .

  The progress of the game is to advance a series of processes constituting the game. In the case of a slot machine, the stage where the game can be started by setting the number of bets is started and the reel is rotated. A step of stopping the reel, a step of deriving a display result, and a step of giving a value such as a medal according to the display result.

  The game program area is assigned to 0000H to 097EH, the game data area is assigned to 097FH to 12FFH, the non-game program area is assigned to 1380H to 1D02H, and the non-game data area is assigned to 1D03H to 267DH. An area (1357H to 137FH) between the game data area and the non-game program area is an unused area 1, and an area (267EH to 26FFH) after the non-game data area in the program / data area in the ROM 41b. The unused area 2 is designated as 0. In the unused areas 1 and 2, 0 is stored in all areas.

  As described above, the game program area related to the progress of the game and the non-game program not related to the progress of the game are separately allocated, and the game program area and the non-program area are rearward in the storage area of the ROM 41b. Since the unused area 1 of at least 16 bytes or more is allocated to the area before the allocated non-program area, a game program area related to the progress of the game, a non-game program not related to the progress of the game, Can be easily identified according to the difference in storage area.

  The game program area and the game data area, the non-game program area and the non-game data area are allocated to continuous areas, respectively, while the game program area and the game data area related to the progress of the game are not related to the progress of the game. Since the game program and the non-game data area are allocated to areas that are not continuous across the unused area 1 of at least 16 bytes or more, the game program area and game data area related to the progress of the game, and the progress of the game Non-game programs and non-game data areas that are not involved can be easily specified according to the difference in storage areas.

  In the above description, before and after the storage area is a magnitude relationship between the address values assigned to the storage area. The smaller address is the front and the larger address is the rear. For this reason, the storage area allocated behind the one storage area corresponds to the storage area having an address value larger than that of the one storage area, and the storage area allocated ahead of the one storage area. This corresponds to a storage area having an address value smaller than that of one storage area.

  Also, a configuration may be adopted in which a game program is allocated behind the non-game program area, and an unused area is allocated before the game program allocated behind the non-game program area. A game program area related to the progress of the game and a non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

  Further, the game program area and the non-game program area may be assigned to areas adjacent to each other with the unused area 1 in between, and even in such a structure, a game program area related to the progress of the game, A non-game program that is not related to the progress of the game can be easily specified according to the difference in the storage area.

  In addition, in the unused areas 1 and 2 of the program / data area of the ROM 41b, since 0 values are stored in all areas, a game program area and game data area, a non-game program area and non-game data, The unused areas 1 and 2 can be easily distinguished from each other, and even when invalid data is stored in the unused areas 1 and 2, they can be easily found.

  It should be noted that 1 may be stored in all of the unused areas 1 and 2 of the program / data area of the ROM 41b. Even in such a configuration, the game program area, the game data area, and the non-game The program area and non-game data can be easily distinguished from the unused areas 1 and 2 and can be easily detected even when invalid data is stored in the unused areas 1 and 2. .

  The game program area and the non-game program area both start from an address (0H) having the same lower 4 digits when the address is expressed in binary, and the program / data area of the ROM 41b. Among them, the game program area related to the progress of the game and the non-game program area not related to the progress of the game can be easily distinguished from other areas.

  In addition, both the game program area and the non-game program area not only start from an address having the same low-order 4 digit value when the address is expressed in binary, but also the low-order 1 digit value when expressed in hexadecimal. Starts from the same 0 address (0H), so that not only when the address is expressed in binary, but also when it is expressed in hexadecimal, the game program area and the non-game program area are easily distinguished from other areas. can do.

  It should be noted that both the game program area and the non-game program area start from an address having the same value in the lower N (N is a natural number of 1 or more) regardless of whether the address is expressed in binary or hexadecimal. With this configuration, the game program area and the non-game program area can be easily distinguished from other areas. For example, the value of the lower N (N is a natural number of 1 or more) digits is the same 1 The same effect can be obtained with a configuration starting from the address.

  As shown in FIG. 6B, the usable area of the RAM 41c includes a game RAM area used as a work by the game program, an unused area 3, a non-game RAM area used as a work by the non-game program, and an unused area. 4 and a stack area. In this embodiment, the game program and the non-game program share one stack area. However, the game stack area where the game program saves data and the non-game stack area where the non-game program saves data. These may be provided separately.

  The game RAM area is allocated to 8000H to 805BH, the non-game RAM area is allocated to 8070H to 814CH, and the stack area is allocated to 8170H to 81FFH. In addition, the area between the game RAM area and the non-game RAM area (805CH to 806FH) and the area between the non-game RAM area and the stack area (814DH to 816FH) are unused areas 3 and 4, respectively. In areas 3 and 4, 0 is stored in all areas. Of the stack areas, the stack pointers (SP) to 81FFH are used stack areas, and the remaining areas 816FH to SP are unused stack areas. As described above, the game RAM area used as a work by the game program and the non-game RAM area used as a work by the non-game program are allocated to non-continuous areas across the unused area 3 of at least 16 bytes or more.

  As described above, the game RAM area and the non-game RAM area are allocated to non-continuous areas across the unused area 3 of at least 16 bytes or more, so that the game RAM area used by the game program related to the progress of the game The non-game RAM area used by the non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

  Hereinafter, the game program area, the game data area, and the game RAM area may be collectively referred to as a game area, and the non-game program area, the non-game data area, and the non-game RAM area may be collectively referred to as a non-game area. . Further, the unused area 1 and the unused area 2, the unused area 3 and the unused area 4 may be collectively referred to as an unused area.

  Based on the parameters set in the HW parameter area, the main control unit 41 is an area (game program area, game) from the top address (0000H) to the address (267DH) set in HPRGEND among the program / data areas in the ROM 41b. Data area, unused area 1, non-game program area, non-game data area) are collectively set to permit, and an area between addresses (267EH) and 26FFH after the address (267DH) set in HPRGEND Access to (unused area 2) is prohibited. Further, based on the parameters set in the HW parameter area, the area from the top address (8000H) to the address (814DH) set in HRAMSTAT (game RAM area, unused area 3) among the usable areas of the RAM 41c. , Non-game RAM area), access to the area (stack area) from address (8160H) to 81FFH after the address (816FH) set in HRAMEND is set to permit, and address (814DH) set in HRAMSTAT To the area (unused area 4) between the addresses (816FH) set in HRAMEND to HRAMEND. Note that access to an area of the ROM 41b other than the program / data area and access to an area of the RAM 41c other than the usable area are uniformly prohibited.

  When the main control unit 41 accesses the unused area 2 between the address (267FH) and 26FFH after the address (267EH) set in HPRGEND in the program / data area of the ROM 41b, When an area other than the program / data area is accessed, the unused area 4 between the address (814DH) set in HRAMSTAT and the address (816FH) set in HRAMEND in the usable area of the RAM 41c. When an access to an area other than the usable area in the RAM 41c is made, it is determined that the access is illegal and an illegal access reset is generated. When an illegal access reset occurs, the state is controlled to a special error state to be described later, the progress of the game is disabled, the state is changed to a setting change state, and is not canceled until a new set value is set.

  As described above, when the main control unit 41 accesses the prohibited area in the program / data area of the ROM 41b based on the parameters set in the HW parameter area, When there is an access to an area for which access is not permitted, when there is an access to an area other than the program / data area in the ROM 41b, there is an access to an area other than the usable area in the RAM 41c. Sometimes, that is, when an access is made to a memory area that is not accessed in normal operation, an illegal access reset is generated to disable the progress of the game. Unauthorized programs are stored in unrelated areas, unused areas of the RAM 41c, etc. Even if it is possible to prevent the illegal program from being executed.

  In particular, in the present embodiment, a game program area and a non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and before the non-game program area behind the game program area. An unused area 1 is assigned to the area, and a group including an area from the start address of the game program area to the final address of the non-game program in the program / data area based on the parameters set in the HW parameter area. While the access to the area (the area from the game program area to the non-game data area) is collectively set to be permitted, the other areas, that is, the program / data area of the game program, game data, non-game program, Non-game data is not stored Because it is forbidden access to the area later than trick data, it is possible to prevent conducted unintended control by malware or illegal data.

  In addition, a game area is allocated behind the non-game program area in the program / data area permitted to be accessed by the program in the ROM 41b, and an unused area in the area before the game program area behind the non-game program area Are allocated to a group of areas including the area from the start address of the non-game program area to the final address of the game program based on the parameters set in the HW parameter area. Thus, while the permission is set, even if access to other areas is prohibited, it is possible to prevent unintended control by an unauthorized program or unauthorized data.

  In this embodiment, based on the parameters set in the HW parameter area, a group of areas (game program) including areas from the start address of the game program area to the final address of the non-game program in the program / data area. The access from the area to the non-game data area) is collectively set to be permitted, but a game program area and a non-game program area are allocated to the program / data area. In addition, the unused area 1 is assigned to the area before the rear non-game program area, and a group of areas including the game program area (area from the game program area to the game data area) of the program / data area, non- A group of areas containing game programs (non-game program areas To the non-game data area) may be set to be permitted, and access to other areas may be prohibited. Even in such a structure, the game program in the program / data area Since access to an area in which no non-game program is stored is prohibited, it is possible to prevent unintended control by an unauthorized program or unauthorized data. In addition, a game area is allocated behind the non-game program area in the program / data area permitted to be accessed by the program in the ROM 41b, and an unused area in the area before the game program area behind the non-game program area Of the program / data area including the game program area (the area from the game program area to the game data area), and the area including the non-game program (from the non-game program area to the non-game area). (Access to the data area) may be set to permit, and access to other areas may be prohibited. Even in such a configuration, a game program or non-game in the program / data area Access to an area where no program is stored Because There is inhibited, it is possible to prevent conducted unintended control by malware or illegal data.

  In the above description, the area where access is permitted is set in the program / data area. However, by setting the area where access is prohibited in the program / data area, the area where access is indirectly permitted is set. It is good also as a structure to be performed.

  Based on the parameters set in the HW parameter area, the main control unit 41 sets the area (game) from the address (0000H) set in IATSTAT1 to the address (097EH) set in IATEND1 in the program / data area of the ROM 41b. Program area), an area (non-game program area) from the address (1380H) set in IATSTAT2 to the address (1D02H) set in IATEND2 is set as a designated area where the IAT circuit 506a permits the program running.

  The IAT circuit 506a is set to IATEND2 from the area (game program area) from the address (0000H) set in IATSTAT1 to the address (097EH) set in IATEND1, and from the address (1380H) set in IATSTAT2 Areas up to the address (1D02H) (non-game program area), that is, areas other than the designated area permitting program running (game data area, non-game data area, unused area 1, 2 in the program / data area of the ROM 41b) When a user program is executed in an area other than the program / data area of the ROM 41b, an IAT generation signal is output. When the IAT generation signal is output, the CPU 41a is controlled to a special error state, which will be described later, and the progress of the game is disabled, and the CPU 41a shifts to the setting change state until a new setting value is set. It is not released.

  As described above, the main control unit 41 executes the user program when the user program is executed in an area other than the designated area where the program travel is permitted based on the parameters set in the HW parameter area, that is, in a normal operation. When the user program is executed in an area that does not occur, the IAT circuit 506a outputs an IAT generation signal to disable the progress of the game, so the unused area of the ROM 41b and the area not related to the operation, Even when an unauthorized program is stored in an unused area of the RAM 41c, the unauthorized program can be prevented from being executed.

  In particular, in the present embodiment, a game program area and a non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and before the non-game program area behind the game program area. The unused area 1 is assigned to the area, and the IAT circuit 506a permits the program running for each of the game program area and the non-game program area in the program / data area based on the parameters set in the HW parameter area. While it is set as a designated area, program running in other areas, that is, areas that do not store gaming programs or non-gaming programs in the program / data area is prohibited. Control line It can be prevented been.

  In addition, a game area is allocated behind the non-game program area in the program / data area permitted to be accessed by the program in the ROM 41b, and an unused area in the area before the game program area behind the non-game program area And the IAT circuit 506a sets each of the game program area and the non-game program area of the program / data area as a designated area that permits program running based on the parameters set in the HW parameter area. Thus, even if the program running in other areas is prohibited, it is possible to prevent unintended control due to unauthorized programs and unauthorized data.

  In this embodiment, based on the parameters set in the HW parameter area, the IAT circuit 506a is set as a designated area in which program running is permitted for each of the game program area and the non-game program area in the program / data area. The game program area and the non-game program area are allocated to the program / data area, and the unused area 1 is allocated to the area before the non-game program area behind the game program area. Based on the parameters set in the HW parameter area, a set of areas including the area from the start address of the game program area to the final address of the non-game program in the program / data area (from the game program area to the non-game data area) I) The T circuit 506a may be set as a designated area for permitting program travel in a lump and the program travel in other areas may be prohibited. Even in such a configuration, a game in the program / data area may be used. Since the program running in the area where no program or non-game program is stored is prohibited, it is possible to prevent unintended control by an unauthorized program or unauthorized data. In addition, a game area is allocated behind the non-game program area in the program / data area permitted to be accessed by the program in the ROM 41b, and an unused area in the area before the game program area behind the non-game program area Is assigned, and based on the parameters set in the HW parameter area, a group of areas (from the game program area) including the area from the start address of the non-game program area to the final address of the game program in the program / data area. Even if the IAT circuit 506a is collectively set as a designated area for permitting program running and the program running in other areas is prohibited, the area up to the non-game data area) Unintended control It can be prevented been.

  In the above description, the program / data area is configured to set the area that permits the program travel. However, the program / data area allows the program travel to be indirectly permitted by setting the area that prohibits the program travel. A configuration may be adopted in which an area is set.

  The program executed by the main control unit 41 includes a main routine that manages the progress of the entire program, and a subroutine that is called during execution of another program.

  In addition, a CALL instruction, an RST instruction, and a jump instruction are included as instructions for causing the main control unit 41 to execute a program stored in the program / data area.

  The CALL instruction is an instruction for calling and executing a subroutine stored at an address designated in the main routine or the subroutine. When calling the subroutine by the CALL instruction, the main control unit 41 stores the call source address in the stack area, and calls and executes the subroutine stored at the designated address. After the subroutine is completed, the caller address stored in the stack area, that is, the caller main routine or subroutine that executed the CALL instruction is returned to.

  The CALL instruction includes a normal CALL instruction and a CALLV instruction which is a special CALL instruction. The normal CALL instruction is an instruction that specifies a high-order address and a low-order address to specify both the high-order address and the low-order address and calls a subroutine while the CALLV instruction specifies only the low-order address. As a result, the subroutine is called by specifying the address by the upper address preset in the vector table area of the ROM 41b and the designated lower address, and the subroutine is called with a smaller amount of data than the normal CALL instruction. It becomes possible.

  The RST instruction is an instruction to call and execute a subroutine stored at a specific address corresponding to a specified value by specifying a value corresponding to a plurality of predetermined specific addresses. Subroutines can be called with a smaller amount of data than instructions and CALLV instructions. When calling the subroutine by the RST instruction, the main control unit 41 stores the caller's address in the stack area, and calls and executes the subroutine stored at the specific address corresponding to the designated value. After the subroutine is finished, the caller address stored in the stack area, that is, the caller main routine or subroutine that executed the RST instruction is returned to.

  The jump instruction is an instruction to move to a program stored at an address specified in the main routine or subroutine. The main control unit 41 moves to the program stored at the address specified by the jump instruction and executes the destination program. In this case, unlike the CALL instruction or the RST instruction, even if the program after the movement ends, the program does not return to the movement source program.

  The main control unit 41 includes an LD command as a command for reading data stored in the program / data area. The LD instruction is an instruction for reading data stored at a specified address in a main routine or subroutine into a specified register. The main control unit 41 reads the data stored at the address specified by the LD instruction, and stores the read data in the register specified by the LD instruction.

  Among the game programs stored in the ROM 41b, subroutines that are particularly frequently used are stored in an area of the game program area of the ROM 41b where the start address is a specific value (for example, 00H). On the other hand, a specific value is set in the vector table area of the ROM 41b as an upper address of a subroutine called by the CALLV instruction. The main control unit 41 specifies only the lower address using the CALLV instruction when calling a subroutine in which the upper address of the head address has a specific value, thereby specifying the specific value set in the vector table area as the upper address. The lower address specified as the lower address is specified, and the subroutine stored in the address including the upper and lower addresses is called and executed. For this reason, an upper address that constitutes a part of an address used when calling a subroutine that is used frequently in the game program is set in the vector table in advance as a specific value, and is based on the specific value set in the vector table. Since the address is specified, it is possible to call a subroutine with a smaller amount of data compared to a normal CALL instruction that calls a program by specifying both an upper address and a lower address, and when calling these subroutines It is possible to reduce the waste of a program for specifying an address.

  Of the non-game programs stored in the ROM 41b, subroutines that are used frequently are stored in the non-game program area of the ROM 41b in the area where the start address is a specific value, and the CALLV instruction When a specific value is set as an upper address of a subroutine to be called at the time, and the main control unit 41 calls a subroutine in which the upper address of the top address is a specific value, only the lower address is specified by using the CALLV instruction. Even if it is configured to call and execute, subroutines can be called with a smaller amount of data compared to a normal CALL instruction that calls a program by specifying both upper and lower addresses. When calling It is possible to reduce the waste of program for specifying the address.

  In addition, the upper address used when calling with the CALLV instruction may be set in a specific register of the main control unit 41 instead of the vector table area.

  In addition to the CALLV instruction, a part of the address is specified by using a value stored in the vector table area, a value set in a specific register, etc. If a special CALL instruction that enables the storage address to be specified is used, it is possible to reduce the waste of a program for designating an address when calling a subroutine. In addition, identification values having a data amount smaller than the addresses are assigned to the plurality of areas constituting the vector table area, the storage addresses of the subroutines are set in the plurality of areas, and the identification values are designated, thereby identifying the areas. Even in a configuration that uses a special CALL instruction that makes it possible to specify a storage address of a subroutine stored in an area corresponding to a value, it is possible to reduce the waste of a program for designating an address when the subroutine is called. .

  In addition, among the game data stored in the ROM 41b, game data that is frequently used is stored in the game data area of the ROM 41b in an area where the head address is a specific value, and a special LD is stored in the vector table area of the ROM 41b. By setting a specific value as the upper address of the data to be read by the instruction, and when the main control unit 41 calls game data in which the upper address of the top address becomes the specific value, only the lower address is specified by using a special LD instruction. Even when it is configured to read out these game data, it becomes possible to call game data with a smaller amount of data compared to a normal LD command that reads out data by specifying both the upper address and the lower address. When wasting game data, the program for specifying the address is wasted It can be reduced.

  In addition, among the non-game data stored in the ROM 41b, non-game data that is frequently used is stored in the non-game data area of the ROM 41b in the area where the head address is a specific value, and in the vector table area of the ROM 41b, When a specific value is set as an upper address of data read by a special LD instruction and the main control unit 41 calls non-game data whose upper address of the head address is a specific value, only the lower address is used by using a special LD instruction. Even if it is configured to read these non-game data by designating, the non-game data is called with a smaller amount of data compared to a normal LD instruction that designates both the upper address and the lower address and reads data. It is possible to specify the address when reading these non-game data. It is possible to reduce the waste of lamb.

  Even in these cases, the upper address used when calling with a special LD instruction may be set in a specific register of the main control unit 41 instead of the vector table area.

  Also, a part of the address is specified using the value stored in the vector table area, the value set in a specific register, etc., and the data storage address can be specified by specifying the remaining part of the address If the configuration uses a special LD instruction, the waste of a program for designating an address when reading data can be reduced. In addition, identification values with a data amount smaller than the addresses are assigned to the plurality of areas constituting the vector table area, the data storage addresses are set in the plurality of areas, and the identification values are designated to identify the areas. Even in a configuration using a special LD instruction that can specify the storage address of data stored in an area corresponding to a value, it is possible to reduce the waste of a program for specifying an address when reading data .

  Further, the main control unit 41 is activated by the occurrence of a system reset by inputting a system reset signal, a WDT reset by the WDT 506b, or the aforementioned illegal access reset. At this time, the value set in the vector table area Is a value indicating an address area set in 0000H to HPRGEND, that is, an area where a program or the like is actually stored in the program area, or FFFFH (a value set in an unused vector table area) If the value set in the vector table area is not a value indicating the address area set in 0000H to HPRGEND and is not FFFFH, it is not activated.

  As described above, the main control unit 41 indicates that the value set in the vector table area, that is, the upper address of the subroutine of the CALLV instruction described later and the start address of the timer interrupt process (main) is outside the area where the program is set. By not starting when it is a value, it is possible to prevent in advance an unintended process from being executed due to the occurrence of an interrupt or the like.

  FIG. 7 is an address map of the game program area in the program / data area of the ROM 41b of the main control unit 41.

  As shown in FIG. 7, the game program area of the ROM 41b is an area having addresses from 0000H to 097EH, and an area from 0000H to 003FH in this area (hereinafter also referred to as a specific address area) is an address. Addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, and 0038H) each having a specific value (8H or 0H) are assigned as specific addresses.

  In the game program area, for example, an initial setting process, an external signal off time waiting process, a maximum inserted medal number setting process, an output port 2 output process, a set value display data acquisition process, an addition process, as a game program related to the progress of the game Subroutines such as all reel stop LED off processing, interrupt one time waiting processing, interrupt BC time waiting processing, hopper stop processing, port output processing, gaming state determination processing, gaming counter transmission processing, command storage processing, etc. are stored. Yes.

  The initial setting process is a process for returning the control state of the main control unit 41 to a state in which a game can be progressed when returning from a power interruption, and the external signal off time waiting process starts from the ON state when an external output signal is output. This is a process of waiting until the time until switching to the OFF state elapses, and the maximum inserted medal number setting process is a process for setting the maximum inserted number of medals used in the game (three in this embodiment) and outputting The port 2 output process is a process of outputting a signal indicating the excitation state of the flow path switching solenoid 30 from the output port according to the progress of the game, and the set value display data acquisition process is performed on the set value display 24. Is a process for acquiring display data for displaying the address, and the addition process is a process for adding a predetermined value to a specified parameter and acquiring address data based on the value after the addition. The all-reel stop LED off process is a process for setting the port output so that the left middle right stop valid LEDs 22L, 22C, and 22R are turned off, and the interrupt once wait process is performed once. The process of waiting for interrupt BC times is a process of waiting until a specified number of interrupt processes are performed, and the hopper stop process is performed so that the hopper motor 34b is turned off. The port output process is a process of outputting a signal based on the port output setting performed in each process, and the gaming state determination process acquires the gaming state and determines the gaming state. Is a process for setting the flag shown in the RAM 41c, the game counter transmission process is a process for setting the value of the game counter as a command, and the command storage process is a command storage process. A process of storing the command in Dokyu.

  Among the game programs stored in the ROM 41b, some of the above-mentioned particularly frequently used subroutines are stored in an area starting from the specific address in the game program area of the ROM 41b. In this embodiment, a plurality of external signal off time waiting processing, output port 2 output processing, addition processing, interrupt one time waiting processing, interrupt BC time waiting processing, port output processing, and game state determination processing are included in the game program. The specific address is stored in the ROM 41b with the first specific address as the head.

  Specifically, the external signal off time waiting process starts with the specific address 0008H, the output port 2 output process starts with the specific address 0010H, and the addition process starts with the specific address 0018H and waits for one interrupt. The process starts with the specific address 0020H, the interrupt BC wait process starts with the specific address 0028H, the port output process starts with the specific address 0030H, and the gaming state determination process starts with the specific address 0038H. Stored in a specific address area.

  In the specific address area, the area from one specific address to the next specific address is 8 bytes, and when a subroutine exceeding 8 bytes is stored starting from the specific address, the subroutine includes a plurality of areas. It is divided and stored. In the present embodiment, the port output processing of the subroutine stored at the specific address is configured with a data amount exceeding 8 bytes, and the first 8 bytes of the subroutine starts with the specific address (0030H) and continues to the next. While being stored in the area (0030H to 0037H) before the specific address (0038H), the portion exceeding 8 bytes is stored in an area other than the specific address area (area starting with 0289H) in the game program area. The The first 8-byte part of the port output process includes a jump instruction to move to the specified address and execute the program stored at the address, and the first 8-byte part starting at the specific address As a result, the portion exceeding 8 bytes stored outside the specific address area is also integrally executed. The jump instruction is an instruction that is executed by calling a program stored at a designated address by designating a 2-byte address.

  In this way, the subroutine having a data amount exceeding 8 bytes is divided into the first 8 byte part and the subsequent subsequent part, and the first 8 byte part is stored in the area starting from the specific address, and the subsequent part is By storing a jump instruction to move to the subsequent stage in the first 8 bytes while storing it outside the specific address area, even if it is a subroutine with a data amount exceeding 8 bytes, it can be specified without going to multiple specific addresses It can be stored in the area starting from the address.

  In this embodiment, when a subroutine of less than 8 bytes is stored with a specific address as the head in the specific address area, there is another area after the subroutine stored in the specific address and before the next specific address. Are stored.

  Specifically, an area of 3 bytes from after the external signal off time waiting process (000DH) to before the next specific address (000FH), that is, between the external signal off time waiting process and the output port 2 output process. The area stores the maximum number of inserted medals set processing consisting of 3 bytes of data, and the subroutine is applied to all the areas from the specific address where the external signal off time waiting process is stored to the next specific address. Data is stored.

  The 3-byte area from the output port 2 output process (0015H) to the next specific address (0017H), that is, the area from the output port 2 output process to the addition process is 3 bytes of data. The set value display data acquisition process consisting of a quantity is stored, and the subroutine data is stored in the entire area from the specific address where the output process of the output port 2 is stored to the next specific address. ing.

  Also, in the 5-byte area from the addition process (001BH) to the next specific address (001FH), that is, the area between the addition process and the one-time interrupt process, the data amount is 5 bytes. The all-reel stop LED off process that is configured is stored, and the subroutine data is stored in the entire area from the specific address where the addition process is stored to the next specific address.

  In addition, the 3-byte area from after the interrupt BC wait process (002DH) to the next specific address (002FH), that is, the area between the interrupt BC wait process and the port output process is 3 Stores hopper stop processing consisting of byte data, and stores subroutine data in all areas from the specific address where the interrupt BC wait processing is stored to the next specific address. It has become.

  Further, in the 2-byte area from the game state determination process (003EH) to the end address (003FH) of the specific address area, that is, the area between the game state determination process and the command storage process, a 2-byte data amount The game counter transmission process is stored, and subroutine data is stored in all areas from the specific address where the game state determination process is stored to the end of the specific address area.

  In this way, in the subroutine stored in the area starting from the specific address and the remaining area before the next specific address, a subroutine having a data amount corresponding to the area or a part thereof is stored. Subroutine data is stored in the entire area from a specific address to the next specific address.

  In the present embodiment, the set value display data acquisition process is executed among the subroutine stored in the area starting from the specific address and the subroutine stored in the remaining area before the next specific address. In this case, the addition process is executed continuously, and the subroutine for the addition process is stored after the subroutine for the set value display data acquisition process in the game program area. The hopper stop process is a process in which the port process is continuously executed when the subroutine is executed, and the port process subroutine is stored after the hopper stop process subroutine in the game program area. The game counter transmission process is a process in which the command storage process is continuously executed when the subroutine is executed. In the game program area, the command storage process subroutine is stored after the game counter transmission process subroutine. Has been.

  Further, among all the subroutines stored in the area starting from the specific address and the subroutine stored in the remaining area before the next specific address, the all reel stop LED off process is performed when the process is executed. The port processing is executed continuously, and includes a jump instruction for designating an address where the port processing is stored and moving to that address.

  In the present embodiment, the subroutine stored in the area starting from the specific address and the remaining area up to the next specific address are the subroutine data composed of the data amount matching the remaining area. Is stored in the entire area from one specific address to the next specific address, but the subroutine stored in the area starting from the specific address and the next specific address are in front of each other. The data of a predetermined subroutine configured with a larger data amount than that of the remaining area may be stored in the remaining area until the predetermined area is stored in the remaining area. And a second part stored at a predetermined address in the game program area outside the specific address area. The first part is stored in the empty area as a data amount corresponding to the remaining area including a jump instruction to move to the predetermined address, and the second part is stored in a predetermined address outside the specific address area. Store the subroutine data in the entire area from the specific address to the next specific address using a part of the subroutine with a larger data amount than the area sandwiched between the subroutines stored in the area starting from the address. be able to.

  The main control unit 41 of this embodiment includes a 1-byte RST instruction that can call a subroutine by specifying a specific address. The operation code of the RST instruction is composed of 8 bits (1 byte), and the values of the first bit to 3 bits and the fifth bit to 8 bits are always set to “1”, while the third bit By designating each value of the fifth bit to a predetermined value, a specific address corresponding to a predetermined combination of “0” and “1” of 3 bits is specified, and the specified specific address is It is possible to call a subroutine stored as the head. Specifically, eight addresses of 0000H, 0008H, 0010H, 0018H, 0020H, 0028H, 0030H, and 0038H are assigned as specific addresses that can be specified by the RST instruction, and the third bit to the operation code of the RST instruction By specifying the fifth bit as “000”, the specific address 0000H is specified, by specifying “001”, the specific address 0008H is specified, and by specifying “010”, the specific address 0010H is specified, Specifying “011” specifies the specific address 0018H, specifying “100” specifies the specific address 0020H, specifying “101” specifies the specific address 0028H, and specifies “110”. As a result, the specific address 0030H is designated, and “11 A particular address 0038H is specified by specifying the ". Then, a subroutine starting from the designated specific address is called.

  The address in the ROM 41b has a 2-byte structure, whereas the parameter (operand) for designating a specific address by the RST instruction is 3 bits from the third bit to the fifth bit. That is, the RST instruction designates a specific address corresponding to a designated parameter among a plurality of specific addresses assigned at predetermined intervals by designating a parameter having a data amount smaller than the program address in the ROM 41b. Since the subroutine stored at the specified specific address can be called, the program capacity related to the calling of the program can be reduced. Also, the entire operation code of the RST instruction is composed of 1 byte and has a smaller data amount than the 2-byte program address. Since the program stored in the specific address can be called with a small amount of data, the program capacity related to the calling of the program can be reduced.

  As described above, the ROM 41b of the main control unit 41 of this embodiment is assigned a 2-byte address that can specify the storage area in which the program is stored, and the storage area with the address of 0000H to 003FH includes An 8-byte address (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H) in which the lower one digit of the address has a specific value (8H or 0H) is assigned as the specific address. In addition, the main control unit 41 designates a specific address by specifying a 2-byte address, jumping to a program at the designated address and executing the program, and 3-bit data shorter than the address. A 1-byte RST instruction that can call a program at a specific address and execute the program is provided. In such a configuration, when a data amount smaller than the area between specific addresses, that is, a program of less than 8 bytes is stored in the specific address, the subroutine stored in the area starting from the specific address and the next An empty area may occur in the area before the specific address, and the storage area of the ROM 41b is not used effectively.

  On the other hand, in the present embodiment, the first specific program, for example, the external signal off time waiting subroutine is stored in the area starting from one specific address, and the second is stored in the area starting from the next specific address. A specific program, for example, a subroutine for output port 2 output processing, and a region between the first specific program and before the next specific address, that is, the first specific program and the second specific program By storing a predetermined program or a part of a predetermined program equal to or less than the data amount corresponding to the empty area, for example, a subroutine for the maximum inserted medal number setting process that matches the data amount of the empty area The subroutine data is stored in the area from the specific address of the first to the next specific address. It can be used in the area effectively.

  Note that the predetermined program stored in the free area between the first specific program and the second specific program may be a program having a data amount smaller than the free area of the area, or in the free area. The programs having the same amount of data may be used, and in any configuration, the predetermined program is stored in the empty area between the first specific program and the second specific program, so that the area of the ROM 41b is reduced. It can be used effectively.

  In this embodiment, one type of subroutine is stored in an empty area between the first specific program and the second specific program. However, the first specific program and the second specific program are different from each other. A plurality of types of subroutines, that is, a plurality of programs may be stored in an empty space between them, and even in such a configuration, subroutines may be stored in an area from one specific address to the next specific address. Data is stored, and the area of the ROM 41b can be used effectively.

  In the present embodiment, a program (for example, after termination) that is executed after the predetermined program as a predetermined program in an empty area between the first specific program and the second specific program. By storing a subroutine for setting value display data acquisition processing to be executed continuously, the main control unit 41 continues to a predetermined program (subroutine for setting value display data acquisition processing) stored in the empty area. The second specific program (addition processing subroutine) is executed, and the second specific program is executed after the predetermined program ends only by calling the predetermined program stored in the empty area by the CALLV instruction. Therefore, in the program stored in the free space, the second specific program is executed by the RST instruction. There is no need to call the ram, it can be reduced program capacity for calling the second specific program.

  In this embodiment, a predetermined program composed of a data amount equal to or less than the free area is stored in the free area between the first specific program and the second specific program. A program including, in a free area between the specific program and the second specific program, a part of a program having a larger data amount than the free area as a predetermined program and a jump instruction for moving to an area other than the free area It is good also as a structure which is memorize | stored and memorize | stores the remaining part of the said program in the predetermined area | region designated with a jump instruction. By setting it as such a structure, it is between 1st specific program and 2nd specific program. Since a part of the program having a larger data amount than the free area can be stored in the free area, the storage area of the ROM 41b is in an empty state. It can be used effectively without. The area in which the remaining portion of the predetermined program is stored may be a specific address area or an area outside the specific address area.

  In this embodiment, as the specific program stored in the area starting from the specific address, a program having a larger data amount (for example, a subroutine for port output processing) than the area from the specific address to the area before the next specific address. And a program including a jump instruction to move to an area other than the area, and an area starting from a specific address by an RST instruction by storing the remaining part of the program in an area other than the area A part of the specific program stored in the program is executed, and the remaining part is executed by the jump instruction. Therefore, the program has a larger data amount than the area from the specific address to the next specific address. However, this program can be specified and executed by the RST instruction. It can be reduced program capacity of the call to a data amount larger program. The remaining part of the specific program is stored in an area outside the specific address area, but may be stored in an area inside the specific address area.

  The game program is a program related to the progress of the game as described above, and is a program for executing a process that hinders the progress of the game unless the process based on the program is executed.

  On the other hand, a non-game program is a program that is not related to the progress of the game as described above, and advances the game even when the game program is called to return to the game program without executing the processing based on the program. It is a program for executing processing that can be performed.

  As shown in FIG. 8, the game program includes a game dedicated program included only in the game program, and a common determination program and a common general-purpose program included in both the game program and the non-game program.

  The game dedicated program includes, for example, a BET process, an internal lottery process, a reel rotation process, a payout process, and an external output 1 process. The BET process is a process for starting a game by setting a bet number by inserting medals, etc. after the control of one game is completed, and operating a start switch 7 after a specified number of bets are set. The internal lottery process is a process of performing an internal lottery and setting a winning flag, etc. The reel rotation process starts the reel rotation, and the reels are operated by operating the stop switches 8L, 8C, 8R. The payout process determines whether or not a winning has occurred according to the stop position of the stopped reel, and pays out medals, sets a re-game, changes the game state, etc. The external output 1 process is a process for performing output control of the medal IN signal, the medal OUT signal, the RB signal, the BB signal, and the RT signal among the external output signals. Although not particularly illustrated, the game program includes processing related to the above-described AT (such as lottery related to AT and control related to navigation notification) and processing for transmitting the above-described internal winning command.

  The common determination program in the game program includes, for example, an input determination process and a payout determination process. The insertion determination process is a process for determining whether or not the medal is normally passed by the inserted medal sensor 31, and is a process executed in a state where a medal can be inserted for setting a bet amount. The payout determination process is a process for determining whether or not the medal is normally passed by the payout sensor 34c, and is a process executed in a state where the payout of the medal is permitted at the time of winning a small role or at the time of credit settlement. It is.

  The common general-purpose program in the game program is a process that is called and executed from a plurality of types of processes constituting the game program. For example, a counter update process, a port input process, a data conversion process, an LED display process, a data setting process, Includes command setting processing. The counter update process is a process for updating the designated counter value, the port input process is a process for acquiring the input state of the designated port, and the data conversion process is input using game data. Is a process for converting and outputting the data, the LED display process is a process for setting the specified value to be displayed on the LED, and the data setting process is a process for setting the specified data, The command setting process is a process for setting a specified command in the command queue. In addition, the initial setting process, the external signal off time waiting process, the maximum inserted medal number setting process, the output port 2 output process, the set value display data acquisition process, the addition process, the all reel stop LED off process, and the waiting for the interrupt once. Processing, interrupt BC wait processing, hopper stop processing, port output processing, gaming state determination processing, gaming counter transmission processing, and command storage processing are also included in the common general purpose program.

  As shown in FIG. 8, the non-game program includes a non-game dedicated program included only in the non-game program, and a common determination program and a common general-purpose program that are the same as the game program.

  Non-game dedicated programs include, for example, test signal output processing, foreign object detection processing, door monitoring processing, external output 2 processing, inserted medal error determination processing, payout medal error determination processing, random number abnormality confirmation processing, RAM abnormality confirmation processing, backup abnormality Includes confirmation processing, register initialization processing, setting value abnormality confirmation processing, and error processing. The test signal output process is a process for outputting a test signal generated in relation to the game result, and the foreign object detection process is a process for detecting a foreign object in the medal path by the insertion port sensor 26. The door monitoring process is a process for detecting the opening of the front door 1b, and the external output 2 process is a security signal (door open signal, setting change signal, input error signal, payout error signal) among external output signals. The inserted medal error determination process is a process for performing output control. Based on the detection status of the inserted medal sensor 31, the inserted medal backflow detection, the medal clogging detection in the medal selector 29, and the foreign object detection in the medal selector 29 are performed. The payout medal error determination process is based on the detection status of the payout sensor 34c, and the medal detection near the payout exit Is a process for detecting foreign matter in the vicinity of the payout exit, the random number abnormality confirmation process is a process for confirming whether the random number circuit is operating normally, and the RAM abnormality confirmation process and the backup abnormality confirmation process are performed by the RAM 41c. Is a process for confirming whether there is an abnormality in the data stored in the register, the register initialization process is a process for initializing various registers of the main control unit 41, and the set value abnormality confirmation process is a normal setting value. The error processing includes various abnormalities (medal insertion abnormality, foreign object detection in the medal selector 29, reel rotation abnormality, medal payout abnormality, payout exit, and the like. Processing for disabling the game when a foreign object detection in the vicinity, RAM abnormality, setting value abnormality, hopper tank 34a empty, overflow tank 35 full detection, etc. are detected It is.

  The common general-purpose program in the non-game program is a process that is called and executed from a plurality of types of processes constituting the non-game program.For example, the counter update process, the port input process, Includes data conversion processing, LED display processing, data setting processing, and command setting processing.

  In particular, the non-game program, when an abnormality is detected as described above, the release condition according to the type of abnormality (in the case of random number abnormality, RAM abnormality, backup abnormality, setting value abnormality, setting value resetting, In the case of other abnormalities, error processing is included that disables the progress of the game until a reset operation is established.

  Further, the non-game program includes processing for determining whether or not a predetermined detection status is based on detection statuses of detection means (the slot sensor 26, the full tank sensor 35a, and the door opening detection switch 25) that are not involved in the progress of the game. .

  In addition, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET processing, internal lottery processing, reel rotation processing, payout processing), and other control states The detection means (for example, the inserted medal sensor 31 and the payout sensor 34c) functioning as detection means not related to the progress of the game is based on the detection status in the control state not related to the progress of the game. (For example, a inserted medal detection process or a payout medal detection process for detecting an abnormality caused by detecting the insertion of a medal during reel rotation or the payout of a medal). Such a determination process corresponds to the common determination program because it is the same process as the process for determining whether or not the game program is in a predetermined detection status based on the detection status in the control state related to the progress of the game. .

  Among the processes included in the game program, the external output 1 process, the process of counting the number of medals inserted in the BET process, the process of switching the flow path switching solenoid 30, the process of counting the number of medals paid out in the payout process, the hopper If it is not directly related to the progress of the game, such as processing to detect that the tank 34a is empty, processing to update the software random number, processing related to AT, transmission processing of internal winning command, etc. The whole or part of the processing may be included in the non-game program. On the other hand, a configuration in which all or a part of these processes are included in the game program as long as it is indirectly related to the progress of the game, such as an activation process and a set value abnormality confirmation process among the processes included in the non-game program It may be.

  In the present embodiment, as shown in FIG. 9, the CPU 41a of the main control unit 41 calls a non-game program in the process based on the game program, executes the process based on the non-game program, and ends the process based on the non-game program. Return to the processing based on the game program.

  As shown in FIG. 10, when the CPU 41a calls a non-game program from the processing based on the game program, the CPU 41a uses arithmetic registers (A, F, BC, DE, All the values of the HL register (hereinafter referred to simply as a register for calculation) are saved in the stack area to protect the data used by the game program. Then, after all the processes based on the non-game program are completed, the value saved in the stack area is returned to the register, and thereafter, the process returns to the process based on the game program.

  In this embodiment, the register value used by the game program is protected by saving it in the stack area, but the game program uses it by changing the value of the front register and back register. The register value may be protected.

  Further, in this embodiment, when a non-game program is called from the processing based on the game program, the register value used by the game program is protected at the beginning of the non-game program, and at the end of the non-game program, It is configured to restore the value of the protected register, but the register value used by the game program immediately before calling the non-game program from the process based on the game program is protected, and all the processes based on the non-game program are performed. After completion, when the non-game program is called from the processing based on the game program, the configuration in which the value of the register protected at the first stage of returning to the game program is restored, the game program is After protecting the value of the register used and after all processing based on the non-game program is completed , A configuration in which the value of the register protected at the initial stage of returning to the game program is restored, the value of the register used by the game program immediately before calling the non-game program from the processing based on the game program, A configuration may be adopted in which the value of the protected register is restored at the end of the game program.

  As shown in FIG. 9, the CPU 41a, in principle, executes the process based on the game program with reference to the game data in the game data area and uses the game RAM area as a work when executing the process based on the game program. The contents of the game RAM area can be referred to and updated. Further, the CPU 41a, in principle, executes processing based on the non-game program by referring to the game data in the non-game data area, and uses the non-game RAM area as a work. It is possible to refer to and update the contents of the non-game RAM area.

  Further, the CPU 41a does not refer to the non-game data area and does not update the non-game RAM area when executing processing based on the game program, but can refer to the non-game RAM area. In executing the processing based on the non-game program, the game data area is not referred to and the game RAM area is not updated, but the game RAM area can be referred to.

  In addition, the process based on the game program can be referred to only a specific area necessary for the game program in the non-game RAM area (for example, an error flag setting area indicating abnormality detection). In the processing based on the game RAM area, only specific areas required for the non-game program (for example, an internal winning flag setting area, a gaming state setting area, an RT setting area, etc.) can be referred to. In addition, a specific area in the non-game RAM area where the process based on the game program can be referred to, and a specific area in the game RAM area where the process based on the non-game program can be referred to may be assigned to a continuous address area. However, a configuration in which part or all of the address areas are allocated to non-contiguous address areas may be used.

  However, the RAM abnormality check, the backup abnormality confirmation, the initialization of the RAM 41c, and the power interruption process to be described later are included in the non-game program, with the exception that these processes allow access to the entire area of the RAM 41c. Has been.

  As described above, in this embodiment, a game program area in which a game program related to the progress of a game is stored, a game data area in which game data referred to by the game program is readable and stored, and work data referred to by the game program Is a game RAM area that is stored so as to be readable and writable, a program that is called by the game program, a non-game program area that stores a non-game program that is not related to the progress of the game, and a non-game that is referenced by the non-game program Since a non-game data area in which data is stored in a readable manner and a non-game RAM area in which work data referred to by the non-game program are stored in a readable and writable manner are separately allocated, a game program, Game data and work program work data; Game program, the workpiece data of the non game data and non-game program, can be easily identified according to a difference in the storage area.

  In addition, by dividing the game program area and the game data area from the non-game program area and the non-game data area, the area occupied by the ROM 41b can be managed in a compact manner according to each function. It becomes easier to specify the corresponding data.

  Further, in this embodiment, when executing the game program, it is possible to refer to the non-game RAM area, and when executing the non-game program, it is possible to refer to the game RAM area. In executing the game program, the data used by the non-game program can be easily used, and in executing the non-game program, the data used by the game program can be used easily. On the other hand, it is impossible to update the non-game RAM area when executing the game program, and it is impossible to update the game RAM area when executing the non-game program. Does not affect the processing of the non-game program, and the non-game program does not affect the processing of the game program.

  Further, in this embodiment, the processing based on the game program can be referred to only a specific area required for the game program in the non-game RAM area (for example, an error flag setting area indicating abnormality detection). The processing based on the non-gaming program can be referred to only specific areas (for example, an internal winning flag setting area, a gaming state setting area, an RT setting area, etc.) necessary for the non-gaming program in the gaming RAM area. Therefore, since the data that can be referred to by the game program in the non-game RAM area and the data that can be referred to by the non-game program are limited to a specific area, the reference destination of the game program or the non-game program can be easily specified. be able to.

  Further, in this embodiment, since the non-game program includes an error process that disables the progress of the game until the cancellation condition is satisfied according to the type of the abnormality when the abnormality is detected, the process in the non-game program It is possible to prevent the game from proceeding as it is when an abnormality or the like is detected.

  In this embodiment, since the non-game program includes a common determination program having the same contents as the common determination program included in the game program (for example, the input determination process and the payout determination process), the game program and the non-game program are mutually connected. The same determination can be made without affecting the result.

  In the present embodiment, the non-game program is a process that is called and executed from a plurality of types of processes constituting the non-game program, and includes a common general-purpose program similar to the common general-purpose program included in the game program. Even if it is a common general-purpose program with the same processing content, it is provided with a game program and a non-game program, so whether the processing content is the same or a non-game program even if it is a common general-purpose program with the same processing content Can be easily identified.

  Further, in this embodiment, it is determined whether or not the non-game program is in a predetermined detection state based on the detection state of the detection means (the inlet sensor 26, the full tank sensor 35a, the door opening detection switch 25) that is not related to the progress of the game. Since the determination process is included, the determination as to whether or not the predetermined detection is performed by the detection means not related to the progress of the game is performed by the non-game program, so that the game program does not become complicated.

  In the present embodiment, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET processing, internal lottery processing, reel rotation processing, payout processing). In other control states, the detection means (for example, the inserted medal sensor 31 and the payout sensor 34c) functioning as detection means not related to the progress of the game is based on the detection state in the control state not related to the progress of the game. A process for determining whether or not a predetermined detection status is present (for example, a inserted medal detection process or a payout medal detection process for detecting an abnormality caused by detecting the insertion of a medal during reel rotation or the payout of a medal) Therefore, in the situation where the detection result of the detection means as described above is not used for the progress of the game, it is not determined whether the predetermined detection is performed by the detection means. By performed by programs, detection result of the detection means in terms of also using the detection results of the detecting means in a situation that is not used in the progress of the game, never game program becomes unnecessarily complex.

  Further, in this embodiment, when a game program calls a non-game program and executes the non-game program, all areas of the register are protected regardless of whether or not the game program is the register actually used. Therefore, when returning to the game program, it is possible to reliably return from the state at the time when the non-game program is called.

  Further, in this embodiment, when a non-game program is called from the processing based on the game program, the register value used by the game program is protected at the beginning of the non-game program, and at the end of the non-game program, Since the value of the protected register is restored, the capacity of the game program can be reduced.

  It should be noted that the register value used by the game program immediately before calling the non-game program from the process based on the game program is protected, and after all the processes based on the non-game program are completed, at the first stage of returning to the game program A configuration may be adopted in which the value of the protected register is restored. With this configuration, register protection processing is performed before the non-game program is called, and register restoration processing is performed after the non-game program is restored. Therefore, the data stored in the register by the non-game program does not affect the game program.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When the main control unit 41 is activated due to the occurrence of a reset, the main control unit 41 performs setting at the time of activation. In the startup setting, a status flag included in the main control unit 41 is initialized. The status flag is data that holds the state of the operation result and execution result of the instruction, and particularly includes an interrupt master permission flag for setting interrupt prohibition / permission. Since the initial value of the interrupt master permission flag is a value indicating prohibition of interrupt, the main control unit 41 is started in a state where interrupt is prohibited.

  After that, the main control unit 41 sets various functions with reference to the HW parameters, and then performs an initial setting process shown in the flowchart of FIG. 11 in accordance with the program stored in the program / data area. In the initial setting process, first, the interrupt is prohibited by setting the value of the interrupt master permission flag to a value indicating prohibition of interrupt (Sa1). As described above, the main control unit 41 is started in an interrupt-inhibited state, but in Sa1, the interrupt is again prohibited. Next, initialization data is set (Sa2), and each output port including the parallel output port 513 is initialized (Sa3). Next, the built-in register is set (Sa4).

  Next, it is determined whether or not the power supply voltage is normal (Sa5). If the power supply voltage is not normal, the determination is repeated until normal. If the power supply voltage is normal, the upper address of the interrupt vector is set (Sa6). Then, access to the RAM 41c is permitted (Sa7), and the stack pointer is initialized (Sa8).

  Next, the RAM parity (hereinafter referred to as RAM parity 1) of all the game RAM areas (including the unused area 3) of the RAM 41c and the RAM of all non-game RAM areas (including the unused area 4). The RAM parity (hereinafter referred to as RAM parity 3) of the parity (hereinafter referred to as RAM parity 2) and the stack area (unused stack area and used stack area) is calculated (Sa9). Then, it is determined whether or not the calculated RAM parities 1 to 3 are 0 (Sa10). As will be described later, if the power interruption processing (main) is normally performed at the time of the previous power shutdown, the RAM parities 1 to 3 should all be 0. If any one of them is not 0, the data stored in the RAM 41c is not normal. In this case, the process proceeds to step Sa14 to clear the destruction diagnosis data (Sa14). On the other hand, when the RAM parities 1 to 3 are all 0, the destructive diagnosis data 1 stored in the game RAM area, the destructive diagnosis data 2 stored in the non-game RAM area, and the stack area The stored destruction diagnosis data 3 is acquired (Sa11), it is determined whether or not the acquired destruction diagnosis data 1 to 3 are correct (Sa12), and the destruction diagnosis data 1 to 3 are cleared (Sa13). .

  Next, it is determined whether or not the setting key switch 37 is in an ON state (Sa14). When the setting key switch 37 is in the ON state, a timer interrupt is set (Sa19). Specifically, the register of the timer circuit 509 built in the main control unit 41 is set so that a timer interrupt is periodically executed every predetermined time. In this embodiment, a value corresponding to about 0.56 ms is set in a predetermined register (time constant register), so that a timer interrupt is periodically generated every about 0.56 ms. In the timer circuit 509, the register is set, so that the timer is initialized and starts counting from the initial value. When the timer interrupt setting in step Sa19 is completed, the process proceeds to a setting change process.

  On the other hand, when the setting key switch 37 is in the OFF state, it is determined whether or not the stored contents of the RAM 41c are destroyed (Sa15). In step Sa15, it is determined whether a RAM abnormality flag, which will be described later, is set, and whether the storage content of the RAM 41c is destroyed based on the determinations in Sa10 and Sa12. If the stored contents of the RAM 41c are not destroyed, a return command is transmitted to the sub-control unit 91 (Sa16). In the case where the stored contents of the RAM 41c are not destroyed, it is determined that the RAM abnormality flag is not set and the RAM parities 1 to 3 are all 0 in the step Sa10, and further in the step Sa12. This is a case in which it is determined that the destruction diagnosis data 1 to 3 are all correct.

  After the step of Sa16, all the registers are restored (Sa17), and the timer interrupt setting similar to the step of Sa19 is performed (Sa18). Then, the process proceeds to Sd24 in a timer interrupt process (main) described later. As a result, the process that was being executed before the power interruption is restored.

  If the stored contents of the RAM 41c are destroyed in step Sa15, the start address (0000H) of the RAM is set in the register (Sa20), and the address from the specified address to the last address (0FFFH) of the usable area is set. The area, that is, all the usable areas are initialized (Sa21).

  Next, a RAM abnormality flag indicating that the storage content of the RAM 41c is not normal is set in the RAM 41c (Sa22), and the process proceeds to error processing. In error processing, the progress of the game is disabled. Further, the error state that has been shifted after the RAM abnormality flag is set can be canceled by shifting to the setting change process by setting the setting key switch 37 to ON and turning on the power switch 39. On the other hand, when the power switch 39 is turned on without turning the setting key switch 37 on, the RAM abnormality flag remains set, and an error state occurs again.

  Next, the setting change process which the main control part 41 performs is demonstrated.

  As shown in FIG. 12, the main control unit 41 first sets a RAM start address (0000H) in a register (Sb1). Next, it is determined whether or not the stored contents of the RAM 41c are destroyed in the same manner as in the step Sa15 shown in FIG. 11 (Sb2). If the contents of the RAM are not destroyed, that is, if the contents of the RAM are not abnormal, the start address of the initialization target RAM at the start of setting change is set in the register (Sb3). That is, the address set in Sb1 is changed. If the contents of the RAM are destroyed, that is, if the contents of the RAM are abnormal, the process proceeds to step Sb4.

  Next, the area from the address designated in the step Sb1 or Sb3 to the last address of the usable area is initialized (Sb4). In step Sb1, the start address of the RAM is set. In this case, all the usable areas are initialized in step Sb4. On the other hand, since the start address of the initialization target RAM at the start of setting change is set in the step Sb3, in this case, in the step Sb4, areas other than the important work and the special work are initialized among the usable areas. Will be.

  Next, a setting command indicating the start of the setting change state is transmitted to the sub-control unit 91 (Sb5), and interruption is permitted (Sb6).

  Next, it is determined whether or not the reset / setting switch 38 has changed from OFF to ON (Sb7). When the reset / setting switch 38 changes from OFF to ON, the set value of the register is updated (in the case of 1 to 5, 1 is added, and in the case of 6, it is updated to 1) (Sb8). If the reset / setting switch 38 has not changed, it is determined whether or not the start switch 7 has changed from OFF to ON (Sb9). If the start switch 7 has not changed, the process returns to step Sb7. On the other hand, when the start switch 7 changes from OFF to ON, it is determined whether or not the setting key switch 37 is in the OFF state (Sb10). If the setting key switch 37 is not in the OFF state, the determination is repeated until the setting key switch 37 is in the OFF state. If the setting key switch 37 is OFF, the setting value data set in the register is stored in the RAM 41c (Sb11).

  Next, a setting command indicating the end of the setting change state is transmitted to the sub-control unit 91 (Sb12). Then, the initial address of the initialization target RAM at the end of the setting change is set in the register (Sb13), and the process proceeds to the main process.

  Next, main processing executed by the main control unit 41 will be described. The main process is repeatedly executed for each unit of game. One period of the main process corresponds to one unit of the game.

  As shown in FIG. 13, the main control unit 41 first prohibits an interrupt (Sc1). Next, the final address of the initialization target RAM is set (Sc2).

  Next, the RAM area indicated by the designated address is cleared (Sc3). At this time, if the main process is started after the setting change process, the initial address of the initialization target RAM at the end of the setting change is set. In the step Sc2, the final address of the initialization target RAM at the end of the setting change is set. Since it is set, areas other than the important work and the special work among the usable areas are initialized. Also, at the end of a game that is not at the end of a specific gaming state, the start address of the initialization target RAM at the end of the game is set in the later-described Sc10 step, and at the Sc2 step, the initialization target RAM at the end of the game is set. Thus, the unused area and the unused stack area of the usable area are initialized. At the end of the specific gaming state and at the end of the game, the start address of the initialization target RAM at the end of the specific gaming state is set in the step of Sc11 described later, and in the step of Sc2, the specific address is set. Since the final address of the initialization target RAM at the end of the gaming state is set, the general area, the unused area, and the unused stack area among the available areas are initialized.

  After initialization of RAM in the step of Sc3, interruption is permitted (Sc4), and a game start waiting process is executed (Sc5). In the game start waiting process, the process waits in a state where a bet number can be set, and a process for starting a game is executed when a specified number of bets are set according to the game state and the start switch 7 is operated.

  Next, an internal lottery process is executed (Sc6). In the internal lottery process, whether or not to win the above-mentioned winning combination based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sc5 (that is, the display result is derived). The process of determining whether or not to allow) is performed.

  Next, a reel control process is executed (Sc7). In the reel control process, the process of rotating each reel 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step of Sd2, and the operation of the stop switch 8L, 8C, 8R by the player are detected. In response to this, processing for stopping the rotation of the corresponding reels 2L, 2C, 2R is executed.

  Next, a game end time setting process is executed (Sc8). In the game end setting process, when it is determined that the rotation of all the reels 2L, 2C, and 2R is stopped in the process of Sc7, a winning occurs according to the display result derived for each reel 2L, 2C, and 2R. The process which determines whether or not is executed. When it is determined that a winning has occurred, processing such as credit addition and medal payout is performed based on the number of payouts according to the winning. When a winning occurs, a process for setting a gaming state for the next game is executed after the medal payout is completed. Further, when no winning occurs, after the reels are stopped, processing for setting a gaming state for the next game is executed.

  When the setting process at the end of the game is completed, it is determined whether or not it is the end of the specific gaming state (Sc9). If it is not the end of the specific gaming state, the initial address of the initialization target RAM at the end of the game is determined. Set (Sc10) and return to the step of Sc1. If it is at the end of the specific gaming state, the start address of the initialization target RAM at the end of the specific gaming state is set (Sc11), and the process returns to the step of Sc1.

  Also, in the main process, a command storing process for generating a command according to the progress of the game and setting the command in the command queue is executed, and the set command is executed in the normal timer execution process (main) thereafter. It is transmitted to the sub-control unit 91 by command transmission processing.

  FIGS. 14 and 15 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the basic process (mainly the main process) at a constant interval (approximately 0.56 ms). is there. The timer interrupt process (main) is a process executed by an interrupt generated according to the count of the timer circuit 509. The address at which the program of the timer interrupt process (main) is stored is a vector table. It is set as a value corresponding to the timer interrupt. When a timer interrupt occurs, processing from that address is executed. Further, other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  As shown in FIG. 14, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sd1).

  Next, a power failure determination process is performed (Sd2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in step Sd2, it is determined whether or not the power interruption flag is set (Sd3). If the power interruption flag is not set, the process proceeds to Sd4, and detection data of various switches from the input port. The port input process to input is performed. On the other hand, if the power interruption flag is set, after executing the power interruption command transmission process for transmitting various commands set in the command queue to the sub-control unit 91 (Sd19), the power interruption process (main) Migrate to

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sd5). In step Sd5, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, the branch counter value is referenced to determine whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sd6). If it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, motor phase signal output processing for outputting the phase signal data of the reel motors 32C, 32C, 32R is executed (Sd7).

  Next, referring to the counter value for branching, it is determined whether or not it is 1, that is, timer interrupt 2 (Sd8). If it is not timer interrupt 2, that is, timer interrupt 1, the reel motor Reel start processing (Sd9) for controlling the step time interval when starting 32L, 32C, 32R, motor step processing (Sd10) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, motor phase signal standby processing (Sd11) for changing the phase signal to one-phase excitation after a lapse of a certain time is sequentially executed, and the process proceeds to step Sd24.

  If it is determined in step Sd8 that the timer interrupt is 2, LED dynamic display processing for dynamically lighting various indicators (Sd12), and control for outputting data such as lighting signals for various LEDs to the output port. Signal output processing (Sd13), time counter update processing for updating various time counters (Sd14), door open detection switch 25 detection status, door command transmission request for door command transmission request (Sd15), command queue After executing the normal command transmission process (Sd16) for transmitting the various commands set to “1” to the sub-control unit 91 and the external output signal update process (Sd17) for updating the external output signal, the process proceeds to step Sd24.

  If it is determined in step Sd6 that timer interrupt 3 or timer interrupt 4 is detected, it is further determined whether or not the branch counter value is 3, that is, timer interrupt 4 (Sd18). If it is not the timer interrupt 4, that is, the timer interrupt 3, the origin passing process (Sd19) for checking the origin passing (passing of the reel reference position) of the rotating reels 2L, 2C, 2R, After sequentially executing the switch input determination process (Sd20) for determining whether or not the detection state has changed, the process proceeds to step Sd24.

  If it is determined in step Sd18 that the timer interrupt is 4, stop switch processing (Sd21) for determining a stop position in accordance with detection of the stop switches 8L, 8C, and 8R, two phases when it is time to stop. A stop process (Sd22) for starting braking by excitation and a final stop process (Sd23) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then the process proceeds to step Sd24.

  In step Sd24, the registers saved in the stack area in Sd1 are restored, and the process returns to the state before the interrupt.

  As described above, in the present embodiment, the main control unit 41 starts in an interrupt-disabled state when a reset occurs, and then interrupts the program at the start of the initial setting process to be executed first. Prohibition is performed, and it is possible to prevent an unintended interrupt from occurring even when the main control unit 41 is activated in a state where the interrupt is not prohibited for some reason.

  In addition, the main control unit 41 is configured to permit the interrupt after setting the timer interrupt in the timer circuit 509 after the activation, and the interrupt is generated in a state where the timer interrupt does not operate normally. Can be prevented. In the timer circuit 509, the timer is initialized by setting the timer interrupt, and the timer starts counting from the initial value. After starting, the time until the first interrupt occurs Timer interrupts can be generated at regular time intervals without any deviation from the time until the second and subsequent interrupts are generated. In addition, the main control unit 41 is configured to update the setting of the timer circuit 509 to the initial value by a program in the initial setting process, and when the setting of the timer circuit 509 is rewritten for some reason at the time of activation. Even if it exists, it can prevent that the unintended interruption generate | occur | produces.

  Further, the main control unit 41 proceeds to the setting change process if the setting key switch 37 is in an ON state at the time of activation, and initializes the RAM 41c at the start of the setting change process. At this time, if the data in the RAM 41c is normal, the important work and the special work are held and the other areas are initialized so that the control state (setting value, gaming state, etc.) before the change is changed after the setting is changed. While some data can be retained, if the data in the RAM 41c is not normal, all the usable areas including the important work and the special work are initialized to ensure that the data in the RAM 41c is abnormal. Can be resolved.

  In addition, since the RAM abnormality flag is set when the RAM abnormality is determined, the main control unit 41 is turned off after the occurrence of the RAM abnormality error, and the RAM parity is 0 when the power is turned on again. Yes, even if it is determined that the destruction diagnosis data is normal, it is possible to determine whether the data in the RAM 41c is destroyed based on the RAM abnormality flag.

  Moreover, the main control part 41 performs the main process which processes in steps according to progress of a game for every game unit after completion | finish of a setting change process. In the main process, the RAM 41c is initialized for each game unit, and the RAM 41c is also initialized at the end of the setting change process. After the setting change process, the main process starts from the stage before the process of initializing the RAM 41c in the main process. The initialization of the RAM 41c after the setting change process is completed and the game unit It is possible to perform initialization of the RAM 41c for each process by common processing.

  Further, when the RAM 41c is initialized, the main control unit 41 prohibits interrupts until the initialization is completed, and the timer interrupt process (main) is performed during the initialization of the RAM 41c. Occurrence can prevent the initialized contents from being changed and the processing performed in the timer interrupt processing (main) from being performed normally.

  Further, the main control unit 41 updates the output state of the external output signal in the main process, and changes the output state of the external output signal in the subsequent timer interrupt process (main) based on the updated output state. In addition, when updating the output state of the external output signal, interrupts are prohibited until the update is completed, and timer interrupt processing (main) occurs before the output state of the external output signal is completed By doing so, it is possible to prevent an external output signal indicating unintended data from being output.

  The main control unit 41 of the present embodiment generates a command according to the progress of the game in the setting change process and the main process described above, stores the generated command in the command queue, and performs a normal time in the timer interrupt process (main). Each time a command transmission process is executed, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

  FIG. 16 is a flowchart showing the control contents of command storage processing executed when various commands generated by the main control unit 41 are stored in the command queue. The command transmitted by the main control unit 41 is composed of 2 bytes. The first byte represents MODE (command classification), and the second byte represents EXT (command content). Further, the form of the command shown in this embodiment is an example, and other data forms may be used. In this embodiment, the command is composed of a 2-byte signal, but these commands may be composed of a 1-byte signal or a 3-byte or more signal.

  In the command storing process, first, MODE and EXT composing a command to be transmitted are generated (Se1). Then, after the MODE and EXT of the generated command are stored in the area of the area number indicated by the storage pointer, that is, the empty area of the command queue (Se2), 1 is added to the area number indicated by the storage pointer (Se3). Since the area number is a numerical value in the range of 0 to 31, when the serial number indicated by the storage pointer is 31, 1 is added and updated to 0 when it becomes 32.

  Next, it is confirmed whether or not the untransmitted flag is set (Se4). If the untransmitted flag is not set, the untransmitted flag is set (Se5). Then, it is checked whether the area number indicated by the storage pointer matches the area number indicated by the transmission pointer, that is, whether all areas of the command queue are full due to unsent commands. If yes, wait until an unsent command stored in the command queue is sent and the area number indicated by the storage pointer does not match the area number indicated by the transmission pointer, and the area number indicated by the storage pointer When the area number indicated by the transmission pointer does not match, that is, when the command queue is empty, the command storage process is terminated (Se6).

  FIG. 17 shows the control of the normal time command transmission process executed in the timer interrupt 2 of the timer interrupt process (main) described above in order for the main control unit 41 to transmit the command stored in the command queue by the command storage process. It is a flowchart which shows the content.

  In the normal command transmission process, first, it is confirmed whether or not an untransmitted flag is set, that is, whether or not an untransmitted command is stored in the command queue (Sf1), and the untransmitted flag is not set. In this case, the detection state of the door opening detection switch 25 is acquired to generate MODE and EXT composing the door command, and the generated MODE and EXT are stored in the area of the area number indicated by the storage pointer, that is, the empty area of the command queue. Store (Sf2, Sf3).

  When it is determined that the unsent flag is set in the step Sf1, and after the MODE and EXT constituting the door command are stored in the command queue in the steps Sf2 and Sf3, the area indicated by the transmission pointer value of the command queue Are transmitted to the sub-control unit 91 (Sf4 to Sf7). Specifically, first, the MODE that constitutes the command stored in the area indicated by the transmission pointer value of the command queue is output (Sf4), and a strobe signal for notifying the sub-control unit 91 that the command has been output is output for a predetermined time. (In this embodiment, 10 μs) is output (Sf5). Then, EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sf6), and the strobe signal is output again for a predetermined time (Sf7).

  Next, 1 is added to the area number indicated by the transmission pointer (Sf8). Since the area number is a numerical value in the range of 0 to 31, when the area number indicated by the transmission pointer is 31, 1 is added and updated to 0 when it becomes 32. Thereafter, it is confirmed whether or not the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether or not the command to be transmitted is stored in the command queue (Sf9). That is, if the command to be transmitted is not stored in the command queue, the untransmitted flag is cleared and the normal time command transmission process is terminated (Sf10). On the other hand, if the area number indicated by the transmission pointer does not match the serial number indicated by the storage pointer, that is, if the command to be transmitted is stored in the command queue, the untransmitted flag is maintained and normal command transmission is performed. The process ends. By maintaining the unsent flag, unsent commands left in the command queue are transmitted in the next timer interrupt process (main).

  The main control unit 41 of this embodiment executes the command transmission process during power interruption before executing the power interruption process (main) when the power interruption flag is set in the above-described timer interruption process. In addition to the normal command transmission process, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

  FIG. 18 is a flowchart showing the control contents of the power interruption command transmission process executed before the main control unit 41 performs the power interruption process (main) in the timer interrupt process (main).

  In the command transmission process at power interruption, first, it is confirmed whether or not an untransmitted flag is set, that is, whether or not an untransmitted command is stored in the command queue (Sg1), and the untransmitted flag is set. If so, all commands stored in the command queue are transmitted to the sub-control unit 91 (Sg1 to Sg7).

  Specifically, first, a MODE composing the command stored in the area indicated by the transmission pointer value of the command queue is output (Sg2), and a strobe signal for notifying the sub-control unit 91 that the command has been output is output for a predetermined time. (In this embodiment, 10 μs) is output (Sg3). Then, EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sg4), and the strobe signal is output again for a predetermined time (Sg5). Thereafter, 1 is added to the area number indicated by the transmission pointer (Sg6). As in the case of adding the transmission pointer in the normal command transmission process, the area number is a numerical value in the range of 0 to 31, so when the area number indicated by the transmission pointer is 31, 1 is added to 32. Update to 0.

  Next, it is determined whether the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether the command to be transmitted is stored in the command queue (Sg7), and the area indicated by the transmission pointer If the number and the serial number indicated by the storage pointer do not match, that is, if the command to be transmitted is stored in the command queue, the area number indicated by the transmission pointer and the serial number indicated by the storage pointer are determined in step Sg7. The steps Sg2 to Sg7 are repeatedly executed until it is determined that they match, and all the commands stored in the command queue are transmitted to the sub-control unit 91.

  In step Sg7, if it is determined that the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, all commands stored in the command queue are transmitted to the sub-control unit 91. When no command remains in the command queue, the main control unit 41 clears the untransmitted flag (Sg8), ends the command transmission process at power interruption, and shifts to power interruption processing (main).

  As described above, in the normal time command transmission process, each time the normal time command transmission process is executed in the timer interrupt process (main), one command (a set of commands consisting of 2 bytes) is sent to the sub-control unit 91. On the other hand, in the command transmission process at power interruption, all commands stored in the command queue are sent to the sub-control unit 91 before the power interruption process (main) is performed in the timer interrupt process. To send.

  FIG. 19 shows the power interruption process (main) executed after the power interruption command transmission process when the main control unit 41 determines that the power interruption flag is set in the timer interruption process (main) described above. It is a flowchart which shows the control content. In the present embodiment, the power interruption process is included in the non-game program.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sg1).

  Next, the destruction diagnosis data 1 is set in the game RAM area, the destruction diagnosis data 2 is set in the non-game RAM area, and the destruction diagnosis data 3 is set in the stack area (Sg2). The data for destructive diagnosis are all 5A (H). Then, all output ports including the parallel output port 513 that outputs a command are initialized (Sg3). As a result, the output state of the output port corresponding to the last command output by the power interruption command transmission process is initialized. Next, the RAM parity adjustment data 1 is calculated and set in the game RAM area so that the exclusive OR of all areas of the game RAM area (including the unused area 3) becomes 0, and the non-game RAM area The RAM parity adjustment data 2 is calculated and set in the non-game RAM area so that the exclusive OR of all areas (including the unused area 4) becomes 0, and all the areas in the stack area (unused stacks) The RAM parity adjustment data 3 is calculated and set in the stack area so that the exclusive OR of the area and the used stack area is 0 (Sg4), and access to the RAM 41c is prohibited (Sg5). Thereafter, the voltage decreases, and the CPU 41a of the main control unit 41 stops and shifts to a standby state. Then, as the voltage decreases while in this standby state, the main control unit 41 is internally in an operation stop state and reliably stops operation in the event of a power interruption.

  When the power supply of AC100V is stopped by the above process, the power interruption process is executed, the destruction diagnosis data 1 to 3 and the RAM parity adjustment data 1 to 3 are stored in the backup RAM, and the RAM access is performed. It is disabled and the output port is cleared.

  As described above, in this embodiment, in the power interruption process executed when power interruption is detected, the RAM parity adjustment data for determining whether or not the data in the RAM 41c is normal is calculated. A process for calculating the RAM parity for determining whether or not the RAM 41c is normal, and a process for determining whether or not the data in the RAM 41c is normal based on the RAM parity when the power is turned on are divided into a game RAM area and a non-game RAM area. Therefore, it is possible to easily specify a data storage area necessary for designing these processes.

  In this embodiment, the adjustment data is set in the target area so that the calculation result of the target area in the power interruption process becomes a specific value (0 in this embodiment), and the target data is set in the start process. Whether or not the data in the RAM 41c is normal is determined based on whether or not the calculation result of the area to be a specific value. The calculation result of the area to be processed in the power interruption process and the area to be processed in the start-up process It may be configured to determine whether or not the data in the RAM 41c is normal depending on whether or not the result of the calculation matches. The calculation method is not limited to exclusive OR, and other calculation methods (for example, summation) may be used.

  In this embodiment, the RAM parity adjustment data 1 is calculated using data stored in all the game RAM areas including the unused area 3 in the power interruption process, and the non-game including the unused area 4 is performed. RAM parity adjustment data is calculated using data stored in all areas of the RAM area, and RAM is calculated using data stored in all areas of the game RAM area including the unused area 3 in the startup process. It is determined whether or not the RAM 41c is normal based on the RAM parity 2 calculated using the data stored in all the non-game RAM areas including the parity 1 and the unused area 4. If an unauthorized program is stored in the use areas 3 and 4, it is determined that the RAM is abnormal. Therefore, it is possible to prevent an unauthorized program from being stored in the unused areas 3 and 4. That.

  In this embodiment, the RAM parity adjustment data 1 is calculated using data stored in all areas of the game RAM area including the unused area 3 in the power interruption process, and the non-game including the unused area 4 is performed. RAM parity adjustment data is calculated using data stored in all areas of the RAM area, and RAM is calculated using data stored in all areas of the game RAM area including the unused area 3 in the startup process. It is configured to determine whether or not the RAM 41c is normal based on the RAM parity 2 calculated using data stored in all areas of the non-game RAM area including the parity 1 and the unused area 4. RAM parity adjustment data 1 is calculated using data stored in the game RAM area not including the area 3, and stored in the non-game RAM area not including the unused area 4. RAM parity adjustment data is calculated using the data, and the RAM parity 1 calculated using the data stored in the game RAM area that does not include the unused area 3 in the startup process, the non-game that does not include the unused area 4 The RAM 41c may be determined to be normal based on the RAM parity 2 calculated using the data stored in the RAM area.

  In addition, the RAM parity adjustment data 1 is calculated using data stored in all areas of the game RAM area including the unused area 3 in the power interruption process, and stored in the non-game RAM area not including the unused area 4. RAM parity adjustment data is calculated using the generated data, and RAM parity 1 and unused area 4 are calculated using data stored in all areas of the game RAM area including the unused area 3 in the startup process. It may be configured to determine whether or not the RAM 41c is normal based on the RAM parity 2 calculated using data stored in the non-game RAM area that does not include the non-game RAM area. When an unauthorized program is stored in 3, it is determined that the RAM is abnormal, so that an unauthorized program can be prevented from being stored in the unused area 3.

  In addition, the RAM parity adjustment data 1 is calculated using data stored in the game RAM area not including the unused area 3 in the power interruption process, and stored in all the non-game RAM areas including the unused area 4. Non-game including RAM parity 1 and unused area 4 calculated using data stored in a game RAM area that does not include the unused area 3 in the startup process. A configuration may be adopted in which it is determined whether or not the RAM 41c is normal based on the RAM parity 2 calculated using data stored in all the regions of the RAM region. Even in such a configuration, the unused region 4 If an illegal program is stored in the memory area, it is determined that the RAM is abnormal, so that it is possible to prevent the unauthorized program from being stored in the unused area 4.

  In this embodiment, in the power interruption process executed when power interruption is detected, the RAM parity adjustment data for determining whether or not the data in the RAM 41c is normal is calculated, and the data is normal when the power is turned on. The process of calculating the RAM parity for determining whether or not, and the process of determining whether or not the data in the RAM 41c is normal based on the RAM parity when the power is turned on are divided into a game RAM area and a non-game RAM area However, in the power interruption process, the game RAM area is calculated by calculating adjustment data in which the calculation result using both the data stored in the game RAM area and the data stored in the non-game RAM area becomes a specific value. Or, it is set in the non-game RAM area, and both the data stored in the game RAM area and the data stored in the non-game RAM area are used in the startup process. Configuration for determining whether or not the data in the RAM 41c is normal based on whether or not the calculated result is a specific value, that is, adjustment data for determining whether or not the data in the RAM 41c is normal in the power interruption process Game RAM, processing for calculating data for determining whether the data is normal when the power is turned on, processing for determining whether the data in the RAM 41c is normal based on the data calculated when the power is turned on, The area and the non-game RAM area may be distinguished from each other, and with such a structure, adjustment data for determining whether or not the data in the RAM 41c is normal is calculated in the power interruption process. Processing, data for determining whether data is normal when power is turned on, data in RAM 41c based on data calculated when power is turned on It can be reduced program capacity necessary for processing for determining normal or not.

  Also in such a configuration, in the power interruption process, not only the game RAM area and the non-game RAM area, but also the adjustment data is calculated using the data of all areas including the unused areas 3 and 4, and the start process Whether or not the data in the RAM 41c is normal depending on whether or not the result calculated using the data of all the areas including the unused areas 3 and 4 is not only the game RAM area and the non-game RAM area. In such a configuration, if an invalid program is stored in the unused areas 1 and 2, it is determined that the RAM is abnormal. It is possible to prevent an illegal program from being stored in the memory.

  In this embodiment, as shown in FIG. 20, the reset circuit 49 of the game control board 40 has a monitor voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main controller 41 among the power supply voltages supplied from the power supply board 101. ), And when the monitoring voltage exceeds the operable voltage (main) (+3.5 V) at which the main control unit 41 becomes operable when the power is turned on, the reset signal is turned on and the main control unit 41 is turned on. After that, when a time sufficient for the drive voltage (DC + 5V) of the main control unit 41 to stabilize (a time sufficient for the monitoring voltage to rise to + 24V) has elapsed, the reset signal is turned OFF and the main voltage is increased. The control unit 41 is activated. On the other hand, the reset circuit 95 of the effect control board 90 has a sub-control unit 91 when the reset signal is turned off by the reset circuit 49 when the power is turned on, that is, at a timing earlier than the timing at which the main control unit 41 is activated. When the power is turned on, the sub-control unit 91 is activated at an earlier stage than the main control unit 41, and a return command or a setting command (start) transmitted from the main control unit 41 is started. ) In a state where the sub-control unit 91 can receive.

  The main control unit 41 executes the above-described initial setting process when the reset signal output from the reset circuit 49 is turned off and starts up. After the return command is transmitted at the end of the process, the timer interrupt is permitted, and then the timer interrupt process is executed at regular intervals. When the setting signal switch 37 is turned on when the reset signal is turned off and the RAM 41c is initialized and the setting change state is started without returning to the state before the power interruption. Before the timer interrupt is permitted at the end of the initial setting process, a setting command (start) is sent to the sub-control unit 91 instead of the return command, and then the timer interrupt is permitted. Interrupt processing is executed at regular intervals. On the other hand, the sub-control unit 91 is activated before the main control unit 41 is activated, performs and completes an initial setting process, and waits until a return command or a setting command (start) is received in a state where the command can be received. To do.

  Next, after transmitting the return command or the setting command, the main control unit 41 executes the timer interrupt process (main) at regular intervals, and executes the normal time command transmission process in the timer interrupt process (main). At this time, if the command to be transmitted is not stored in the command queue, the door command is generated and transmitted based on the detection state of the door opening detection switch 25. On the other hand, the sub-control unit 91 receives the return command or the setting command (start) and starts output control of the rendering device.

  In addition, the main control unit 41 transmits a door command or the like by a normal command transmission process executed in the timer interrupt process (main), and after the start of the main control unit 41 until the end of the initial setting process. After the main control unit 41 is activated, a return command or a setting command (start) is transmitted, and then a command such as a door command transmitted by a normal command transmission process is permitted. It will be.

  Further, as shown in FIG. 20, the main control unit 41 executes a power failure determination process in the timer interrupt process (main), and based on whether or not a voltage drop signal is input from the power interruption detection circuit 48. Identify the occurrence of a power outage. The power interruption detection circuit 48 monitors the aforementioned monitoring voltage (DC + 24V) higher than the driving voltage (DC + 5V) of the main control unit 41, and detects a voltage drop that is higher than the driving voltage (DC + 5V) of the main control unit 41. Since the voltage drop signal is output when the voltage (main) (+20 V) or less is reached, the main control unit 41 identifies the occurrence of power interruption when the monitoring voltage is equal to or less than the voltage drop detection voltage (main). . When the occurrence of a power interruption is identified in the power failure determination process, the main control unit 41 executes a power interruption command transmission process and sends all commands stored in the command queue to the sub-control unit 91. Then, the power interruption process (main) is executed.

  In the reset circuit 49, the monitoring voltage is lower than the voltage drop detection voltage (main) (+ 20V) and is lower than the operation limit voltage (main) (+ 8V) higher than the operable voltage (main) (+ 3.5V). As a result, the reset signal is turned ON to make the main control unit 41 inoperable. The operation limit voltage (main) is a voltage drop after the power failure detection circuit 48 becomes equal to or lower than the voltage drop detection voltage (main) for detecting occurrence of power failure until the voltage drops to the operation limit voltage (main). The main control unit 41 identifies the occurrence of power interruption after the detected voltage (main) or less, executes the command transmission process at power interruption, and secures the time required to execute the power interruption process. Is set to

  The time required for the main control unit 41 to identify the occurrence of power interruption after executing the voltage drop detection voltage (main) or less, execute the command transmission process at power interruption, and execute the power interruption process is as follows: The maximum time until the main control unit 41 detects a power interruption (0.56 ms because the occurrence of power interruption is specified for each timer interrupt process (main)), and the command transmission process in the power interruption command queue The time required to transmit the maximum number of storable commands (32) (40 μs (MODE transmission 10 μs, transmission interval 10 μs, EXT transmission 10 μs, transmission interval 10 μs) is required for one command transmission. X32 = 1280 μs) and the time required for the power interruption process (main).

  On the other hand, the power interruption detection circuit 98 monitors the aforementioned monitoring voltage (DC + 24V) higher than the driving voltage (DC + 5V) of the sub-control unit 91, and the monitoring voltage is lower than the operation limiting voltage (main) (+ 8V), Since the voltage drop signal is output when the voltage drop detection voltage (sub) (+ 6V) is lower than the drive voltage (DC + 5V) of the sub control unit 91, the sub control unit 91 monitors the voltage drop detection voltage (sub). The occurrence of power interruption is specified by the following. And the sub control part 91 will perform a power interruption process (sub), if generation | occurrence | production of a power interruption is specified in a power failure determination process.

  In the reset circuit 95, the monitoring voltage is lower than the voltage drop detection voltage (sub) (+ 6V) and lower than the operation limit voltage (sub) (+ 4V) higher than the operable voltage (sub) (+ 3.5V). As a result, the reset signal is turned ON to make the sub-control unit 91 inoperable. The operation limit voltage (sub) is a voltage drop after the power failure detection circuit 98 becomes equal to or lower than the voltage drop detection voltage (sub) for detecting the occurrence of power failure until the voltage drops to the operation limit voltage (sub). It is set so that the time required for the sub control unit 91 to identify the occurrence of power interruption and to execute the power interruption process after the detection voltage (sub) or less is reached.

  In addition, the sub-control unit 91 makes the main control unit 41 inoperable after the monitoring voltage is the operation limit voltage (main), that is, the power-off command transmission process and the power-off process (main) by the main control unit 41 are completed. When a voltage drop detection voltage (sub) lower than the voltage falls below the voltage drop detection voltage (sub), the occurrence of power interruption is specified by the output voltage drop signal, and the power interruption process (sub) is executed. Since the state in which the command can be received is maintained until the command transmission process at power interruption is completed, the power interruption process is executed in a state where the main control unit 41 has received all the commands transmitted by the command transmission process at power interruption. Can be done. Note that even if the timing at which the sub-control unit 91 identifies the occurrence of power interruption is the timing before the main control unit 41 becomes inoperable, the command transmitted by the main control unit 41 by the command transmission process at power interruption is used. If the configuration is such that the command can be received until a timing sufficient to receive all, the main control unit 41 executes the power interruption process in a state where all the commands transmitted by the power interruption command transmission process have been received. can do.

  As described above, the main control unit 41 according to the present embodiment generates a command in accordance with the progress of the game in the main process and the like, stores the generated command in the command queue, and performs a normal time command in the timer interrupt process (main). In this configuration, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91 every time transmission processing is executed.

  In such a configuration, in a state where a plurality of commands are stored in the command queue, the power supply to the slot machine 1 may be stopped and a power interruption may occur, and the main control is performed when the main control unit 41 detects a power interruption. In the state where a plurality of commands are not transmitted on the unit 41 side, the untransmitted commands are held as they are even after the power interruption, and the commands held before the power interruption after the power interruption is returned to the sub-control unit 91 When the transmission is performed, the control state on the main control unit 41 side at the time of power interruption and power recovery will be different from the control state on the main control unit 41 side specified on the sub control unit 91 side.

  On the other hand, in the present embodiment, the main control unit 41 is stored in the command queue before executing the power interruption process (main) for enabling the return to the control state before the power interruption when the power interruption is detected. Since the command transmission process at the time of power interruption is executed in order to transmit all commands to the sub control unit 91, the control state on the main control unit 41 side at the time of power interruption and recovery from power interruption, and the sub control unit 91 The control state on the main control unit 41 side specified on the side can be matched as much as possible.

  Further, the main control unit 41 has a maximum number of commands that can be stored in the command queue after the power supply is stopped after the power interruption is detected (up to 32 commands in this embodiment). Is transmitted to the sub-control unit 91 and after the power interruption is detected, all the commands stored in the command queue are transmitted after the power interruption process (main) is completed. The process up to the power interruption process (main) can be executed reliably.

  In this embodiment, the main control unit 41, which is the first control means for controlling the game, transmits a command as control information to the sub-control unit 91, which is the second control means for controlling the effect. However, the first control means may be a control means for performing control other than game control, for example, effect control. The second control unit may be a control unit that performs some control based on the control information transmitted from the first control unit. For example, the first control unit is a control unit that controls the effect. In some cases, the control means for controlling the effect device based on the control information transmitted from the first control means may be the second control means.

  In this embodiment, as a power interruption process (main) executed by the main control unit 41 (first control means), RAM parity adjustment is performed so that the RAM parity (exclusive OR) of the backup area becomes zero. By performing the process of setting data and setting destruction diagnosis data (data other than 0), the RAM parity is 0 at the time of power failure recovery, and the destruction diagnosis data matches, so the data in the backup area Can be determined as normal, but when the power supply to the slot machine 1 is stopped and a power interruption occurs, the power interruption process is performed so that the control state before the power interruption can be restored. For example, a configuration may be adopted in which it is possible to determine that the data in the backup area is normal by setting the checksum of the backup area and matching the checksum calculated when power is restored.

  Further, in this embodiment, the reset circuit 49 of the game control board 40 is reset before the power supply voltage drops below the operable voltage (main) at which the monitoring voltage drops and the main control unit 41 becomes inoperable. Is supplied to the main control unit 41, and the main control unit 41 is configured to stop all operations by being supplied with a reset signal, that is, to be in an uncontrollable state. The period from when the reset signal is supplied until control is disabled is required to transmit the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and to complete the power interruption process (main). In the configuration in which the reset signal is not supplied to the main control unit 41 when power is interrupted, the monitoring voltage is lower than the operable voltage (main) of the main control unit 41. The period until the control becomes impossible is longer than the period required to transmit the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and to complete the power interruption process (main). Even after the power failure is detected, it is possible to reliably execute the processing from the transmission of all the commands stored in the command queue to the power failure processing (main).

  Further, in this embodiment, the operation limiting voltage (main) that stops the operation of the main control unit 41 when power interruption occurs is equal to or lower than the voltage drop detection voltage (main) that the power interruption detection circuit 48 detects the occurrence of power interruption. After the time has elapsed, the time until the voltage drops to the operation limit voltage (main) becomes equal to or lower than the voltage drop detection voltage (main). The period until the main control unit 41 becomes inoperable after the occurrence of the power interruption is stored in the command queue by setting so as to secure the time required to execute the power interruption process. The maximum possible number of commands is transmitted to the sub-control unit 91 and is longer than the period required to complete the power interruption process (main). Driving voltage drop capacitor The period until the main control unit 41 becomes inoperable after being interrupted by delaying by a battery, a capacitor, etc. is sent to the sub-control unit 91 the maximum number of commands that can be stored in the command queue, and The sub-control unit 91 is configured to have a configuration that is longer than the period required to complete the power interruption process (main) or the maximum number of commands that can be stored in the command queue until the main control unit 41 becomes inoperable. The maximum number that can be stored in the command queue may be set so as to be longer than the period required to complete the power interruption process (main), even in these configurations, After the occurrence of power interruption, it is possible to reliably execute the processing from transmission of all commands stored in the command queue to power interruption processing (main).

  In addition, the main control unit 41 according to the present embodiment executes a command transmission process at power interruption when detecting power interruption, and transmits all commands stored in the command queue to the sub control unit 91. Since the power disconnection process (main) is executed and each output port of the parallel output port 513 including the output port that outputs a command in the power disconnection process (main) is initialized, the power supply is erroneously in an unstable state. It is possible to prevent the command from being transmitted.

  In addition, the main control unit 41 of the present embodiment executes a normal time command transmission process in the timer interrupt process (main), so that a predetermined number of commands stored in the storage area stored in the command queue. (In this embodiment, one command) is transmitted to the sub-control unit 91 every predetermined trigger (timer interrupt processing (main) once every four times), so a predetermined number (in this embodiment, 1) Even if the above commands are stored in the command queue, the number of commands transmitted in one timer interrupt process (main) is limited to a predetermined number. It is possible to prevent other control by the main control unit 41 from being delayed due to the transmission of.

  In addition, the main control unit 41 of the present embodiment, at a predetermined opportunity (when performing a normal command transmission process executed in the timer interrupt process (main)), a command corresponding to the progress of the game (internal winning command) When the stop operation command is not stored, a door command indicating the detection state of the door opening detection switch 25 is transmitted to the sub-control unit 91, whereby the open / closed state of the front door 1b is determined. 91 can be specified, and the door command is transmitted when a command corresponding to the progress of the game is not stored in the command queue at a predetermined opportunity. Delayed by transmission or other control (for example, each control in the main process) by the main control unit 41 by transmission of a door command ) It is possible to prevent the delay.

  The main control unit 41 is permitted to transmit a command such as a door command transmitted by a normal command transmission process after transmitting the return command or the setting command (start) after the activation. After the power is turned on, the door command will not be sent until it returns to the state before power interruption and sends a return command, or until the setting command (start) is sent without returning to the state before power interruption. Therefore, after determining whether or not to return the main control unit 41, the sub control unit 91 side can specify the state of the main control unit 41 side, and the main control unit 41 is in the control state before the power interruption. It is possible to prevent an unintended operation from being performed when the sub control unit 91 receives a command in a state where it is not determined whether or not to return.

  In the present embodiment, when any command is not stored in the command queue in the normal command transmission process, the door command indicating the detection state of the door opening detection switch 25 is generated and transmitted. When no command is stored in the command queue in the normal command transmission process, the operation switches (MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R) are based on the output of the switch detection circuit 44. It is possible to specify the control state on the main control unit 41 side, such as a command indicating a detection state (on / off), a command indicating whether or not an error has been detected and a type of detected error, and a command capable of specifying the game state of the game. A configuration may be adopted in which a command is generated and transmitted to the sub-control unit 91. Even in such a configuration, the sub-control unit 91 can specify the control state on the main control unit 41 side, and the transmission of a command according to the progress of the game can specify the control state of the main control unit 41. It is possible to prevent delays due to transmission or other control by the main control unit 41 from being delayed due to transmission of a command capable of specifying the control state of the main control unit 41.

  Next, a timer counter for measuring a time interval used by the main control unit 41 for game progress control and the like will be described with reference to FIGS.

  The main control unit 41 sets an initial value corresponding to the measured time as the timer value of the timer counter assigned to the RAM 41c when the time measurement start condition is satisfied, and periodically sets a timer in the timer interrupt process (main). The value is subtracted, and when the timer value becomes 0, it is specified that the time has elapsed.

  Specifically, when a timing start condition is established in the main process, the main control unit 41 sets an initial value of a timer value corresponding to the timing time in an area to which a timer counter corresponding to the condition is assigned. The set timer value is decremented by 1 until it becomes 0 every 2.24 ms in the time counter update process of the timer interrupt process (main).

  Then, in the main process, as shown in FIG. 21, the address of the corresponding timer counter is acquired (Si1), the acquired value is read (Si2), and it is determined whether the read value is not 0 (Si3). If it is determined that the read value is 0, it is determined that the time has elapsed.

  As shown in FIG. 22, the timer counter used in the present embodiment has an initial value of 1 byte timer A, 1 byte timer B, 1 byte timer C, an initial value exceeding 1 byte, 2 bytes or less. 2 byte timer A, 2 byte timer B, 2 byte timer C, 2 byte timer D are included.

  The 1-byte timer is a timer for measuring a relatively short period that can be measured with a timer value within 1 byte. For example, an external output signal timer that measures an output period of an external output signal, an LED output update period LED update timer that measures the time, stop invalid timer that measures the period until the stop operation is validated after detection of the stop operation, wait for payout that measures the period until the medal payout starts after the reel stops Timer, insertion detection timer for measuring the period after the insertion medal sensor 31 is detected ON, insertion slot detection timer for measuring the period after the detection of the insertion slot sensor 26 is detected, and ON of the dispensing sensor 34c are detected There are a payout detection timer for measuring a period after being started, a start-up timer for measuring a period from the start of reel rotation until the stop operation becomes effective. Among these, the stop invalid timer, the payout waiting timer, and the start timer do not cross the timing at which one game ends, but the external output signal timer, the LED update timer, the input detection timer, the input port The detection timer and the payout detection timer may straddle the timing at which one game ends with the time measured by these timers.

  The 2-byte timer is a timer for measuring a relatively long period that cannot be measured with a timer value within 1 byte. For example, a 1-game time timer that measures a specified time (about 4.1 seconds) required for 1 game. , A security signal timer for measuring the minimum output period of the security signal among the external output signals, a standby time timer for measuring a period from the end of the game, and a hopper empty for measuring a period in which the payout sensor 34c is not detected after the hopper motor 34b is driven. There is a timer. Of these, the waiting time timer and the hopper empty timer do not straddle the timing when one game ends, but the one gaming time timer and the security signal timer have one measuring time measured by these timers. There are times when the timing of the end of.

  As described above, the timer counter is a timing at which one game ends, that is, a timing at which a part of the RAM 41c is initialized as the game progresses (a part of the RAM 41c at the end of one game or at the end of a specific gaming state). Including a timer counter that measures a measurement period spanning the timing at which a part of the RAM 41c is initialized in accordance with the progress of the game. The counter is also assigned to a special work that is not initialized at the timing according to the progress of the game.

  Among these timer counters, the 1-byte timers A to C are allocated to the consecutive 3 byte areas (804CH to 804EH) of the RAM 41c one byte at a time, and the 2-byte timers A to D are the continuous 8-byte RAM 41c. Two bytes are allocated to the area (804FH to 8055H). Further, the 1-byte timers A to C and the 2-byte timers A to D are also assigned to continuous areas of the RAM 41c. Hereinafter, an area to which the 1-byte timers A to C are allocated is referred to as a 1-byte timer group, and an area to which the 2-byte timers A to D are allocated is referred to as a 2-byte timer group. That is, both the 1-byte timer group and the 2-byte timer group are set in an area to which consecutive addresses are assigned according to a predetermined rule. The area to which consecutive addresses are assigned according to a predetermined rule is, for example, an area to which an address added by N (N is a natural number) from the start address and the start address is assigned.

  FIG. 23 is a flowchart showing the control content of the time counter update process.

  In the time counter update process, first, the number of 1-byte timer counters to be updated (3 in this embodiment) is set as the number of processes for 1 byte (Sj1), and the start address (804CH) of the 1-byte timer group is set. A pointer is set (Sj2).

  Next, if the value of 1 byte stored at the specified address (address indicated by the pointer) is not 0, 1 is subtracted from the value of 1 byte of the specified address (Sj3), and 1 is subtracted from the number of times set in the step of Sj1. (Sj4), it is determined whether the number of processes after subtraction is 0 (Sj5).

  If the number of processes after subtraction is not 0 in step Sj5, that is, if all 1-byte timers have not been updated, 1 is added to the pointer (Sj6), and the process returns to step Sj3. As a result, the pointer moves to the address of the unprocessed 1-byte timer, and if the 1-byte value of the designated address is not 0, the pointer is subtracted.

  When the number of processes after subtraction in step Sj5 is 0, that is, when all the 1-byte timers have been updated, the number of 2-byte timer counters to be updated as the number of 2-byte processes (this embodiment) Then, 4) is set (Sj7), and the pointer is incremented by 1 (Sj8). As a result, the pointer moves to the start address (804FH) of the 2-byte counter group.

  Next, if the 2-byte value stored in the area consisting of the designated address (address indicated by the pointer) and the next address is not 0, the 2-byte value of the designated address and the next address is decremented by 1 (Sj9), and Sj7 1 is subtracted from the number of processes set in step (Sj10), and it is determined whether or not the number of processes after subtraction is 0 (Sj11).

  If the number of processes after the subtraction is not 0 in step Sj11, that is, if all the 2-byte timers have not been updated, the pointer is incremented by 2 (Sj12), and the process returns to step Sj9. As a result, the pointer moves to the address of the unprocessed 2-byte timer, and if the 2-byte value of the designated address and the next address is not 0, the pointer is subtracted.

  If the number of processes after subtraction in step Sj11 is 0, that is, if all the 2-byte timers have been updated, the process ends.

  As described above, in this embodiment, the value of the timer counter assigned to the RAM 41c is periodically updated to become a specific value (0), thereby specifying the passage of time. Conventionally, when measuring multiple types of time intervals, timer values are set and updated within multiple types of processing that require timekeeping, and each type of program for updating multiple types of timer values is processed. Since it is necessary to provide it inside, it was a factor which increased program capacity. In addition, since multiple types of timer counters are assigned as data groups for each process used, it is necessary to read out the values of unrelated addresses in order to update all of them in one process. there were.

  On the other hand, in this embodiment, an area in which a plurality of types of timer counter values are stored is set to an area to which consecutive addresses are assigned according to a predetermined rule in the RAM 41c, and the timer value stored in the designated address is Since multiple types of timer values are updated by repeatedly executing the update process while changing the specified address for the area where multiple types of timer counter values are stored by adding a constant to the current specified address Thus, the program capacity can be reduced as compared with the case where each of the processes for designating a plurality of types of addresses and updating the values of the addresses is performed in the individual processes.

  Multiple types of timers can be obtained by repeatedly executing the process of updating the timer value stored at the specified address while changing the specified address for the area where the multiple types of timer counter values are stored by performing a predetermined calculation. Any configuration may be used as long as the value is updated. For example, by adding a constant to the current designated address, multiple types can be obtained by repeatedly executing while changing the designated address for an area in which multiple types of timer counter values are stored. The timer value may be updated, or a value corresponding to the number of processes with respect to the reference address (for example, for a 1-byte counter, +1 for the number of processes 1, +1 for the number of processes 2, and the number of processes While changing the designated address for the area where multiple types of timer counter values are stored by adding or subtracting +3 ...) for 3 Ri may be configured to update a plurality of types of the timer value by return run.

  In the present embodiment, the configuration includes seven types of timer counter values of 1-byte timers A to C and 2-byte timers A to D. However, at least two types of timer counter values are determined according to a predetermined rule of the RAM 41c. In the process of updating the timer value stored in the specified address, the specified address for the area in which multiple types of timer values are stored is changed by performing a predetermined operation. However, if the configuration is such that two or more types of timer values are updated by repeated execution, the program capacity can be reduced as described above.

  In addition, only one of the 1-byte timer and 2-byte timer is set to set the timer counter value in an area to which consecutive addresses are assigned according to a predetermined rule in the RAM 41c, and update the timer value stored in the designated address. A configuration in which a plurality of types of timer values are updated by repeatedly executing a predetermined calculation while changing a designated address for an area in which a plurality of types of timer values are stored may be employed.

  Further, only for some of the timer counters provided in the main control unit 41, a process of setting a timer value in an area to which consecutive addresses are assigned according to a predetermined rule in the RAM 41c and updating the timer value stored in the designated address, A configuration in which a plurality of types of timer values are updated by repeatedly executing a predetermined calculation while changing a designated address for an area in which a plurality of types of timer values are stored may be employed.

  In this embodiment, a separate timer counter is provided for each type of period to be measured. For example, a single timer counter may be shared for a plurality of types of periods in which the measurement periods do not overlap.

  In the present embodiment, the main control unit 41 executes the process according to the timer interruption process (main) for periodically performing a predetermined process regardless of the progress of the game and the progress of the game. A main process that performs different processes in stages, and the main control unit 41 sets an initial value to the timer counter when a timing condition is satisfied in the main process, and a plurality of types of timer interrupt processes (main) The timer value is updated, and it is not necessary to provide a process for updating multiple types of timer values in each process constituting the main process, so the program capacity for updating multiple types of timer values is reduced. be able to.

  In this embodiment, the timer interrupt process (main) is executed by periodically interrupting the main process. However, in the timer interrupt process periodically performed, it is determined in advance regardless of the progress of the game. The main control unit 41 may be configured to perform both a periodic process for performing the processed process and a main process for performing a process that varies stepwise depending on the progress of the game. By setting an initial value to the timer counter when the timing condition is satisfied in the process and updating multiple types of timer values in the periodic process, multiple types of timer values are set in each process constituting the main process. Since it is not necessary to provide a process for updating, it is possible to reduce the program capacity related to updating of a plurality of types of timer values.

  Further, in this embodiment, in the time counter update process, the value of the address is updated on condition that the value of the designated address is not 0, and the timer value is updated to an abnormal value. Can be prevented.

  Further, in this embodiment, in the time counter update process, the number of processes equal to the number of timer counters to be updated is set, and the process of updating the timer value is repeatedly executed for the set number of processes. The number of timer counters to be updated can be easily set. For example, when a plurality of types of timer counters having different update intervals are provided, the type of timer value to be updated can be arbitrarily set according to the number of processes to be set. it can.

  Note that the number of processes, that is, the number of timer counters to be updated may be set in a program, or values set in a table may be read and set.

  In addition, the timer counter to be updated last is set in advance without setting the number of processes at the beginning, and the timer value is updated repeatedly until the address of the timer counter is reached. The specific end value (for example, FFH) is stored at the next address of the timer counter to be executed, and the process of updating the timer value is repeatedly executed until the value read from the designated address becomes the specific end value. good.

  In this embodiment, a 1-byte timer counter and a 2-byte timer counter are provided, and a process for updating a 1-byte timer value and a process for updating a 2-byte timer value are separately provided. Therefore, the capacity of the program and the capacity occupied by the timer value in the RAM 41c can be reduced as compared with the case where the process of updating the 1-byte timer value and the process of updating the 2-byte timer value are made common.

  In this embodiment, a relatively long time corresponding to an initial value exceeding 1 byte is measured by providing a 2-byte timer counter. For example, a timer counter having a different update interval, for example, a timer, is used. Interrupt processing (main) By providing a first timer counter that is updated once every four times and a second timer counter that is updated once every fourteen times, a relative value can be obtained without providing a 2-byte counter. It is also possible to employ a configuration for measuring a long time interval. By doing so, it is not necessary to provide a process for updating a 1-byte timer value and a process for updating a 2-byte timer value. It is possible to reduce the program capacity related to the update.

  In the present embodiment, a plurality of types of timer counters are assigned to special works that are not initialized in accordance with the progress of the game in the RAM 41c, and are not initialized in accordance with the progress of the game. Regardless of the progress of the game, it is possible to measure the time spanning the timing when a part of the RAM 41c is initialized in accordance with the progress of the game.

  In particular, in this embodiment, not only the timer counter that may cross the timing when the measurement period ends in one game, that is, the timing at which a part of the RAM 41c is initialized as the game progresses, Since the timer counter that does not cross over the timing at which a part of the RAM 41c is initialized according to the progress is stored in the area assigned to the special work together with other timer counters, the timer counter can be easily managed. In addition, a timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game is set, and a timing at which a part of the RAM 41c is initialized at the measurement period according to the progress of the game. The usage of the timer counter can be easily changed by a later design change, such as changing to a timer counter that may straddle. It can be. In addition, as described above, if a single timer counter is shared for a plurality of types of periods in which measurement periods do not overlap, the timing at which a part of the RAM 41c is initialized may be crossed as the game progresses. It is possible to measure the measurement period and the measurement period that does not cross the timing at which a part of the RAM 41c is initialized in accordance with the progress of the game with one timer counter.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  In the embodiment, the example in which the present invention is applied to a slot machine in which bets are set using medals and credits as game values has been described. However, a slot machine that sets bets using game balls as game values. Alternatively, the present invention may be applied to a complete credit type slot machine in which a bet amount is set using only credit as a game value. In the case of using a game ball as a game value, for example, one medal can correspond to five game balls, and when three bets are set in the first embodiment, 15 game balls are used. This is equivalent to setting the number of bets using.

  Further, the present invention is not limited to the use of only one of a plurality of types of game values such as medals and game balls, for example, a combination of a plurality of types of game values such as medals and game balls. It may be. That is, it is possible to play a game by setting the number of bets using any of a plurality of types of gaming values such as medals and game balls, and a plurality of types of games such as medals and game balls when a winning occurs. You may apply the slot machine which can pay out all of utility values.

  In the embodiment, the slot machine is described as an example of the gaming machine. However, the main control unit 41 and the initial setting process related to the main control unit 41 disclosed in the above embodiment, the timer interrupt process, the command storage process, and the normal time Processes related to the sub-control unit 91 and the sub-control unit 91, such as command transmission processing, power-off command transmission processing, timer counter update processing, etc., are made by launching game balls to other gaming machines, for example, gaming areas. The present invention may be applied to a pachinko gaming machine or the like in which a game is performed and a game ball that has been launched enters a prize opening provided in the game area and a prize is generated, so that the game ball is paid out as a prize ball.

1 Slot machine 2L, 2C, 2R Reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 91 Sub control unit

Claims (1)

In gaming machines that perform games,
Storage means capable of storing a program and assigned an address capable of specifying a storage area;
Control means for performing control according to a program stored in the storage means;
First program calling means for calling a program stored at a designated address by designating an address;
Second program calling means for calling a program stored in a specific address corresponding to the specified parameter among a plurality of specific addresses assigned at predetermined intervals by specifying a parameter having a data amount smaller than the address ,
With
The storage means stores a first specific program in an area starting from one specific address, stores a second specific program in an area starting from a specific address next to the one specific address, and stores the first specific program A gaming machine that stores a predetermined program in an area after the area where the program is stored and before the next specific address.

Images