JP2018093892A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a program from being executed in an inappropriate state of a CPU brought by malfunction due to noise, etc..SOLUTION: Though a program is started with cancellation of a reset after power-on, interruption is invalidated by an initial setting INI inside a CPU. Interruption is invalidated also in an initial setting P-INI which is firstly executed in a program A. Therefore, reactivation process is normally executed because of the invalidation of interruption even in an irregular case where the program jumps to a start address due to a certain factor.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a gaming machine such as a slot machine or a pachinko machine, and more particularly to an initial setting of a CPU included in the gaming machine.

  2. Description of the Related Art A gaming machine (a spinning machine, slot machine) having a plurality of spinning cylinders with symbols arranged on the outer peripheral surface is known. This type of gaming machine gives a certain game value to a game medium (medal) and performs a game for acquiring such a game medium. In addition, this type of gaming machine has an internal lottery triggered by the player's rotation start operation and starts rotation of a plurality of spinning cylinders, and a mode according to the result of the internal lottery as a player's stop operation trigger. In order to stop multiple cylinders. The game result is determined by the symbol combination displayed on the winning determination line in a state where the plurality of spinning cylinders are stopped, and medals are paid out according to the game result.

  Various devices such as a liquid crystal display device, a display lamp for display (electric decoration), and a sound generator (sound device, speaker) are provided in the gaming machine as devices that play a role of enhancing the interest of the player. In addition, there may be provided a movable accessory (movable body) that includes a movable part and produces an effect by the movement of the movable part. In the following description, not only the liquid crystal display device, the electrical decoration, and the sound generation device itself but also their control devices may be referred to as “effect devices”.

When the power is turned on, the CPU of the sub-control board prohibits interrupts and performs various register settings as a startup process. When the startup process ends, the interrupt is permitted and the main process routine is entered.

  When the power is turned on or reset, the CPU (central processing unit) provided in the gaming machine performs processing related to predetermined initial settings by returning the CPU, its peripheral devices, effect devices, etc. to a predetermined state. Yes, the CPU again starts various processes from that state. The state immediately before the power is turned off is stored in a nonvolatile memory (backup memory), and the state at the time of turning off the power can be restored by reading and setting the stored contents in the initial setting.

  In the initial setting, the CPU is executed by reading an initial setting program (start program) stored in advance in the ROM and performing processing in accordance with instructions of the program, and is provided in advance in the CPU. Some CPUs themselves set internal registers and pointers depending on the circuit or the like. The former can be called initial setting by a program, and the latter can be called initial setting (in the CPU) by the CPU itself. Examples of the former include setting of registers and pointers, resetting of peripheral devices and production devices, and restoration of the contents of backup memory. Examples of the latter include setting registers and pointers, and prohibiting interrupts. The contents of the initial setting by the CPU itself may be changed later by the start program. The contents of the initial setting by the CPU itself (how to make the contents of the register, etc.) are predetermined by the CPU manufacturer, and the user of the CPU creates a start program accordingly. CPU users usually do not need to consider what processing is being performed by the CPU itself.

  In the gaming machine described in Patent Document 1, when the processing by the program is started together with the release of the reset after the power is turned on, the interrupt is invalidated in the CPU. For this reason, when the start program for initial setting operates, CPU interruption is prohibited. The start program is designed with that in mind. If the process proceeds in the order of reset, initial setting by the CPU, and reading and execution of the start program by the CPU, the processing is performed correctly because the interrupt is invalidated by the initial setting by the CPU itself.

  However, although it is an irregular case that does not go through the above process, the program may jump to the start address (for example, 0000) of the start program for some reason. In this case, since the initial setting by the CPU itself has not been performed, interruption is not prohibited. When the start program is executed in this interrupt enabled state, an interrupt is actually generated, and there is a high possibility that the restart process by the start program is not normally performed. As a result, the operation of the gaming machine may be hindered.

  An object of the present invention is to provide a gaming machine capable of normally performing a restart process even when execution of a start program is started in the irregular state as described above.

The present invention performs at least a storage unit storing a program and an initial setting (initial setting by the CPU) by the central processing unit itself by resetting, and a position (start address) determined by the initial setting by the central processing unit itself in the storage unit In a gaming machine comprising a processing unit (sub-board) including a central processing unit that reads and executes a start program stored in
The start program includes an initial setting instruction by a program that executes processing corresponding to at least a part of initial setting by the central processing unit itself performed by the central processing unit based on reset. The initial setting by the central processing unit itself includes setting an internal register to disable interrupts and setting a program counter to an initial value (for example, 0000). If the start program is to be executed without resetting for some reason, the initial setting by the program is originally lacking, but is included in the initial setting by the central processing unit itself. In addition, the processing that should be originally performed should also be performed in the initial setting by the program. The initial setting instruction by such a program is, for example, interrupt prohibition.

  Preferably, the initial setting instruction by the program is arranged at the head of the start program. “Head” means a position that is executed before other processing, particularly processing that may be affected by the presence or absence of initial setting by the central processing unit itself. For example, even if the start program is not directly arranged at the execution start address, the position may be a position where no problem occurs when the start program is executed without resetting for some reason.

  According to the present invention, the start program includes an initial setting instruction for executing processing corresponding to at least a part of the initial setting performed by the central processing unit based on reset. Even if the processing starts from the program start address, the program can be executed normally.

It is a perspective view of the slot machine which shows the state where the front door was closed. It is a perspective view of the slot machine showing a state where the front door is opened. It is a block diagram of a slot machine. It is a flowchart of the gaming process of the slot machine. It is a block diagram of the communication system of the gaming machine according to the embodiment of the invention. It is explanatory drawing of the slave board | substrate which concerns on embodiment of invention. According to the embodiment of the invention (initial setting at the time of program execution: disabling interrupts) According to the embodiment of the invention (initial setting at the time of program execution: disabling interrupts) According to the embodiment of the invention (initial setting at the time of program execution: setting of a bus state controller) According to the embodiment of the invention (initial setting at the time of program execution: setting of a bus state controller) According to the embodiment of the invention (initial setting at the time of program execution: setting of a bus state controller) According to the embodiment of the invention (initial setting at the time of program execution: setting of a bus state controller) According to the embodiment of the invention (initial setting during program execution: setting of CS0 space for storing start program) According to the embodiment of the invention (initial setting during program execution: setting of CS0 space for storing start program) According to the embodiment of the invention (initial setting during program execution: setting of CS0 space for storing start program) According to the embodiment of the invention (adjustment of reset release timing at initial setting) According to the embodiment of the invention (adjustment of reset release timing at initial setting) According to the embodiment of the invention (adjustment of reset release timing at initial setting) FIG. 19 is a circuit diagram (FIG. 19A) and a timing chart (FIG. 19B) for explaining the operation of the processing unit according to the embodiment of the invention (maintaining the initial setting at the time of malfunction). It is a perspective view in the state where the front door of the pachinko machine was opened. It is a figure (front view) which shows the mode of the board surface of a pachinko machine. It is a block diagram of a pachinko machine.

<Mechanical structure of gaming machine>
FIG. 1 shows a front view of the slot machine with the front door closed, and FIG. 2 shows a front view of the slot machine with the front door open. In the following description, the upward, downward, left, or right directions refer to directions viewed from the player facing the slot machine unless otherwise specified.

  1 and 2, reference numeral 100 denotes a slot machine. The slot machine 100 includes a slot machine housing 120 and a front door that is attached to one side of the front surface of the slot machine housing 120 by a hinge or the like so as to be opened and closed. 130. The front door 130 includes an upper door 130U and a lower door 130L that can be opened and closed independently.

  A game display 131 is provided in the upper right corner of the front surface of the front door 130. The player can see three reels of the reel unit 203 through the game display unit 131.

  A medal insertion slot 132 for a player to insert medals is provided on the right side of the upper surface of the upper door 130U. On the left side of the medal insertion slot 132, a clogged medal is inserted into the slot machine. A reject button 133 is provided for forcibly discharging outside 100.

  A start switch 134 for starting a game is provided on the left side of the upper surface of the lower door 130L, and three stop buttons 140 are provided between the start switch 134 and the medal slot 132 corresponding to each of the three reels. Yes.

  A liquid crystal panel LCD1 is provided at the center of the upper door 130U, and a liquid crystal panel LCD2 is provided on almost the entire surface of the lower door 130L.

  A switch (cross key unit) SW as an operation unit is provided at the center of the upper surface of the lower door 130L, that is, above the stop button 140 and between the bet switch BET and the medal slot 132. The switch SW includes, for example, a cursor key (switch) for moving the cursor up / down / left / right, an operation confirmation button / cancel button, and the like.

  Illuminated DRU, DRL, DLU, and DLL are provided on the left and right ends of the slot machine 100, respectively. That is, an electric decoration DLU is provided at the left end of the upper door 130U, an electric decoration DRU is provided at the right end, an electric decoration DLL is provided at the left end of the lower door 130L, and an electric decoration DRL is provided at the right end. Each of the electrical decorations DRU, DRL, DLU, and DLL includes a light emitting device (LED).

  As shown in FIG. 2, the slot machine housing 120 is fixed to the inner bottom surface, stores a plurality of medals therein, and stores the stored medals in a payout opening provided at the lower front portion of the lower door 130 </ b> L. A hopper device 121 for paying out one by one is installed. A hopper tank 122 that opens upward and stores a large number of medals is provided at the top of the hopper device 121. Inside the slot machine housing 120, a reel unit 203 including three reels is installed at a position where the game display unit 131 comes when the upper door 130U is closed. The reel unit 203 includes three reels (first reel to third reel) in which a plurality of types of symbols are arranged on the outer peripheral surface. The game display unit 131 is provided with an opening through which a player can see the symbols of each rotating reel of the reel unit 203. A power supply unit 205 is provided on the left side of the hopper device 121.

  As shown in FIG. 2, the medal (coin) selector 1 is attached to the lower surface of the lower door 130L at the lower portion of the medal slot 132 on the upper surface of the lower door 130L. This medal selector 1 rolls the medal toward the hopper device 121 while detecting the passage of the medal inserted from the medal insertion slot 132, and has a different diameter medal or iron or iron whose outer diameter is different from the predetermined dimension. This is an apparatus for selecting and removing illegal medals made of an alloy and selecting and eliminating a predetermined number or more of medals that can be inserted per game.

  Further, as shown in FIG. 2, a lead-out path 136 that covers the lower side of the medal selector 1 and communicates with the payout port at the lower part of the lower door 130L is provided. The medals distributed by the medal selector 1 are returned to the player from the payout port via the derivation path 136.

  The main board 10 is attached to the inside of the slot machine housing 120 and below the reel unit 203. The main board 10 is provided with a setting change switch SSW for performing an internal setting relating to a game (for example, which of a plurality of lottery tables is used). The sub-board 20 is attached to the lower center of the back surface of the upper door 130U.

  A low-frequency speaker SPL is provided in the upper left corner of the slot machine housing 120, and two speakers SP that cover a standard sound range are provided below the lower door 130L.

<Electric structure of gaming machine>
FIG. 3 shows a functional block diagram of the slot machine 100.

  In this figure, the display about the power supply system is omitted. Although not shown in FIG. 3, the slot machine includes a power supply unit (power supply unit 205 in FIG. 2) for generating a DC power supply (+5 V or the like) from a commercial power supply (AC 100 V).

<Electric structure of gaming machine: Overall>
The slot machine 100 includes a main substrate 10 and a sub substrate 20 that operates in response to a command from the main substrate 10 as main processing devices. Substrates including the main substrate 10 and the sub-substrate are accommodated inside the case so that they cannot be contacted from the outside, and are subjected to a sealing process so that traces remain when these substrates are removed. Specifically, the main board 10 and the sub board 20 are integrally attached by caulking, and are covered by an integral case that covers the entire main board 10 and the sub board 20.

  The main board 10 is used for performing an internal lottery in response to the player's operation, and for performing processing (game processing) such as rotation / stop of the spinning cylinder and payout of medals. The main board 10 includes a CPU that performs a control operation according to a preset program, a ROM that is a storage unit that stores the program, and a RAM that temporarily stores processing results and the like.

  The sub board 20 is for receiving a command signal from the main board 10 and notifying the result of the internal lottery and performing various effects. The sub-board 20 includes a CPU that performs a control operation in accordance with a preset program corresponding to the command signal, a ROM that is a storage unit that stores the program, and a RAM that temporarily stores processing results and the like. Only one command flows from the main board 10 to the sub board 20, and conversely, no command is issued from the sub board 20 to the main board 10. The sub-board 20 includes means for generating random numbers used for production.

  Hereinafter, the main board and the sub board will be described in detail.

<Electric structure of gaming machine: main board>
The main board 10 includes the bet switch BET, the start switch 134, the stop button 140, the reel (rotating cylinder) unit 203, the setting change switch SSW, the hopper driving unit 80, the hopper 81, and the number of medals paid out from the hopper 81. A medal detection unit 82 for counting (these constitute the hopper device 121 described above) is connected.

  Further, medal sensors S1 and S2 of the medal selector 1 are connected to the main board 10.

  The medal selector 1 is provided with medal sensors S1 and S2 for counting medals. The medal sensors S1 and S2 are attached to the downstream side (near the exit) of a medal passage (not shown) provided in the medal selector 1 (the upstream side of the medal passage communicates with the medal insertion port 132). The two medal sensors S1 and S2 are provided side by side at a predetermined interval along the medal traveling direction. The medal sensors S1 and S2 are, for example, photointerrupters that have a light emitting portion and a light receiving portion that face each other, are formed in a U-shaped cross section, and are positioned so that the detection optical axis faces the medal passage from above. . Each photo interrupter detects the passage of a medal sent without being blocked on the way. The reason why two photo interrupters are adjacent is not only to detect the number of medals but also to monitor whether or not the passage of medals is normal. That is, by providing two photo interrupters adjacent to each other, it is possible to detect the passing speed and passing direction of medals, thereby detecting not only the number of medals but also an illegal act moving in the reverse direction.

  The reel unit 203 includes three spinning cylinders 40a to 40c, stepping motors 155a to 155c that respectively rotate these, and spinning cylinder position detectors (index sensors) 159a to 159c that detect their positions, respectively (note that The stepping motors 155a to 155c may be simply referred to as a motor 155 or a motor).

  Based on the reference position signal detected by the index sensor 159 every time each of the rotating cylinders 40a to 40c makes one rotation, the rotating cylinder control means 1300 starts from the reference position (a frame specified by an index (not shown)) of the rotating cylinder 40. Is obtained (by counting the number of rotation steps of the rotation shaft of the step motor), the current rotation state of the drum 40 can be monitored. That is, the main substrate 10 can obtain the position of the rotating drum 40 when the stop button 140 is operated by obtaining the rotation angle from the reference position of the rotating drum 40.

  In the following description, reference numeral 40 is used to indicate any one or a plurality of spinning cylinders, and reference numerals 40a to 40c are used to separately indicate three spinning cylinders.

  The hopper driving unit 80 rotates an unillustrated rotating disk of the hopper 81 and performs an operation of paying out medals of the payout number instructed by the main board 10. The gaming machine includes a medal detection unit 82 that operates every time a medal is paid out, and the main board 10 receives a medal actually paid out from the hopper 81 based on an input signal from the medal detection unit 82. You can manage the number.

  The insertion accepting unit (insertion accepting means) 1050 receives the outputs of the medal sensors S1 and S2 of the medal selector 1, accepts the insertion of medals for each game, and based on the insertion of medals corresponding to the prescribed number of insertions. Then, a process of permitting the start operation of the first to third cylinders for the start switch 134 is performed. Note that the pressing operation of the start switch 134 is an opportunity to start the rotation of the first cylinder to the third cylinder, and is an opportunity to execute the internal lottery. Further, the prescribed number of throws may be set according to the game state, and the prescribed number of throws is set to 3 in the normal state, the bonus establishment state, and the bonus state.

  When medals are inserted, the inserted medals are set to the inserted state up to a specified number of insertions according to the gaming state. Alternatively, when the bet switch BET is pressed in a state where medals have been credited to the gaming machine, the credited medals are set to the inserted state by limiting the prescribed number of insertions according to the gaming state. The main board 10 controls whether or not to accept a medal. From the time when the start switch 134 is pressed and the rotation of each cylinder starts (game start time), when the three stop buttons 140 are pressed and the rotation of each cylinder stops (when the medal payout is completed when winning) (game) When the medal is not accepted (when it is not permitted), the medal sensor S1, S2 does not count the medal and is returned as it is. . Similarly, the main board 10 controls the validity / invalidity of the bet switch BET according to whether or not the medal insertion is accepted. In addition, the bet switch BET is valid from the end of the game to the start of the game, but during other periods (when pressing of the BET switch is not permitted), the bet switch BET is pressed. Even it is ignored.

  The main board 10 incorporates random number generating means 1100. The random number generation means 1100 is a means for generating a random number for lottery. The random value can be generated based on, for example, a count value of an increment counter (a counter that counts numerical values so as to circulate a predetermined count range). In this embodiment, the “random number value” is not only a value that is randomly generated in a mathematical sense, but even if the generation itself is regular, the acquisition timing and the like are irregular. Includes a value that can function as a random number.

  The internal lottery means 1200 performs an internal lottery in which the player determines whether or not the winning combination is based on a start signal from the start switch 134. That is, a lottery table selection process for selecting a lottery table (not shown) stored in a memory (not shown) of the main board 10, a random number determination process for determining the winning of a random number obtained from the random number generating means 1100, The lottery flag setting process for setting a flag to that effect when a big win or the like is won by the determination result is performed.

  In the lottery table selection process, a lottery table (not shown) stored in a storage unit (ROM) (not shown) is used to determine which lottery table is used for internal lottery. In the lottery table, for each of a plurality of random values (for example, 65536 random values from 0 to 65535), replay, small role (bell, cherry), regular bonus (RB: bonus), and big bonus (BB :), etc., are associated with each other. In addition, a normal state, a bonus establishment state, and a bonus state can be set as the gaming state, and a replay lottery state, a replay low probability state, and a replay high probability state can be set as replay lottery states.

  The lottery table selection process allows the contents of the lottery to be set within a predetermined range (the probability of winning can be increased or decreased), and the setting work is performed by the store in the hall where the gaming machine is installed. . The switch used in this setting operation is a setting change switch SSW.

  A normal gaming machine includes a plurality of (for example, six) lottery tables having different lottery probabilities such as BB, RB, and small roles in advance. In the lottery of gaming machines, one of the plurality of lottery tables is set, and the winning / losing determination by lottery is made based on the set lottery table. Changing a setting relating to which of a plurality of lottery tables is used is referred to as a setting change (hereinafter referred to as “setting change”).

  Conventionally, in a gaming machine such as a slot machine, when changing a setting value (usually 1 to 6), the door of the gaming machine is opened, and a setting change key is set as a key switch of a setting change switch SSW provided on the main board 10. With the key inserted and the key switch turned on, the game machine is turned on so that the setting can be changed. Every time the setting change button (push button) of the setting change switch SSW is pressed, 7 segments The set value displayed on the display unit is incremented to cyclically change the values from 1 to 6, and the desired set value is operated by operating the start switch when the desired set value is displayed on the display unit. Is confirmed.

  In the random number determination process, on the basis of the start signal from the start switch 134, a random number value (lottery random number) is acquired for each game from random number generation means (not shown), and the lottery table is referred to for the acquired random number value. To determine whether or not they have won the role.

  In the lottery flag setting process, the lottery flag of the winning combination determined to be won based on the result of the random number determination process is changed from the non-winning state (first flag state, off state) to the winning state (second flag state, on Status). When two or more types of winning combinations are won, a lottery flag corresponding to each of the two or more types of winning winning combinations is set to the winning state. The lottery flag setting information is stored in storage means (RAM).

  A lottery flag (possible carryover flag) that can carry over the winning state for the next game until winning, and a lottery flag that is reset to the non-winning state without bringing the winning state to the next game regardless of winning Carry-over impossible flag) may be provided. In this case, there are a regular bonus (RB) and a big bonus (BB) as a combination to which the former carry-over possible flag is associated, and other combinations (for example, small role, replay) correspond to the latter carry-over impossible flag. It is attached. In other words, in the lottery flag setting process, when a regular bonus is won by internal lottery, the winning state of the regular bonus lottery flag is carried over until the regular bonus is won, and when a big bonus is won by internal lottery, A process of carrying over the winning state of the flag until the big bonus is won is performed. At this time, the main board 10 determines whether or not a role other than the regular bonus and the big bonus (small role and replay) is used even in a game in which the winning state of the regular bonus or big bonus lottery flag is carried over by the internal lottery function. An internal lottery is performed. In other words, in the lottery flag setting process, in a game in which the winning state of the regular bonus lottery flag is carried over, if a small role or replay is won in the internal lottery, the regular bonus lottery flag and the internal lottery already won In a game in which the lottery flags corresponding to two or more types of winning combinations or replay lottery flags won in the win state are set to the winning state and the winning state of the big bonus lottery flag is carried over, it is small in the internal lottery When a winning combination or replay is won, a lottery flag corresponding to two or more kinds of winning combinations including a big bonus lottery flag that has already been won and a small bonus or replay lottery flag that has been won in an internal lottery is set to a winning state. Set.

  The spinning cylinder control means 1300 rotates the first to third cylinders by a stepping motor based on a start signal generated by the player pressing the start switch 134 (rotation start operation), and the first cylinder -Depressing (stopping) the three stop buttons 140 corresponding to the rotating cylinders in a state where the rotation speed of the third cylinder reaches a predetermined speed (about 80 rpm: a rotational speed of about 80 rotations per minute). In addition to performing control to permit the operation), control is performed to stop the first to third cylinders driven to rotate by the stepping motor in accordance with the lottery flag setting state (internal lottery result).

  In addition, when the player presses the three stop buttons 140 in a state where the pressing operation (stop operation) with respect to the three stop buttons 140 is permitted (validated), Based on the signal, the supply of the drive pulse (motor drive signal) to the stepping motor of the reel unit 203 is stopped, thereby controlling each of the first to third drums.

  That is, each time the three stop buttons 140 are pressed, the spinning cylinder control means 1300 determines the stopping position of the spinning cylinder corresponding to the pressed button among the first to third cylinders. Thus, control is performed to stop the spinning cylinder at the determined stop position. Specifically, referring to a stop control table (not shown) stored in the storage means (ROM), the first time corresponding to the pressing timing, pressing order, etc. of the three stop buttons (mode of stop operation) A stop position of the cylinder to the third cylinder is determined, and control is performed to stop the first cylinder to the third cylinder at the determined stop position.

  Here, in the stop control table, the positions of the first cylinder to the third cylinder (pressing detection position) at the time when the stop button 140 is operated, and the actual stop positions (or pressing detection of the first cylinder to the third cylinder). Correspondence with the number of sliding frames from the position) is set. The number of sliding symbols is a symbol that passes through the reference position between the operation of the stop button 140 and the rotation stop of the corresponding rotating cylinder when a specific symbol that can be visually recognized from the game display unit at the time of stopping the rotating drum is used as the reference position. The number of Since the turning cylinder control means 1300 stops each turning cylinder within 190 ms from the operation of each stop button 140, the number of sliding frames is in the range of 0 to 4 (however, 80 revolutions / minute, (In the condition of the number of symbols = 21). Depending on the setting state of the lottery flag, a stop control table for determining the stop positions of the first cylinder to the third cylinder may be prepared.

  As described above, the spinning cylinder control unit 1300 is based on the reference position signal (the frame detected by the reel index) of the spinning cylinder based on the reference position signal detected by the index sensor 159 every time the rotating cylinder makes one rotation. By obtaining the rotation angle (the number of rotation steps of the rotation shaft of the step motor), the current rotation state of the rotating drum can be monitored. That is, the main board 10 can obtain the position of the rotating cylinder when the stop button 140 is operated by obtaining the rotation angle from the reference position of the rotating cylinder.

  The spinning cylinder control unit 1300 performs so-called pull-in processing and kicking processing as control for stopping the spinning cylinder. The pull-in process is a control for stopping the spinning cylinder so that the symbol corresponding to the combination whose lottery flag is set to the winning state is stopped on a valid winning determination line (so that the winning combination can be won). It is processing. On the other hand, the kicking process means that the symbol corresponding to the combination for which the lottery flag is set to the non-winning state does not stop on a valid winning determination line (so that a non-winning combination cannot be won) Is a control process for stopping the process. That is, in the gaming machine of the present embodiment, the lottery flag setting state, the stop button 140 pressing timing, the pressing order, and the stop position of the spinning cylinder that has already stopped (in the display pattern) in order to realize the pull-in processing and kicking processing. The stop control table is set so that the stop position of each cylinder changes according to the type). In this way, the main board 10 can stop the symbol of the combination for which the lottery flag is set to the winning state in a winning form, while the symbol of the combination for which the lottery flag is set to the non-winning state is in the winning form. Control is performed to stop the first to third cylinders so as not to stop.

  In the gaming machine of the present embodiment, the first to third drums are controlled to stop the rotating drum corresponding to the pressed stop button within 190 ms from the time when the stop button 140 is pressed. Is set to That is, in the stop control table for determining the stop position of each rotating cylinder, the number of frames required from when the stop button 140 is pressed until each cylinder stops is in the range of 0 to 4 frames (predetermined pull-in range). Is set in

  The winning determination means 1400 performs a process of determining whether or not a winning combination has been won based on the stopping modes of the first to third cylinders. Specifically, referring to the winning determination table stored in the storage means (ROM), the symbol combination displayed on the winning determination line when all of the first to third cylinders are stopped. It is determined whether or not this is a predetermined winning combination form.

  The winning determination means 1400 executes a winning process based on the determination result. As a process at the time of winning a prize, for example, when a small role wins, the hopper 81 is driven to perform a medal payout control process, or a credit is increased (a predetermined maximum number is increased to 50, for example, When the replay is won, a replay process is performed. When a big bonus or a regular bonus is won, a game state transition control process for shifting the game state is performed.

  The payout control means 1500 performs payout control processing relating to the payout of medals according to the game result. Specifically, when a small combination wins, the number of medals to be paid out in the game is determined based on a payout predetermined for each combination, and the medals corresponding to the determined number of payouts are determined by the hopper driving unit 80. Then, the hopper 81 is driven to pay out. At this time, a current flows through a motor (not shown) built in the hopper 81.

  When medal credits (internal storage) are permitted, instead of actually paying out medals by the hopper 81, the number of credits stored in a credit storage area (not shown) of the storage means (RAM) (not shown) A credit addition process for adding the number of payouts to the number of credited medals is performed to virtually pay out medals.

  When the replay is won, the replay processing means 1600 performs a replay process (regame process) for setting the same preparatory state as the previous game without requiring insertion of medals owned by the player for the next game. When a replay wins, an automatic insertion process is performed in which the same number of medals as the previous game is automatically set to the insertion state without using the player's own medals (including credit medals). The game machine is set in a state of waiting for a rotation start operation (pressing operation of the start switch 134 by the player) in the next game in a state where the same winning determination line as the previous game is validated.

  The replay processing unit 1600 may perform control to change the winning probability of replay in the internal lottery under a predetermined condition. For example, when a predetermined turn is displayed when the spinning cylinder is stopped by operating the stop button 140, the winning probability of replay varies. The replay lottery states include a replay no lottery state in which replay is excluded from the internal lottery, a replay low probability state in which the replay winning probability is set to about 1 / 7.3, and a replay winning probability of about 1 / A plurality of lottery states such as a high replay probability state set to 6 can be set.

  The error processing unit 1700 determines an error of the gaming machine based on the outputs of a door opening / closing detection sensor (not shown), the medal sensors S1 and S2, and the medal detection unit 82, and notifies that when it determines that there is an error. To a predetermined state (for example, a state in which no operation is accepted).

  A door open / close detection sensor (not shown) is a sensor that detects that the front door 130 (the upper door 130U and the lower door 130L) is closed, and is an electrical switch such as a micro switch or a contact. When the front door 130 (upper door 130U, lower door 130L) is closed, the switch is turned on (or turned off) by the action part of the switch contacting the back side of the front door 130 (upper door 130U, lower door 130L). When the front door 130 (upper door 130U, lower door 130L) is opened, the action part is separated and turned off (or turned on). The door opening / closing detection sensor may be an optical sensor such as a photo interrupter. The medal sensors S1 and S2 and the medal detection unit 82 have been described above.

Specifically, the error processing unit 1700 performs the following operation.
When an opening of the front door 130 (upper door 130U, lower door 130L) is detected based on the output of a door opening / closing detection sensor (not shown), error processing is performed.
-Based on the outputs of the medal sensors S1 and S2, the reverse flow of the medals (the detection order of the sensors S1 and S2 is reversed), the medal retention (the detection times of the sensors S1 and S2 are longer than a predetermined threshold) When error is detected, error processing is performed.
Based on the output of the medal detection unit 82, the medal clogging (the detection time of the medal detection unit 82 is longer than a predetermined threshold), hopper empty (the medal detection unit despite operating the hopper driving unit 80) When 82 detects no medal), error processing is performed.

  When the error processing unit 1700 determines that an error has occurred as described above, the error processing unit 1700 notifies the fact and sets the gaming machine to a predetermined state (error state). This state is canceled by a reset switch (not shown). The reset switch is provided on the panel of the power supply unit 205, for example.

  There are also errors that occur in the sub-board 20. Although this error does not result in an inoperable state, the liquid crystal display device or the like can notify that an error has occurred due to the processing of the sub-board 20 itself. The error occurs, for example, when an invalid command is received (including when the encrypted command cannot be correctly decrypted), and the error is canceled by the reset switch (from the main board 10 to the sub board 20). Reset command).

  Further, the main board 10 may perform control to shift the gaming state between the normal state, the bonus establishment state, and the bonus state (gaming state transition control function). As the game condition transition condition, one condition may be defined, or a plurality of conditions may be defined. When a plurality of conditions are established, transitioning the gaming state to another gaming state based on the fact that one of the plurality of conditions is satisfied or all of the plurality of conditions are satisfied Can do.

  The normal state is a game state corresponding to the initial state among a plurality of types of game states, and a transition from the normal state to the bonus establishment state is possible. The bonus establishment state is a gaming state that shifts when a big bonus or a regular bonus is won in the internal lottery. In the bonus establishment state, when the big bonus is won in the internal lottery in the normal state, the lottery flag corresponding to the big bonus is maintained in the winning state until the big bonus is won, and the regular bonus is won in the internal lottery in the normal state Until the regular bonus is won, the lottery flag corresponding to the regular bonus is maintained in the winning state. In the bonus state, it is determined whether or not the end condition is satisfied based on the total number of medals paid out by the bonus game, and medals exceeding a predetermined payout limit number are paid out according to the type of bonus won. The bonus state is terminated and the gaming state is returned to the normal state.

  The reel unit 203 includes three spinning cylinders 40a to 40c, and one stepping motor 155a to 155c is attached to each of the three spinning cylinders 40a to 40c. The stepping motor 155 includes a gear-shaped iron core or permanent magnet as a rotor (rotor), a plurality of windings (coils) as a stator (stator), and is rotated by switching windings through which current flows. It is. That is, a current is passed through the windings of the stator to generate a magnetic force, and the rotor is rotated by attracting the rotor. Since the rotation axis can be stopped at a specified angle, it is used to drive the rotation of the slot machine. A plurality of windings constitute one phase. As the number of phases, for example, there are two (two phases), four (four phases), and five (five phases).

  The stepping motor can change its characteristics (excitation mode changes) by changing the way of applying current to the windings of each phase. The two-phase type is as follows.

• Single-phase excitation Always allow current to flow through only one phase of the winding. Positioning accuracy is good.

・ Two-phase excitation
Current flows in two phases. An output torque approximately twice that of single-phase excitation can be obtained. The positioning accuracy is good and the stationary torque is large when stopped, so that the stop position can be held reliably.

・ One-two-phase excitation
A current is passed by alternately switching between one phase and two phases. Since the step angle can be halved in the case of one-phase excitation and two-phase excitation, smooth rotation can be obtained.

  Note that “driving” a stepping motor includes rotating the motor by the above-described excitation and exciting each phase in order to stop at a desired position and hold the position.

  Regarding driving of the spinning cylinders 40a to 40c of the slot machine, for example, a four-phase stepping motor having a basic step angle of 1.43 degrees is used, and one-two-phase excitation is adopted as a pulse output method.

  10CG is a command transmitter that transmits a command to be sent to the sub-board 20. This command includes a command related to winning combination information, a command related to information on the number of inserted medals and the number of credits (stored number). Specifically, the command transmission unit 10CG is realized by the CPU executing a program written in advance in a ROM mounted on the main board 10.

<Game processing on the main board>
Next, the game processing in the main board 10 will be described with reference to FIG.
Generally, in a gaming machine, one game is started from the insertion of medals (insertion of credits) until the end of payout (or until the increase in the number of credits is completed). There is a rule that it is not possible to proceed to the next game until one game is finished.

  First, when a prescribed number of medals are inserted, the start switch 134 is activated, and the processing of FIG. 4 is started.

  In step S1, the start switch 134 is turned on by operating the start switch 134. Then, the process proceeds to the next step S2.

  In step S2, a lottery process is performed by the main board 10. Then, the process proceeds to the next step S3.

  In step S3, the rotation of the first reel to the third reel starts. Then, the process proceeds to the next step S4.

  In step S4, when the stop button 140 is operated, the stop button 140 is turned ON. Then, the process proceeds to the next step S5.

  In step S5, rotation stop processing is performed on the reel corresponding to the pressed stop button 140 among the first to third reels. Then, the process proceeds to the next step S6.

  In step S6, it is determined whether or not the operation of the stop button 140 corresponding to the three reels has been performed. If it is determined that all three stop buttons 140 corresponding to the three reels have been operated, the process proceeds to the next step S7.

  In step S7, it is determined whether or not the symbol combinations corresponding to the lottery flag are aligned on the effective winning line while the lottery flag is established, that is, whether or not the winning is confirmed. If it is determined that the winning is confirmed, the process proceeds to the next step S8. If the winning is not confirmed, no medals are paid out even if the lottery flag is established.

  In step S8, medals corresponding to the symbol combinations arranged on the winning determination line are paid out.

  The process from the insertion of the medal to the completion of the execution of step S8 is one game. When the standby process in step S8 ends, the process returns to the beginning of the flowchart. In other words, the next game is possible (transition to the next game).

<Electric structure of gaming machine: Sub-board>
Connected to the sub-board 20 are liquid crystal panels LCD1 and LCD2, LEDs 202B, 202U and 202L, speaker SP, bass speaker SPL, solenoid SN, motors MU and ML, sensors SENU and SENL, and switch SW. The LEDs 202B, 202L, and 202U incorporate a latch that acquires and holds data and an LED that is an electrical decoration (the LED may be provided outside the substrate). These components are controlled by the sub-board 20, and are an output device that produces effects by video, light, sound, and movement of the movable body, or an input device or player for detecting the movement of the movable body. It is an input device which receives operation by.

  Although not shown, the model-specific block BB and the lower door block BL have a video controller (VDC) for controlling the liquid crystal panel LCD2, a speaker SP, and a sound for generating sound by driving the speaker SP. A drive circuit for driving the controller, solenoid SN, motors MU and ML is incorporated.

  The components such as the liquid crystal panel described above, except for the bass speaker SPL, correspond to the model-specific block BB and the upper door block BU and the lower door 130L provided corresponding to the upper door 130U built in the slot machine housing 120. The lower door block BL is provided in a distinguishable manner.

  In the example of FIG. 3, the model-specific block BB includes a solenoid SN, a speaker SP, and an LED 202B, and the upper door block BU includes a liquid crystal panel LCD1, an LED 202U, a motor MU, and a sensor SENU that detects the operation of the movable body. The lower door block BL includes a liquid crystal panel LCD2, a speaker SP, an LED 202L, a motor ML, a sensor SENL that detects the operation of the movable body by the motor ML, and a switch SW such as a cursor key. The entire liquid crystal panel LCD2 is configured to be slightly movable back and forth by the motor ML, and the player may be able to perform an operation of pushing the liquid crystal panel LCD2 in a state where the liquid crystal panel LCD2 is moved forward. In this case, the switch SW of the lower door block BL includes a switch for detecting depression of the liquid crystal panel LCD2.

<Electric structure of gaming machine: Outline of initial operation of CPU of sub-board>
When the power of the gaming machine is turned on, the CPU of the sub-board starts operation (when reset, the operation resumes and operates in the same way as when the power is turned on).

  When the power is turned on (reset), the start address as the initial value of the program counter and the initial value of the stack pointer are extracted from a predetermined table (exception processing vector table) and stored. The program counter is a counter indicating the position of the program to be executed. The stack is a storage area (register) used to temporarily hold information, and the stack pointer is the last address (latest information in the stack of addresses (a series of information indicating the position of a series of held information)). Register).

  Next, the vector base register is initialized to a predetermined value (H'00000000), the interrupt mask level bits (I3 to I0) of the status register are set to a predetermined value (B'1111), the BO bit and CS bit are set to 0, respectively. Turn into. It also initializes the interrupt controller. The vector base register is one of the control registers and is used as a base address (program jump destination) of an exception processing vector area including an interrupt. When an exception or interrupt occurs, it is referenced as the branch destination base address. The status register is one of the control registers, and its contents indicate the state of the CPU. The interrupt controller is for determining the priority order of interrupts.

  The mask level bit sets the priority level of the interrupt. Some interrupts are always enabled, but some interrupts are not always enabled and only want to be enabled in certain situations. Therefore, there is an interrupt mask function that disables interrupt acceptance for each interrupt factor. The mask level bit is used for this purpose. Interrupts that can be disabled with an interrupt mask are called maskable interrupts, and interrupts that cannot be disabled with an interrupt mask are called non-maskable interrupts (NMI). The priority is set to 15 by setting the interrupt mask level bits (I3 to I0) of the status register to a predetermined value (B'1111). Even if an interrupt occurs, the interrupt is not accepted unless its priority level exceeds the mask level of 15. Therefore, interrupts are substantially prohibited at priority level 15 immediately after reset (NMI interrupt priority level is 16, which is accepted as an exception). The BO bit is a bit indicating that a predetermined register has overflowed, and the CS bit is a bit indicating that an overflow has occurred in a predetermined operation. A normal state is obtained by setting them to 0. The IBNR of the interrupt controller is a bank number register.

  The initial operation described above is provided in advance on the CPU side and is not described by a program.

  Based on the initial value of the program counter extracted from the exception processing vector table, the program branches to the start address and starts executing the program.

  In the case of an interrupt, refer to the stack pointer to save the program counter and status register in the stack area, fetch the address corresponding to the interrupt from the exception processing vector table, branch to that address, and start program execution To do. Thereafter, the processing state becomes a program execution state in which the CPU sequentially executes the programs.

  The program is executed by reading an instruction from the start address. At this time, a memory (ROM, RAM) storing a program for initial startup is selected (when the start address is read, CS0 described later is set). Enabled). This memory is an IC provided separately from the CPU. In addition to this memory, a similar memory may be provided. In this case, a chip select (CS) is used to distinguish a plurality of memories. Programs and data can be read from memory with CS enabled. CS is generated by a bus state controller (BSC) built in the CPU. There are a plurality of outputs, and they are distinguished as CS0, CS1, CS2,.

  Immediately after the start of the CPU operation, the setting of the CS space to which the external device is connected is valid only for the CSO on which the device connection for program activation is assumed, and the other CS spaces are invalidated. Therefore, the memory connected to the CSO stores programs and data for enabling each CS space and performing various settings according to the relationship with the device connected to the space other than the CPU CSO. The CPU reads and executes the program and data to validate the memory connected to the other CS1, CS2,. The CSO space access setting at the time of initial start-up is a setting in which the weight value and the like are the maximum and the access width and the like are the minimum so that any memory can be connected to CS0. This is a setting value with a high possibility that the minimum operation is guaranteed, so that even if the memory connected to CS0 has a low specification, reading and writing can be normally performed.

<Electric structure of gaming machine: command transmission from main board to sub board>
The sub-board 20 receives a command from the main board 10 and performs processing such as rendering according to the command. Only one command flows from the main board 10 to the sub board 20, and conversely, no command is issued from the sub board 20 to the main board 10.

  The sub board 20 generates a command (display command, drawing command) for displaying a predetermined screen on the liquid crystal panels LCD1 and LCD2, for example, in accordance with a command from the main board 10. For example, when performing an effect by animation or the like, a large number of commands are continuously transmitted one after another.

  In FIG. 3, 20 CR is a command receiving unit that receives a command received from the main board 10. Specifically, the command receiving unit 20CR is realized by the CPU executing a program written in advance in a ROM mounted on the sub-board 20.

  As the above-mentioned command, there is a command for performing an effect suggesting the winning contents by the software on the sub-board 20 side. For example, as shown in the following AT, suggestions for obtaining a ball are displayed on a display device such as a liquid crystal display device in order to provide convenience (assist) for the player's operation. The suggestion is not always issued, but in specific cases. Note that the present invention is not limited to a mode in which the sub board displays AT (notifies) based on a command from the main board. For example, the main board may display (notify) the AT by a display (notification means) under the control of the main board. The following description also applies to such a form.

  The gaming machine includes an effect display device including a liquid crystal display device, a speaker, a display lamp, and the like. This effect display device is controlled by the sub-board 20, and informs the player of a prize or the like, or a so-called assist time (AT) in which a specific small role is awarded during a certain game as a stop button pressing mode. It is intended to teach the user with some action. (Assist Time (AT): Even if a specific small role is won, the player will not be paid out unless the symbol combination corresponding to this small role is aligned on the winning judgment line. , After the big bonus is over (or at the time of winning) or at any other opportunity, the assist time will be drawn in order to align the symbol combination corresponding to a specific small role on the winning judgment line for a certain game (That tells the player about the stop operation with some action)

  The command receiving unit 20CR receives a command received from the main board 10. For example, a command received as serial data is input to a serial-parallel converter (shift register), and is output every certain data (for example, 8 bits). The output data is transferred to the CPU of the sub-board 20 as a command, and is interpreted and executed.

<Electric structure of gaming machine: Connection between sub-board and components such as slave board / LED>
The above-described gaming machine is separated into a plurality of blocks such as an upper door block BU and a lower door block BL, and can be independently incorporated or removed (separated housing). Manufacturing, shipment, and installation may be performed in a state where some blocks, for example, the lower door block BL are not incorporated.

  FIG. 5 is a block diagram showing connections of sub-boards, slave boards (relay boards), rendering devices such as LEDs, solenoids, motors, and sensors (photosensors, switches, etc.) according to the embodiment of the invention. FIG. 5 shows the connection system related to the production device and the slave board in the block diagram of FIG. At least the harnesses HBU and HBL connecting the sub board 20 and the slave boards 206BU and 206BL specify the data line through which the digital signal propagates and the timing for acquiring (latching) the digital signal, as shown in the lower left of FIG. And a clock line through which a clock signal to be transmitted propagates, and a communication system between them is clock synchronous serial communication. In FIG. 5, the same or corresponding parts as those in FIG.

  Of the elements shown in FIG. 5, the slave boards 206BU and 206BL are implemented by hardware such as an IC. The I2C transmission / reception processing unit 207 and the transmission / reception processing unit 208 of the slave board 206BB are stored in a ROM mounted thereon. This is realized by the CPU executing a program written in advance. The transmission processing units 209T and 210T and the reception processing units 209R and 210R are realized by either hardware such as an IC or software.

  In FIG. 5, the sub-board 20 is included in the upper door block BU, but this is an example. For example, the sub-board 20 may be included in the lower door block BL, or may be provided separately from the model-specific block BB, the upper door block BU, and the lower door block BL.

  In the gaming machine according to the embodiment of the present invention, I2C (Inter-Integrated Circuit) or clock synchronization is used as a control communication method from the sub-board 20 to a slave board (relay board) that controls effect devices such as accessories and electrical decorations. Uses serial communication. As the number of controlled objects / devices increases, the sub board connects to the slave board via serial communication, and each slave board performs serial-parallel conversion (serial-parallel conversion). Each slave board is connected to a device such as an accessory or illumination.

  That is, in the gaming machine according to the embodiment of the invention, I2C is used as the communication method between the sub-board 20 and the model-specific block BB. Since the configuration of the electrical member of the model-specific block BB changes for each model, versatile bidirectional communication is adopted. The communication system between the sub-board 20 and the upper door block BU uses synchronous serial. Since the reel unit 203 is to be replaced at the same time when the reel unit 203 is replaced, a harness HBU dedicated to the upper door block BU is provided. The communication system between the sub-board 20 and the lower door block BL uses synchronous serial. Since it is a remaining common part, a harness HBL dedicated to the lower door block BL is provided.

  BB is a model-specific block unique to each model of gaming machine. BL is a lower door block (first block) used in common for each housing. BU is a replaceable upper door block (second block).

  The model specific block BB, the lower door block BL, and the upper door block BU include a slave board (model specific relay board) 206BB, a slave board (first relay board) 206BL, and a slave board (second relay board) 206BU, respectively. The slave board 206BB has a built-in CPU and is more flexible and sophisticated than the slave boards 206BL and BU (for example, an address is determined in advance for the slave board 206BB, and it is determined whether the received message is addressed to itself. Can be requested to the sub-board 20 when transmitting data). The slave boards 206BL and BU have a predetermined communication procedure with the other party (transmission processing units 209T and 210T, reception processing parts 209R and 210R of the sub board 20), and need not be flexible. . For this reason, the slave substrates 206BL and BU can be configured by a dedicated IC.

  J11 is a model-specific input / output terminal of the sub-board 20. This includes one data line and one clock line (same for other terminals).

  J21 and J22 are first output terminals, and J31 is a first input terminal. J41 and J42 are second output terminals, and J51 is a second input terminal.

  The harness (model-specific harness) HBB connects the model-specific input / output terminal J11 to the slave substrate 206BB.

  The harness HBL connects the first output terminals J21 and J22 and the first input terminal J31 to the slave substrate 206BL.

  The harness HBU connects the second output ends J41 and J42 and the second input end J51 to the slave substrate 206BU.

  The transmission processing unit 209T generates a serial signal to be transmitted from the first output terminals J21 and J21 to the slave substrate 206BL.

  The reception processing unit 209R converts the serial signal received from the slave substrate 206BL at the first input terminal J31 into a parallel signal. The converted parallel signal is subjected to predetermined processing by the sub-board 20.

  The transmission processing unit 210T generates a serial signal to be transmitted from the second output terminals J41 and J42 to the slave substrate 206BU.

  The reception processing unit 210R converts the serial signal received from the slave substrate 206BU at the second input terminal J51 into a parallel signal. The converted parallel signal is subjected to predetermined processing by the sub-board 20.

  The transmission / reception processing unit 208 of the slave substrate 206BB performs reception processing and transmission processing according to the address from the I2C transmission / reception processing unit 207. Although only one slave board 206BB is shown in FIG. 5, a plurality of slave boards 206BB can be connected to the same harness HBB (including signal lines branched from now). An address is used to identify the slave substrate 206BB.

  FIG. 6 is an explanatory diagram of the slave substrates 206BB, 206BL, and 206BU.

  The slave boards 206BL, 206BU, and 206BB that drive the LEDs include an LED driver IC01. The LED driver IC01 receives a serial signal and a clock from the sub-board 20, acquires data from the serial signal based on the clock, and based on a decoding result of the data, connects the plurality of connected LEDs 202L, 202U, 202B in a predetermined pattern. Blink. For example, a specific LED is turned on, and the duty ratio is set to a predetermined value to adjust the luminance.

  The slave boards 206BL and 206BU for driving the motor are provided with a motor control circuit IC02. The motor control circuit IC02 receives the serial signal and clock from the sub-board 20, acquires data from the serial signal based on the clock, and excites the connected motor windings in a predetermined pattern based on the decoding result of the data. . For example, the winding is sequentially excited to rotate the motor, and the rotation speed is adjusted by changing the excitation frequency. The output of the motor control circuit IC02 is connected to a motor driver DRV for flowing a current necessary for driving the motor through the windings.

  Slave boards 206BL and 206BU including sensors (switches) include a parallel-serial converter IC3 for converting input signals of a plurality of sensors from parallel to serial. The parallel-serial converter IC3 receives a clock from the sub-board 20. The parallel-serial converter IC3 takes in the outputs of a plurality of sensors at predetermined intervals, converts the sensor data into serial signals based on the clock, and sends them to the sub-board 20. The serial data is received by the reception processing units 209R and 210R of the sub-board 20, and is subjected to serial-parallel conversion and transferred to the CPU of the sub-board 20.

<Initial setting during program execution: Disabling interrupts>
The CPU starts executing the program when the reset is released after the power is turned on. However, as described in <Electric structure of gaming machine: Outline of initial operation of CPU of sub board> Interrupt is disabled. In this state, a predetermined program (program A in FIG. 7, hereinafter sometimes referred to as “start program”) is executed first. This start program is stored at an address set by the initial operation of the CPU, and is normally executed only when reset is released.

  However, it is conceivable to jump to the start program address due to factors such as noise. If the start program is executed at the time of reset release, the interrupt is disabled at the time of execution, but if the jump is exceptionally jumped to the address of the start program, the CPU is not performing the initial operation and the interrupt is in the enabled state. is there. When processing is executed with the interrupt enabled, there is a high possibility that the restart process by the start program will not be performed normally. When an interrupt occurs, the CPU refers to the stack pointer, saves the program counter and status register to the stack area, retrieves the start address corresponding to the interrupt from a predetermined table, branches to that address, and executes the program. However, during the initial setting, the initial setting for executing the branch destination program is not performed, and therefore, normal operation may not be performed. For example, if the start program is executed without resetting for some reason, such as cheating, the cheating person gives an interrupt signal to the CPU to perform interrupt processing, which is convenient for himself It is also conceivable to perform operations (setting value change, winning flag setting, table rewriting, etc.). There is no problem because interrupts are prohibited after reset, but it is a problem when the start program is started illegally.

  In order to avoid such a situation, in the embodiment of the invention, in a gaming machine including a CPU that performs a predetermined initial operation as an operation of the CPU itself at the time of reset release and invalidates the interrupt, even on the start program side (for example, after reset) (In the first process of (1) and the execution of an unintended start program), the interrupt is invalidated and the process is executed thereon.

  FIG. 7 is an explanatory diagram of the execution of the program by the CPU according to the embodiment of the invention.

  Upon receiving the power-on reset signal RST (low level signal) at the power-on reset terminal, the CPU performs a predetermined initial setting INI (the initial setting by the CPU itself, the initial setting INI of the CPU is schematically shown in FIG. Shown as one unit). The internal state of the CPU and all the registers of the built-in peripheral modules are initialized by the initial setting INI by the CPU itself. In the initial setting INI by the CPU itself, the CPU operates as follows.

  1. The initial value (start address) of the program counter (PC) is fetched from the exception processing vector table.

  2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.

  3. Clears the vector base register (VBR) to H'00000000, initializes the interrupt mask level bits (I3 to I0) of the status register (SR) to H'F (B'1111), and initializes the BO and CS bits to 0 To do. It also initializes the interrupt controller (INTC). By setting in this way, interrupts are prohibited.

  4). The values fetched from the exception vector table are set in the program counter (PC) and stack pointer (SP), respectively, and program execution is started. In FIG. 7, the program A jumps to the top address 0000.

  The program counter is a counter indicating the position of the program to be executed.

  The exception processing vector table is a table that stores values set in the program counter and the stack pointer in exception processing such as at reset. The contents of the exception processing vector table are preset.

  The stack is a storage area (register) used to temporarily hold information, and the stack pointer is a register that points to the last address in the stack of addresses.

  The vector base register is one of the control registers and is used as a base address (program jump destination) of an exception processing vector area including an interrupt. When an exception or interrupt occurs, it is referenced as the branch destination base address.

  The status register is one of the control registers, and its contents indicate the state of the CPU.

  The interrupt controller is for determining the priority order of interrupts.

  The mask level bit sets the priority level of the interrupt. Some interrupts are always enabled, but some interrupts are not always enabled and only want to be enabled in certain situations. Therefore, there is an interrupt mask function that disables interrupt acceptance for each interrupt factor. The mask level bit is used for this purpose. Interrupts that can be disabled with an interrupt mask are called maskable interrupts, and interrupts that cannot be disabled with an interrupt mask are called non-maskable interrupts (NMI). The priority is set to 15 by setting the interrupt mask level bits (I3 to I0) of the status register to a predetermined value (B'1111). Even if an interrupt occurs, the interrupt is not accepted unless its priority level exceeds the mask level of 15. Therefore, interrupts are substantially prohibited at priority level 15 immediately after reset (NMI interrupt priority level is 16, which is accepted as an exception).

  The BO bit is a bit indicating that a predetermined register has overflowed, and the CS bit is a bit indicating that an overflow has occurred in a predetermined operation. A normal state is obtained by setting them to 0.

  Initializing the interrupt controller (INTC) prevents interrupts from being accepted exceptionally.

  In FIG. 7, it is assumed that the program counter is set to, for example, 0000 by the initial setting INI by the CPU itself (an arrow pointing upward from the CPU). In FIG. 7, it is assumed that there is a case where it jumps to 0000 unintentionally (an arrow from the top of ROM to the bottom left).

  Programs A, B, C,... Are stored in a storage unit (ROM). Program A (symbol Program A in FIG. 7) is a program (start program) that is executed first after reset. In FIG. 7, the head address is 0000. Programs B, C,... Are arbitrary programs such as production programs.

  The program A (start program) includes an initial setting program P-INI that performs processing similar to the initial operation performed by the CPU. The instruction (initial setting instruction) of the initial setting program P-INI performs initial setting of registers that may affect the execution of programs A, B, C,... (At least program A). For example, the following processing is performed.

  a. Set the start address (H'00000000) of the exception vector table in the vector base register (VBR).

  b. Set all interrupt mask level bits (I3 to I0) in the status register (SR) (H'F (B'1111)) (interrupt disabled state).

  c. Initialize the interrupt controller (INTC).

  After the above processing, programs A, B, C,... Are executed.

  By including a process for performing a predetermined initial setting (at least b) in the program A (start program) executed by reset, even if the start program is started unintentionally due to factors such as noise, The process can be performed normally. The validity of starting program execution is maintained.

  If there is no initial setting P-INI in the start program, when the start program is started unintentionally, the process is interrupted by an interrupt, and the result of the start program execution may not be normal.

  When the program A (start program) includes a plurality of processes, it is desirable to place the instruction of the initial setting P-INI at the head of the program A. In FIG. 8, the initial setting P-INI is arranged before other processes a (P-a) to c (P-c). In an irregular case, interrupts cannot be prohibited before the initial setting P-INI is completed. However, this makes it possible to shorten the period for accepting interrupts and increase the possibility of normal operation. The initial setting P-INI may be executed prior to other processes, and may not be directly arranged at the start address (0000 in FIG. 7).

<Initial settings for program execution: Bus state controller settings>
The CPU reads data from the memory and writes data to a writable memory. At the time of reading and writing, this is done by designating the memory address (address, position). In order to effectively use the address space that can be used by the CPU, the CPU incorporates a bus state controller (see FIG. 9). The address space (CS space) that can be used by the CPU is large and is usually covered by a plurality of memory ICs (may be referred to as devices). The bus state controller optimally manages a plurality of memories. For example, the following is performed.

  Divide the address space into a maximum of 8 (areas CS0 to CS7), and allocate a maximum of 64 MB to each.

  Each area independently has a bus size (8, 16, 32 bits) that is the access width, a cycle wait function (up to 255 waits) to synchronize timing with a slow device, and a wait control to set the timing. Set the value.

  Since what kind of memory is connected to the CPU and how many are connected depends on the model, initial settings are made when the program is executed (initial setting by the program, initial setting P-INI2 in FIG. 9, This is different from the initial setting P-INI in FIG. 7), and the bus state controller is set so as to be optimal for the model (symbol AA in FIG. 9). The bus state controller initial setting process (initial setting process by program) is included in, for example, program A (start program) in FIG.

  The processing of the initial setting P-INI2 for appropriately connecting to the CS space in the initialization of the bus state controller will be described with reference to FIGS.

  FIG. 10 shows the default state. A correspondence relationship between devices such as a control ROM connected to the CPU, address spaces CS0 to CS7 assigned to each device, and a distinction between CS valid / invalid at the time of reset is shown. On the other hand, FIG. 12 shows the setting after the initial setting. 9 to 12, a device refers to an IC that is connected to a CPU such as a memory IC such as a ROM or a RAM, an I / O IC such as a port, or a controller IC such as a VDP and managed in an address space.

  As shown in FIG. 10, immediately after the start of the CPU operation, the setting of the CS space to which the external device is connected is the device connection for starting the program by the initial setting by the CPU itself (in the example of FIG. 10, the control ROM is connected). ) Is valid only for CSO, and other CS spaces are invalidated. A control ROM (shown as CS0, address 0000 in FIG. 9) connected to the CSO to perform an initial setting (initial setting by a program) for connecting to a device other than CS0 enabled by the initial setting by the CPU itself. Device) stores programs and data for enabling each CS space and performing various settings according to the relationship with the device connected to a space other than the CSO of the CPU (see FIG. 12).

  In FIG. 12, the CS is valid for a device used during operation of the gaming machine. The weight value is indicated by a sign such as W0, but this is determined for each device according to its hardware performance. For example, the greater the read / write speed, the smaller the wait value and the faster the operation becomes possible (the wait corresponds to the time that the CPU waits according to the device speed). The access width is indicated by a code such as B0, but this corresponds to the bus size (8, 16, 32 bits) for each device. For example, if the bus size of the control ROM is large, B0 is set to 32 bits, so that a large amount of data can be read and written at a time, and a higher speed operation is possible. The initial setting P-INI2 in FIG. 9 includes a table as shown in FIG. 12 for optimal setting for each device in this way.

  As described above in <Electric structure of gaming machine: overview of initial operation of CPU of sub-board>, the interrupt is invalidated in the CPU at the time of reset release by the initial setting by the CPU itself. However, similarly, the bus state controller is also set to a predetermined state. For example, as shown in FIG. 10, only CS0 is valid, its weight value is maximum, and the access width is minimum. This setting can be applied to any device, and thus is highly likely to guarantee a minimum operation. For example, even a low-speed device with a narrow access width can be accessed.

  In this state, program A (start program) is executed first. This start program is stored in the address set by the initial setting by the CPU itself, and is executed only when the reset is released.

  The initial setting P-INI2 (initial setting by the program) of the program A (start program) is processed, for example, according to the procedure shown in FIG. 11 (bus state controller procedure: (CS0) to (CS6)) as shown in FIG. To enable the CPU to properly connect to the CS space.

  (CS0) Although CS0 is enabled in the default state, parameters such as the weight value and access width are settings that are likely to guarantee the minimum operation as described above, and are actually connected. It is not commensurate with the performance of the control ROM. Therefore, first, the setting value of the CS0 space corresponding to the control ROM is changed to an optimum value. For example, the weight value is set to W0 and the access width is set to B0 based on the table of FIG. In this way, the performance of the program A is improved by adjusting the performance of the CSO space to the maximum, and then the setting for the other CS space is performed.

  (CS1) The CS1 space corresponding to the second half of the control ROM is validated, and the setting value of the CS1 space corresponding to the control ROM is changed to an optimum value. For example, the weight value is set to W0 and the access width is set to B0 based on the table of FIG.

  (CS7) The CS7 space corresponding to the control register of the VDP (liquid crystal panel controller) is validated, and the setting value of the corresponding CS7 space is changed to an optimum value. For example, the weight value is set to W7 and the access width is set to B7 based on the table of FIG.

  (CS2) The CS2 space corresponding to the backup RAM is validated, and the setting value of the CS2 space corresponding to the CS2 space is changed to an optimum value. For example, the weight value is set to W2 and the access width is set to B2 based on the table of FIG.

  (CS3) The CS3 space corresponding to the device control port is validated and the setting value of the corresponding CS3 space is changed to an optimum value. For example, the weight value is set to W3 and the access width is set to B3 based on the table of FIG.

  (CS6) The CS6 space corresponding to the DRAM and VRAM is validated, and the setting value of the corresponding CS6 space is changed to an optimum value. For example, the weight value is set to W6 and the access width is set to B6 based on the table of FIG.

  It should be noted that the validation and setting of the CS space only needs to be completed when access to the corresponding space is required, and all of the above processing (processing CS0 to CS7 in FIG. 11) is initialized P-INI2 There is no need to do this. For example, if only CS0, CS1, and CS7 are valid (the control ROM and VDP control register can be read and written), a VDP control program that can be processed is started after (CS1) and then (CS2) is performed. Also good. In this case, the above (CS2) to (CS6) are removed from the initial setting P-INI2, and they are performed after the VDP control program.

  As for CS4 used for debugging etc., it may be invalidated if it is not used in order to avoid malfunctions such as noise, and may be validated as necessary. In FIG. 12, CS4 is disabled (the display of the (CS4) debug port in FIG. 11 with a dotted line indicates that it is normally disabled). To enable the debug port, perform (CS4) after (CS3) above.

  Although it is invalid in FIGS. 11 and 12, (CS4) will be described. While enabling the CS4 space corresponding to the debug port, the setting value of the corresponding CS4 space is changed to an optimal value. For example, the weight value is set to W4 and the access width is set to B4 based on the table of FIG.

  According to the embodiment of the invention, it is possible to appropriately refer to the corresponding device by appropriately setting the CS space before using each device by the initial setting by the program.

<Initial setting for program execution: Setting of CS0 space for storing start program>
The reading and writing of the control ROM that stores the program for controlling the CPU (for example, the commands and data for performing the initial setting P-INI and P-INI2 shown in FIGS. Don't be. For this purpose, the setting of the bus controller must be a value that can reliably fetch the data in the control ROM.

  There are various types of ICs that can be used as the control ROM. It is expensive and has high performance, that is, high read speed, and therefore the weight value can be reduced and the access width can be increased. However, it is inexpensive, but the read speed is low, the read value is large, the wait value is large, and the access width cannot be reduced There are various types of memory. Parts used for designing a gaming machine are preferably not only low in cost but also general-purpose and easily available. If the CPU of the gaming machine can cope with a wide range of speeds from high speed to low speed, the choices of usable devices (memory) increase.

  From this point of view, in the embodiment of the invention, the initial setting INI of the CPU after reset (initial setting by the CPU itself) increases the wait value within the range allowed by the CPU, and increases the access width. It shall be set small. By doing in this way, the choice of the device (memory) used as control ROM of CS0 space can be expanded.

  FIG. 13 shows a setting example of the initial setting INI. The initial setting INI of the CPU after reset is that the address space CS0 to which the control ROM is connected is valid for the setting of the bus state controller, the wait value is Wint (predetermined wait value), and the access width is Bint (predetermined Access width). Wint is a large weight value (for example, maximum value) within a range allowed by the CPU, and Bint is also a small access width (for example, minimum value). For example, when the weight value is expressed by 8 bits, Wint = 255 and Bint = 8 bits.

  Thereafter, the performance of the entire system can be improved by enabling the setting of the bus state controller to be switched to an arbitrary value using a program (for example, initial setting P-INI2).

  For example, as shown in FIG. 12, the wait value Wint and the access width Bint are changed to W0 and the access width to B0 for the CS0 space. Assuming that the performance of the device used as the control ROM is sufficiently high, W0 is a small weight value (for example, the minimum value) within the range allowed by the CPU, and B0 is also a large access width (for example, the maximum value). is there. W0 <Wint, B0> Bint. For example, when WO = 38, 38 <255, and when BO = 32 bits, 32 bits> 8 bits. Alternatively, WO is made as small as possible and BO is made as large as possible within the performance range of the device used as the control ROM. The wait value is set to 255 because it may be written during debugging. During debugging, writing is performed to the ROM using Toll, so the maximum value is set to 255 to ensure writing. On the other hand, when shipping to the market, it is set to 0 which is the minimum value so that writing to the ROM is not possible (in addition, the signal line for writing is cut off for the sake of safety).

  According to the embodiment of the invention, it is possible to increase the choices of ROM that stores the start program. Note that the device for storing the start program is not limited to the ROM, and the embodiment of the invention can also be applied to a RAM (for example, a power-backed-up SRAM or a backup RAM).

  In addition, by setting the bus state controller so that the performance of the device connected to the CPU is fully exhibited by the initial setting P-INI2, the performance of the gaming machine can be improved.

  A modification according to the embodiment of the invention will be described with reference to FIGS.

  In FIG. 13, the setting contents of the bus state controller are included in the initial setting P-INI2 of the start program, but this may be stored separately from the control ROM. In this case, identification information for specifying the type and model of the device is prepared in the initial setting P-INI2, and the CPU reads the identification information, and based on this, the setting contents of the bus state controller are read and set.

  FIG. 14 shows an outline of the operation. Equipped with an initial setting table INI-T that stores settings for each device in advance. This includes the weight value and access width corresponding to the device identification information of FIG. After reset, the CPU accesses the initial setting P-INI2 of the control ROM and reads the identification information. The CPU accesses the initial setting table INI-T, reads the setting corresponding to the device identification information, and performs the setting. The initial setting table INI-T may be built in the CPU as indicated by a dotted line in FIG.

  FIG. 15A shows an example of identification information of the initial setting P-INI2. Identification information (ROMinfo etc.) is stored in advance for each connected device. The identification information is, for example, specific information (data) such as an allowable weight value and access width, but may be information (data) of the manufacturer and model number. Based on this, the setting contents are read from the initial setting table INI-T and the bus state controller is set.

  FIG. 15B shows an example of the initial setting table INI-T. Setting information such as a weight value and access width is stored for each identification information. In the example shown in the figure, valid / invalid information of CS is also stored for each identification information. The CPU reads the setting information from the initial setting table INI-T based on the identification information read from the initial setting P-INI2, and sets the bus state controller based on this.

  This modification can also increase the choice of ROM for storing the start program, and set the bus state controller so that the performance of the device connected to the CPU is fully exhibited, thereby improving the performance of the gaming machine. be able to.

  In this modification, the setting contents of the bus state controller are stored in a memory provided separately from the control ROM, so that the area spent for the initial setting of the control ROM can be reduced, and other programs can be stored accordingly. Become.

<Adjustment of reset release timing at initial setting>
Initial setting of the CPU itself and initial setting based on the start program are performed by power-on reset. At that time, devices (LED driver, motor driver, sound amplifier, etc. other than the CPU mounted on the sub board 20 ( Reset is also performed for (block). An LED driver, a motor driver, a sound amplifier, and the like may include a plurality of devices such as an IC, and in this section, an LED driver, a motor driver, a sound amplifier, and the like including a case of a plurality of devices are described as blocks. From the point of function and performance, the block is the same as the device. The target block (LED driver, motor driver, sound amplifier, etc.) can be reset by sending a reset signal from the CPU. The reset can be performed individually in units of blocks. These reset signals have predetermined logic at the time of starting the board. All blocks are shifted to the reset state by power-on reset, and then the reset is released.

  Blocks such as the CPU, LED driver, motor driver, and sound amplifier of the sub-board 20 are supplied with current from a common power supply unit. The power supply unit is designed so that its capacity supplies a sufficient current to the CPU and block, and the power supply unit normally does not become overloaded. However, when reset is released, a larger amount of current may temporarily flow, exceeding the rating of the power supply unit, that is, exceeding the value at which the required current can be supplied. Recent gaming machines are equipped with more drive units and light emitting elements, and the risk is high. Since the power supply unit includes a safety device that stops its operation when the rating is exceeded, it may operate and the gaming machine may stop. This should be avoided.

  The power supply system of the gaming machine will be described with reference to FIG. FIG. 16 is a power system diagram of this gaming machine. In this figure, the same or corresponding parts as in FIG.

  A power supply unit 205 supplies current to at least the main substrate 10, the sub substrate 20, and the peripheral substrate connected to the sub substrate 20.

  2051 is a rectifier that receives an AC power supply (AC input) connected to the gaming machine and rectifies the AC power supply. Note that the rectifying unit 2051 is not necessary when receiving a DC power supply instead of an AC power supply from the outside. That is, power supply from the outside of the gaming machine may be either AC or DC.

  Reference numeral 2052 denotes an AC-DC converter (first power supply unit) that converts the rectified power supply into a smooth direct current of 24 V (first voltage). The AC-DC converter 2052 includes an overcurrent protection circuit 2052a. This shuts down or reduces the output when a current exceeding the rated value or the upper limit value is output, or when a current exceeding the upper limit value is input from the rectifier unit 2051 (overcurrent detection limiter function). The overcurrent protection circuit 2052a prevents an excessive load from being applied to the AC-DC converter 2052 for a certain period of time and protects the AC-DC converter 2052 from destruction.

  Reference numeral 2053 denotes a DC-DC converter (second power supply unit) that converts the 24V power output from the AC-DC converter 2052 into 12V (second voltage).

  Reference numeral 20SA denotes a sound amplifier (acoustic signal generator) that outputs an acoustic signal for generating sound by driving speakers (acoustic generators) SPL and SP. The sound amplifier 20SA includes a memory (storage unit) (not shown) and stores acoustic data in advance (acoustic data storage unit). Based on this data, the sound amplifier 20SA generates an acoustic signal.

  20MD is a motor driver which generates a drive signal for driving the motors ML and MU.

  The 20LD is an LED driver that generates a light emission signal for blinking the LEDs 202B, 202L, and 202U.

  20CNV is a DC-DC converter that generates a 5V power supply for the LED driver 20LD.

  As can be seen from FIG. 16, the CPU and each block receive a current supply from a common AC-DC converter 2052. Therefore, if reset release is performed simultaneously for each block, as described above, more current temporarily flows at the time of reset release, so that the rating of the AC-DC converter 2052 may be exceeded and the overcurrent protection circuit 2052a may be activated. is there.

  Therefore, in the embodiment of the invention, the current value does not exceed the rating of the AC-DC converter 2052 by shifting the reset release timing by shifting the timing of the reset signal given to each block from the CPU.

  The CPU performs, for example, the processing of FIG. 17 according to the initial setting of the start program. An example of a reset timing chart by this processing is shown in FIG.

S100: The CPU shifts a plurality of blocks such as the LED driver 20LD, the motor driver 20MD, and the sound amplifier 20SA to the reset state. Specifically, a reset signal from the CPU is input to the reset terminal of each block.

S101: The CPU measures a predetermined time. Wait for the timing.

S102: The CPU cancels the reset state of a predetermined block (for example, LED driver 20LD) after completion of timing. Specifically, the input of the reset signal to the reset terminal is stopped. In the example of FIG. 18, the reset is released at time tr1.

S103: The CPU measures a predetermined time. Wait for the timing.

S104: The CPU cancels the reset state of another block (for example, the motor driver 20MD) after completion of timing. Specifically, the input of the reset signal to the reset terminal is stopped. In the example of FIG. 18, the reset is released at time tr2.

S105: The CPU measures a predetermined time. Wait for the timing.

S106: The CPU cancels the reset state of the remaining block (sound amplifier 20SA) after completion of timing. Specifically, the input of the reset signal to the reset terminal is stopped. In the example of FIG. 18, the reset is released at time tr3.

  As can be seen from FIG. 18, the reset timing for all the blocks is the same (time tr0), but the timing for releasing them is different (tr1, tr2, tr3). Therefore, a relatively large current consumption at the time of reset release does not flow at the same time. According to the embodiment of the present invention, the inrush current can be dispersed by changing the reset release timing of each block, so that the operation of the gaming machine is not hindered.

  When there are a plurality of blocks, the order of reset release may be as follows, for example.

(Order: Part 1)
Release the reset from the one with large current consumption (power). A block with a large current consumption (power) is considered to have a large inrush current. Based on this, if the reset of the block with the maximum current (electric power) is first released, the current is not supplied to other blocks with a large inrush current at that time, and there is a margin, and the overcurrent protection circuit 2052a Is unlikely to work. It is expected that the possibility that the overcurrent protection circuit 2052a operates can be reduced if reset is released in order from the largest consumption current (power).

(Order: Part 2)
When a current is supplied from a common AC-DC converter 2052 as shown in FIG. 16 and the voltage is lowered to serve as a power source for each block, the block is directly supplied with a current from the common power source (converter) (FIG. 16). Next, the sound amplifier 20SA) is first released from reset, and then the block (motor driver 20MD in FIG. 16) that receives current supply from the converter that is directly supplied with current from the common power supply, The reset is released in the order of blocks (LED driver 20LD in FIG. 16) receiving current supply from the converter receiving supply. Since the inrush current of a block that is directly supplied with a current from a common power supply directly affects the common power supply, it is expected that the reset should be canceled first when there is a margin. When the converters are connected in series as shown in FIG. 16, it is expected that the influence of the inrush current on the common power source can be reduced by releasing the reset in the order of connection (from the center toward the end) ( Each converter may be provided with a capacitor (not shown), which can reduce the inrush current somewhat).

<Maintaining initial settings in case of malfunction>
In the initial setting described above, the address space CS3 is assigned to the device control port (see FIG. 12). The device control port is a port for holding and outputting a control signal for controlling the device, and the device control signal is an important signal that determines the operation of the device.

  A specific circuit is shown in FIG. The address space CS3 is connected to a control port for switching between a liquid crystal panel control signal and a 5V signal (high level signal) supplied to an external device (an apparatus outside the sub-board 20). Since a sufficient number of I / O port pins were not prepared for the CPU, a dedicated IC (latch in FIG. 19) was connected to the address space CS3, and the above signals were connected to this IC (latch). Control external devices by setting ports.

  As can be seen from FIG. 19A, there is no circuit for reading the output of the IC (latch) and feeding it back to the CPU, and the above signal only writes to the IC (latch).

  The problem here is that, for example, when the output of the IC (latch) changes unintentionally due to the influence of noise or the like, this cannot be detected. For this reason, it cannot correct that the signal which was not intended is output, and it may consider having a bad influence on operation | movement of a game machine.

  Therefore, in the embodiment of the invention, whether the operation is normal or abnormal for an IC that determines the operation mode by setting data, such as the latch of FIG. First, writing is repeated at a predetermined timing. That is, data having the same value as the optimum value when the initial setting is performed is continuously written. In other words, the initial setting is repeated. For example, as shown in FIG. 19B, the CPU gives a write signal to the latch at intervals of Tw. Although not shown, when a write signal is generated, the CPU prepares and latches a latch input signal (initial setting signal, in the above example, a liquid crystal panel control signal and a 5V signal supplied to an external device). To supply. The Tw interval is an example, and the interval may be different every time.

  According to the embodiment of the invention, even if the content held by the latch changes unintentionally due to some external factor such as static electricity or radio waves, the initial setting can be repeated to restore the normal state. it can.

  By shortening the initial repetition interval, even if the content held by the latch changes unintentionally, it is possible to return at a level that does not hinder the game. In the embodiment of the invention, since it is not necessary to determine whether the IC (latch) that is the control target is normal or abnormal, the load on the program is small (processing for detecting an abnormality can be omitted).

  In the above description, a slot machine has been described as an example, but the embodiment of the present invention can also be applied to other gaming machines such as pachinko machines.

  The pachinko machine (ball game machine) will be briefly described with reference to FIGS. 20, 21, and 22. FIG. The pachinko machine includes an outer frame 50, a main body member 51, and an opening frame door 52 as main members. The opening frame door 52 is provided with a transparent plate member made of glass or resin at its opening, and an electric decoration (not shown), a speaker 52b, a door 53 with a ball tray, and the like are attached around the opening.

  The game board 10 </ b> B is detachably attached to the main body member 51 using a predetermined fixing member so as to face the space portion of the main body member 51. The board surface 11 of the game board 10 </ b> B is a rectangular board surface provided with a guide rail 12 and a discharge port (out port) 13 that guides a game ball dropped in a substantially circular game area defined by the guide rail 12 to the outside. An out ball sensor 13S is provided inside the discharge port 13 (FIG. 21).

  As shown in FIG. 21, the board surface 11 includes a variable display device (center accessory) 30a having one or a plurality of variable display portions such as an effect display lamp and an LCD (liquid crystal display device), a through chucker 30b, a normal winning device ( (Not shown), a start chucker (starting winning device) 30d having a start winning opening, and attackers 30c, 30e having a large winning opening. Sphere passage detectors 20b, 20c, 20d, and 20e are provided inside 30b, 30c, 30d, and 30e.

  The board surface 11 is provided with decorative devices of various designs for enhancing interest, together with a winning device 30, obstacles such as nails and windmills (not shown).

  FIG. 22 is a functional block diagram of the gaming machine according to the embodiment of the present invention.

  Although not shown, the main control device (main substrate) 101 and the sub control device (sub substrate) 200 are configured around a CPU and include a ROM, a RAM, an I / O, and the like. Then, the CPU operates as described below by reading the program stored in the ROM.

  Reference numeral 100 denotes a main control device that performs processing related to the game. The main control device 101 performs electrical game control processing and generates main processing information. The main control device 101 receives (inputs) the signals from the ball passage detectors 20b to 20d that move (flow down) the game area and detect the winning balls that have passed through the winning devices 30b to 30d, respectively, and receive the winning balls of the winning devices 30b to 30d. A lottery / judgment is made according to the passage.

  1110 is a random number acquisition for acquiring a random number based on the fact that a game ball has passed through the start chucker (start winning prize opening) 30d (more precisely, detected by the sensor 20d provided therein). Part. The random number obtaining unit 1110 includes either or both of a hard random number generator 1120 including a counter and a soft random number generator 1130 operated by a program.

  Reference numeral 1210 denotes a symbol fluctuation control unit that causes the special symbol display device 119 to variably display symbols based on the random numbers acquired by the random number acquisition unit 1110.

  1310 is a special game control unit. The special game control unit 1310 stops and displays the symbols constituting the predetermined award mode on the special symbol display device 119 on condition that the random number acquired by the random number acquisition unit 1110 is a winning random number (big hit). Then, a special game advantageous to the player is performed.

  Reference numeral 1410 denotes a probability variation game control unit. The probability variation game control unit 1410 causes the random number acquisition unit 1110 to perform a probability variation game that increases the possibility of acquiring the winning random number after the special game by the special game control unit 1310. The variably displayed symbols are displayed in a stopped or jackpot pattern based on the random numbers acquired by the random number acquisition unit 1110 after a predetermined time.

  1510 is extracted based on the fact that a game ball passes through a start chucker (start prize-winning device) 30d when the game ball passes through the start chucker (start winning device) 30d while the special symbol display device 119 displays the symbols in a variable manner. This is a hold processing unit that stores the random number that has been stored, and that can perform the variable display of the symbol based on the stored random number after the variable display of the symbol has been completed.

  Reference numeral 1610 denotes a prefetch processing unit. The prefetch processing unit 1610 determines whether or not each reserved ball is a big hit. A random number, which is the stored content of the reserved ball, is provisionally determined (prefetched) at the timing of starting winning random number extraction, and the result is sent to the sub-control device 200.

  110a is a payout for paying out a predetermined number of game balls as game profits according to the game ball winnings of the winning devices 30c to 30e and the normal winning device (not shown) and / or according to the lottery / judgment result thereby It is a control device.

  110b is a payout control board for controlling the payout control device 110a.

  Reference numeral 119 denotes a special symbol display device that is a display device (for example, a 7-segment display) provided in the state display device 141.

  Reference numeral 130 denotes a normal symbol display device that is a display device (for example, a 7-segment display) provided in the state display device 141.

  141 is a state display device provided on the board surface of the gaming machine so that it can be visually recognized by the player. The status display device 141 includes a round number display unit 150 that displays the number of rounds and a reservation number display unit 160 that displays the number of reservations. The number-of-holds display unit 160 is arranged on the game board and displays a held ball during the symbol variation display.

  Reference numeral 200 denotes a sub-control device that performs control to perform predetermined output mode processing including effects such as driving of a movable body, blinking of light, generation of sound, and the like by obtaining processing information generated by the main control device 101. .

  An effect symbol control unit 2100 controls the image display device 210 to display an image related to an effect, an image related to a game state, a current game state, an error display, a hold display, and the like. Note that during the fluctuation of the special symbol display device 119, the fluctuation is stopped from the fluctuation display in synchronization with the special symbol display device 119.

  Reference numeral 2200 denotes an accessory driving unit that controls the movable body 220 provided in the game board 10B.

  Reference numeral 2300 denotes a lamp control unit for controlling lighting of the lamp / lighting 230 provided on the game board 10B, the variable display device 30a, or the gaming machine housing.

  Reference numeral 2400 denotes a sound control unit that controls the sound generator 240.

  Reference numeral 2500 denotes a prefetch effect processing unit that performs an effect related to prefetching based on the determination result from the prefetch processing unit 1610. For example, the display corresponding to the holding ball corresponding to the hit of the image display device 210 (e.g., the light emission color of the holding ball display) is different from the other, which suggests that the holding ball is highly likely to win. Or notify that it is a win.

  Reference numeral 2600 denotes a specific effect processing unit that performs processing related to a specific effect that is an effect unrelated to the game state of the main control device 101 based on the output (time signal) of the real-time clock 2700. For example, at every hour or at a predetermined time, a predetermined music piece is played independently of the gaming state, and the video image is displayed on the image display device 210.

  Reference numeral 2700 denotes a real-time clock that outputs a time signal.

  Reference numeral 210 denotes an image display device such as a liquid crystal display device (LCD).

  220 is a movable body. The movable body 220 moves back and forth between, for example, a normal state and a different state. The movable body is, for example, a flat plate shape, a cylindrical shape, a disk shape, a gear shape having irregularities, or the like. Although not shown, a power unit for driving the movable body 220 is provided.

  The image display device 210 and the movable body 220 are provided in a variable display device (center accessory) 30a.

  Reference numeral 230 denotes a lamp / lighting including a light emitting element.

  240 is a sound generator. The sound generating device 240 includes a speaker 52b and a sound processor (not shown) that generates a driving signal for the speaker 52b based on a signal from the sound control unit 2400 of the sub-control device 200.

  22 corresponds to the sub-board 20 of FIG. 3, and the CPU and ROM of the sub-control device 200 correspond to the CPU and ROM of the sub-board 20 of FIG. In the ROM of the sub-control device 200, a start program for initial setting is stored in advance. This start program includes an initial setting command for executing processing (for example, interrupt prohibition setting) corresponding to at least part of the initial setting performed by the CPU based on reset.

  The embodiment of the present invention can be applied not only to the sub board 20 and the sub control apparatus 200 but also to the main board 10 and the main control apparatus 101.

  In the embodiment of the present invention, the initial setting performed by the start program has been described centering on interrupt inhibition, but other processing, for example, register setting, may be used. CPU parameters such as a counter and a flag may be set so that the restart process can be normally performed even when the execution of the start program is started in an irregular state.

  The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

20 Sub-board (processing section)
CPU Central processing unit ROM Read only memory (storage unit)
Initial setting of the CPU itself that is performed in the INI CPU
Program A Program A (starting program)
Initial setting by P-INI program (initial setting command)

Claims (3)

A storage unit that stores at least a program, and a central unit that performs initial setting by the central processing unit itself by resetting, and reads and executes a start program stored in the storage unit at a position determined by the initial setting by the central processing unit itself In a gaming machine including a processing unit including a processing device,
The game machine according to claim 1, wherein the start program includes an initial setting instruction by a program for executing processing corresponding to at least a part of initial setting by the central processing unit itself performed by the central processing unit based on reset. The initial setting by the central processing unit itself includes at least interrupt disable setting,
2. The gaming machine according to claim 1, wherein the initial setting instruction by the program is an interrupt prohibition setting instruction.   3. The gaming machine according to claim 1, wherein the initial setting instruction by the program is arranged at a head of the start program.

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