JP2016134591A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 222
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 67
- 239000011347 resin Substances 0.000 claims abstract description 67
- 238000002360 preparation method Methods 0.000 claims abstract description 8
- 238000007789 sealing Methods 0.000 claims description 51
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 22
- 230000017525 heat dissipation Effects 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000000465 moulding Methods 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000005855 radiation Effects 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 11
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】準備工程では、IGBTを有する第1半導体チップ16U,16L及びFWDを有する第2半導体チップ18U,18Lを、第1ヒートシンク20U,20Lと第2ヒートシンク22U,22Lにより挟んで接続構造体52を形成する。その際、対応する第1半導体チップと第2半導体チップのうち、第1半導体チップがゲートに近くなるように配置する。また、切り欠き部40を有する第1ヒートシンク20Uを用い、Z方向からの投影視において、ゲートから最も遠い第2半導体チップ18Uの周囲の一部であってゲートから最も遠い位置を含んで切り欠き部が位置し、該第2半導体チップの周囲の残りと残りの半導体チップの周囲を、第1ヒートシンクと第2ヒートシンクが覆うように、各ヒートシンクを配置する。
【選択図】図9
Description
Claims (2)
- 第1ヒートシンク(20U,20L)と第2ヒートシンク(22U,22L)との間に、半導体チップとして、パワートランジスタが形成された第1半導体チップ(16U,16L)及び前記パワートランジスタに対応する還流ダイオードが形成された第2半導体チップ(18U,18L)を、前記第1ヒートシンクと前記第2ヒートシンクとの対向方向に直交する第1方向に並べて配置し、各ヒートシンクと各半導体チップとをはんだ(38)により接続して両面放熱構造とすることで、該両面放熱構造を少なくとも1つ備える接続構造体(52)を準備する準備工程と、
前記接続構造体を型のキャビティ内に配置し、前記型のゲート(54)から前記キャビティ内に樹脂を注入して、前記接続構造体を封止するための封止樹脂体(28)を成形する成形工程と、
を備える半導体装置の製造方法であって、
前記準備工程では、
前記対向方向からの投影視において、対応する前記第1半導体チップ及び前記第2半導体チップのうち、前記第1半導体チップが前記ゲートに対して近くなるように、各半導体チップを配置するとともに、
前記第1ヒートシンク及び前記第2ヒートシンクの少なくとも一方として、貫通部(40,56)を有するものを用い、前記対向方向からの投影視において、前記ゲートから最も遠い位置にある前記第2半導体チップの周囲の一部であって前記ゲートから最も遠い位置を含んで前記貫通部が位置し、該第2半導体チップの周囲の残りの部分と、残りの前記半導体チップの周囲とを、前記第1ヒートシンク及び前記第2ヒートシンクの両方が覆うように、前記第1ヒートシンク及び前記第2ヒートシンクを配置することを特徴とする半導体装置の製造方法。 - 前記準備工程では、
前記第1ヒートシンクと各半導体チップとの間に金属ブロック(24U,24L,26U,26L)を配置して、前記半導体チップの主電極と前記金属ブロック、及び、前記金属ブロックと前記第1ヒートシンクを、前記はんだにより接続するとともに、
前記貫通部が、前記ゲートから最も遠い位置にある前記第2半導体チップの主電極形成面のうち、前記金属ブロックを取り囲む外周領域の一部と重なるように、前記第1ヒートシンク及び前記第2ヒートシンクを配置することを特徴とする請求項1に記載の半導体装置の製造方法。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018164160A1 (ja) * | 2017-03-10 | 2018-09-13 | 株式会社村田製作所 | モジュール |
CN109285787A (zh) * | 2017-07-19 | 2019-01-29 | 丰田自动车株式会社 | 半导体装置的制造方法 |
JP2019079966A (ja) * | 2017-10-25 | 2019-05-23 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP2020057740A (ja) * | 2018-10-04 | 2020-04-09 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63158844A (ja) * | 1986-09-10 | 1988-07-01 | Fuji Electric Co Ltd | 樹脂パツケ−ジ型半導体装置のトランスフアモ−ルド法 |
JP2009224560A (ja) * | 2008-03-17 | 2009-10-01 | Denso Corp | 半導体装置およびその製造方法 |
WO2013133134A1 (ja) * | 2012-03-07 | 2013-09-12 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
JP2014154779A (ja) * | 2013-02-12 | 2014-08-25 | Toyota Motor Corp | 半導体装置 |
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2015
- 2015-01-22 JP JP2015010333A patent/JP6332054B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63158844A (ja) * | 1986-09-10 | 1988-07-01 | Fuji Electric Co Ltd | 樹脂パツケ−ジ型半導体装置のトランスフアモ−ルド法 |
JP2009224560A (ja) * | 2008-03-17 | 2009-10-01 | Denso Corp | 半導体装置およびその製造方法 |
WO2013133134A1 (ja) * | 2012-03-07 | 2013-09-12 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
JP2014154779A (ja) * | 2013-02-12 | 2014-08-25 | Toyota Motor Corp | 半導体装置 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018164160A1 (ja) * | 2017-03-10 | 2018-09-13 | 株式会社村田製作所 | モジュール |
CN109285787A (zh) * | 2017-07-19 | 2019-01-29 | 丰田自动车株式会社 | 半导体装置的制造方法 |
JP2019021811A (ja) * | 2017-07-19 | 2019-02-07 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
CN109285787B (zh) * | 2017-07-19 | 2021-11-16 | 株式会社电装 | 半导体装置的制造方法 |
JP2019079966A (ja) * | 2017-10-25 | 2019-05-23 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP6992406B2 (ja) | 2017-10-25 | 2022-01-13 | 株式会社デンソー | 半導体装置の製造方法 |
JP2020057740A (ja) * | 2018-10-04 | 2020-04-09 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP7087901B2 (ja) | 2018-10-04 | 2022-06-21 | 株式会社デンソー | 半導体装置の製造方法 |
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