JP2016042497A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 173
- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 238000000034 method Methods 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 50
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000009467 reduction Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 80
- 230000015556 catabolic process Effects 0.000 description 43
- 239000012535 impurity Substances 0.000 description 34
- 239000011229 interlayer Substances 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 239000000758 substrate Substances 0.000 description 16
- 230000000052 comparative effect Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
Description
[構造説明]
図1は、本実施の形態の半導体装置(半導体チップ)の構成を模式的に示す平面図である。図2は、本実施の形態の半導体装置の構成を示す断面図である。図2に示す断面は、例えば、図1のA−A部と対応する。本実施の形態の半導体装置(半導体素子)は、縦型のパワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)である。MOSFETは、MISFET(Metal Insulator Semiconductor Field Effect Transistor)と呼ばれることもある。図3は、本実施の形態の半導体装置のp型カラム領域の構成を示す平面図である。
図2に示すように、セル領域CRには、パワーMOSFETが形成されている。このパワーMOSFETは、半導体基板1S上のエピタキシャル層EPSの主表面に形成されている。エピタキシャル層EPSは、複数のp型カラム領域(p型ピラー、ピラーともいう)PC1と複数のn型カラム領域(n型ピラー、ピラーともいう)NC1とから成る。p型カラム領域PC1とn型カラム領域NC1とはX方向に交互に配置されている。このようなp型カラム領域PC1とn型カラム領域NC1とが周期的に配置された構造を、スーパージャンクション(Superjunction)構造と言う。図3に示すように、p型カラム領域PC1の上面からの平面視における形状は、ライン状(Y方向に長辺を有する矩形状)である。
図2に示すように、中間領域TRには、ゲート引き出し部GPU、ゲート引き出し電極GPE、ソース引き出し領域SPRおよびソース引き出し電極SPEが形成されている。
図2に示すように、周辺領域PERには、フィールドプレート電極(電極、ダミー電極とも言う)FFPが形成されている。
次いで、図4〜図17を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、本実施の形態の半導体装置の構成をより明確にする。図4〜図17は、本実施の形態の半導体装置の製造工程を示す断面図または平面図である。本実施の形態の半導体装置は、いわゆる「トレンチフィル法」と呼ばれる方法を用いて製造される。本実施の形態の半導体装置において、セル領域CRおよび中間領域TRのpn接合の耐圧は、例えば、600V〜650V程度、周辺領域PERのpn接合の耐圧は、700V〜750V程度である。
本実施の形態においては、様々な応用例について説明する。なお、実施の形態1等と同様の部位には同一または関連する符号を付し、その繰り返しの説明は省略する。
実施の形態1(図3)においては、セル領域CRおよび中間領域TRに、ライン状のp型カラム領域PC1を配置し、周辺領域PERに、スパイラル状のp型カラム領域PC3を配置したが、中間領域TRのp型カラム領域をスパイラル状としてもよい。
実施の形態1(図3)においては、中間領域TRを区画する矩形状の領域の角部(Ca)を起点として、ここから中間領域TRを囲むように、第1周目のp型カラムを配置したが、起点を変更してもよい。本応用例において、スパイラル状のp型カラム領域PC3の起点S以外は、実施の形態1と同様である。
応用例2(図24)においては、p型カラム領域PC3の起点Sをセル領域CRの角部からずらしたが、起点Sをずらすことにより形成された領域に、ダミーp型カラム領域DCを形成してもよい。本応用例において、ダミーp型カラム領域DC以外は、応用例2と同様である。
実施の形態1(図3)においては、周辺領域PERのp型カラム領域PC3をスパイラル状とし、第n−1周のp型カラムと第n周のp型カラムとの間隔を均一としたが、第n−1周のp型カラムと第n周のp型カラムとの間を変更してもよい。本応用例において、p型カラム領域PC3の第n−1周のp型カラムと第n周のp型カラムとの間隔以外は、実施の形態1と同様である。
応用例4(図26(A))においては、第1周〜第n周までのp型カラムについて、カラムの周回毎にカラム間の間隔を変更したが、各周のp型カラムの角部を起点として間隔を変更してもよい。
本応用例においては、フィールドプレート電極FFPの形状について説明する。図28〜図31は、本実施の形態の応用例6の半導体装置の構成を説明するための平面図または断面図である。実施の形態1においては、フィールドプレート電極FFPを、p型カラム領域PC3とn型カラム領域NC3の境界の上方に配置した。即ち、図28に示すように、フィールドプレート電極FFPを、p型カラム領域PC3のセル領域CR側と逆側の端部の上方に配置した。この場合、フィールドプレート電極FFPは、p型カラム領域PC3と同様に、スパイラル状に配置される。
BC ボディコンタクト領域
Ca 角部
Cb 点
CH チャネル領域
CR セル領域
DC ダミーp型カラム領域
DE ドレイン電極
DT1 溝
DT3 溝
EP エピタキシャル層
EPI エピタキシャル層
EPS エピタキシャル層
FFP フィールドプレート電極
GE ゲート電極
GOX ゲート絶縁膜
GPE ゲート引き出し電極
GPU ゲート引き出し部
IL 層間絶縁膜
NC1 n型カラム領域
NC3 n型カラム領域
PAS 表面保護膜
PC1 p型カラム領域
PC3 p型カラム領域
PER 周辺領域
PF1 導体膜
PR フォトレジスト膜
S 起点
SE ソース電極
SPE ソース引き出し電極
SPR ソース引き出し領域
SR ソース領域
TR 中間領域
Claims (20)
- 第1領域と前記第1領域を囲む第2領域とを有する半導体層と、
前記第1領域の前記半導体層中に形成された第1導電型の複数の第1ピラーおよび前記第1導電型と逆導電型の第2導電型の複数の第2ピラーと、
前記第1領域の前記半導体層の上方に形成された半導体素子と、
前記第2領域の前記半導体層中に形成された前記第1導電型の第3ピラーおよび前記第2導電型の第4ピラーと、
を有し、
前記第1ピラーと前記第2ピラーは交互に配置され、
前記第3ピラーは、前記第1領域をスパイラル状に囲むように配置され、
前記第4ピラーは、前記スパイラル状の第3ピラーの間に配置され、前記第1領域をスパイラル状に囲むように配置され、
前記第1ピラーは、前記半導体層中に形成された第1溝中に配置され、
前記第3ピラーは、前記半導体層中に形成された第2溝中に配置され、
前記スパイラル状の第3ピラーの第1周は角部を有し、角部を構成する第1側面および第2側面は、(100)面または(110)面と対応する、半導体装置。 - 請求項1記載の半導体装置において、
前記第3ピラーおよび前記第4ピラーは、平面視において矩形状の前記第1領域を、矩形状に少なくもとも2周以上スパイラル状に囲み、
第1周目は、前記矩形状の前記第1領域の各辺に沿って配置され、
第2周目は、前記第1周目の各辺に沿って配置されている、半導体装置。 - 請求項2記載の半導体装置において、
前記第3ピラーの起点は、前記矩形状の前記第1領域の角部に配置されている、半導体装置。 - 請求項2記載の半導体装置において、
前記第3ピラーの起点は、前記矩形状の第1辺の途中の位置に配置されている、半導体装置。 - 請求項4記載の半導体装置において、
前記矩形状の前記第1領域の角部から前記第3ピラーの起点までの間に位置する第5ピラーを有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第3ピラーおよび前記第4ピラーは、平面視において矩形状の前記第1領域を、矩形状に少なくもとも3周以上スパイラル状に囲み、
第1周目は、前記矩形状の前記第1領域の各辺に沿って配置され、
第2周目は、前記第1周目の各辺に沿って配置され、
第3周目は、前記第2周目の各辺に沿って配置され、
前記第1周目と前記第2周目との間隔は、前記第2周目と前記第3周目との間隔と異なる、半導体装置。 - 請求項6記載の半導体装置において、
前記第1周目と前記第2周目との間隔は、前記第2周目と前記第3周目との間隔より小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記第3ピラーおよび前記第4ピラーは、平面視において矩形状の前記第1領域を、矩形状に少なくもとも2周以上スパイラル状に囲み、
第1周目は、前記矩形状の前記第1領域の各辺に沿って配置され、
第2周目は、前記第1周目の各辺に沿って配置され、
前記第1周目の第1辺と前記第2周目の第1辺との間隔は、前記第1周目の第2辺と前記第2周目の第2辺との間隔と異なる、半導体装置。 - 請求項8記載の半導体装置において、
前記第1周目の第1辺と前記第2周目の第1辺との間隔は、前記第1周目の第2辺と前記第2周目の第2辺との間隔より小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記第2溝について、前記第2溝の深さ/幅であるアスペクト比が12以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1溝について、前記第1溝の深さ/幅であるアスペクト比が12以上であり、
前記第2溝について、前記第2溝の深さ/幅であるアスペクト比が12以上である、半導体装置。 - 請求項1記載の半導体装置において、
前記第2領域の前記半導体層上に形成された電極を有する、半導体装置。 - 請求項12記載の半導体装置において、
前記電極は、前記スパイラル状の第3ピラーに沿ってスパイラル状に配置されている、半導体装置。 - 請求項12記載の半導体装置において、
前記電極は、前記スパイラル状の第3ピラーに沿って環状に配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体素子は、
前記第2ピラー上にゲート絶縁膜を介して形成されたゲート電極と、
前記第2ピラーの隣の前記第1ピラーの上部に形成された前記第1導電型の半導体領域と、
前記半導体領域の上部に形成されたソース領域と、
を有する、半導体装置。 - (a)第1導電型の半導体層の第1領域に複数の第1溝を形成し、前記半導体層の前記第1領域を囲む第2領域に前記第1領域をスパイラル状に囲む第2溝を形成する工程、
(b)前記第1溝および第2溝中に、前記第1導電型と逆導電型の第2導電型の半導体を埋め込むことにより、
(b1)前記第1溝中に第1ピラーを形成するとともに、前記第1ピラー間の前記半導体層よりなる第2ピラーを形成し、
(b2)前記第2溝中に第3ピラーを形成するとともに、前記スパイラル状の第3ピラーの間の前記半導体層よりなる第4ピラーを形成する工程、
を有し、
前記(a)工程は、第1側面と第2側面とで構成される角部を有する前記第2溝を形成する工程であり、
前記(b2)工程は、結晶成長により、前記半導体を前記第2溝に埋め込む工程である、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、前記第1側面および前記第2側面は、(100)面または(110)面と対応する、半導体装置の製造方法。
- 請求項16記載の半導体装置の製造方法において、
前記第2溝は、平面視において矩形状の前記第1領域を、矩形状に少なくもとも3周以上スパイラル状に囲み、
第1周目は、前記矩形状の前記第1領域の各辺に沿って配置され、
第2周目は、前記第1周目の各辺に沿って配置され、
第3周目は、前記第2周目の各辺に沿って配置される、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記第1溝は、前記第1溝の深さ/幅であるアスペクト比が12以上であり、
前記第2溝は、前記第2溝の深さ/幅であるアスペクト比が12以上である、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(b)工程の後、
(c)前記第1領域に、半導体素子を形成する工程を有し、
前記(c)工程は、
(c1)前記第2ピラー上にゲート絶縁膜を介してゲート電極を形成する工程、
(c2)前記第2ピラーの隣の前記第1ピラーに前記第1導電型の半導体領域を形成する工程、
(c3)前記半導体領域の上部にソース領域を形成する工程、
を有する、半導体装置の製造方法。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04332173A (ja) * | 1991-05-07 | 1992-11-19 | Fuji Electric Co Ltd | プレーナ型半導体装置及びその製造方法 |
JP2004128293A (ja) * | 2002-10-04 | 2004-04-22 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2007012801A (ja) * | 2005-06-29 | 2007-01-18 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2010040975A (ja) * | 2008-08-08 | 2010-02-18 | Sony Corp | 半導体装置およびその製造方法 |
JP2011108906A (ja) * | 2009-11-19 | 2011-06-02 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
US20130200499A1 (en) * | 2012-02-03 | 2013-08-08 | Inergy Technology Inc. | Semiconductor device |
JP2014003200A (ja) * | 2012-06-20 | 2014-01-09 | Renesas Electronics Corp | 縦型パワーmosfetおよび半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4074051B2 (ja) * | 1999-08-31 | 2008-04-09 | 株式会社東芝 | 半導体基板およびその製造方法 |
JP2008227474A (ja) * | 2007-02-13 | 2008-09-25 | Toshiba Corp | 半導体装置 |
JP4945594B2 (ja) * | 2009-03-16 | 2012-06-06 | 株式会社東芝 | 電力用半導体装置 |
EP2599107B1 (en) * | 2010-07-26 | 2016-12-21 | STMicroelectronics Srl | Process for filling deep trenches in a semiconductor material body |
JP6009731B2 (ja) * | 2010-10-21 | 2016-10-19 | 富士電機株式会社 | 半導体装置 |
JP2012186374A (ja) * | 2011-03-07 | 2012-09-27 | Renesas Electronics Corp | 半導体装置、及びその製造方法 |
JP5641995B2 (ja) * | 2011-03-23 | 2014-12-17 | 株式会社東芝 | 半導体素子 |
US8786010B2 (en) * | 2011-04-27 | 2014-07-22 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
CN105789271B (zh) * | 2011-09-27 | 2019-01-01 | 株式会社电装 | 半导体器件 |
JP6375176B2 (ja) * | 2014-08-13 | 2018-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
CN204243047U (zh) * | 2014-11-03 | 2015-04-01 | 吉林华微电子股份有限公司 | 沟槽超级结半导体器件的正交超级结拐角终端 |
JP6534813B2 (ja) * | 2015-01-08 | 2019-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04332173A (ja) * | 1991-05-07 | 1992-11-19 | Fuji Electric Co Ltd | プレーナ型半導体装置及びその製造方法 |
JP2004128293A (ja) * | 2002-10-04 | 2004-04-22 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2007012801A (ja) * | 2005-06-29 | 2007-01-18 | Shindengen Electric Mfg Co Ltd | 半導体装置 |
JP2010040975A (ja) * | 2008-08-08 | 2010-02-18 | Sony Corp | 半導体装置およびその製造方法 |
JP2011108906A (ja) * | 2009-11-19 | 2011-06-02 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
US20130200499A1 (en) * | 2012-02-03 | 2013-08-08 | Inergy Technology Inc. | Semiconductor device |
JP2014003200A (ja) * | 2012-06-20 | 2014-01-09 | Renesas Electronics Corp | 縦型パワーmosfetおよび半導体装置 |
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