JP2015522188A5 - - Google Patents

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Publication number
JP2015522188A5
JP2015522188A5 JP2015519327A JP2015519327A JP2015522188A5 JP 2015522188 A5 JP2015522188 A5 JP 2015522188A5 JP 2015519327 A JP2015519327 A JP 2015519327A JP 2015519327 A JP2015519327 A JP 2015519327A JP 2015522188 A5 JP2015522188 A5 JP 2015522188A5
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JP
Japan
Prior art keywords
clock
clock domain
frequency
data signal
mechanism according
Prior art date
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Application number
JP2015519327A
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English (en)
Japanese (ja)
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JP6192065B2 (ja
JP2015522188A (ja
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Publication date
Priority claimed from GB1211425.2A external-priority patent/GB2503473A/en
Application filed filed Critical
Publication of JP2015522188A publication Critical patent/JP2015522188A/ja
Publication of JP2015522188A5 publication Critical patent/JP2015522188A5/ja
Application granted granted Critical
Publication of JP6192065B2 publication Critical patent/JP6192065B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015519327A 2012-06-27 2013-06-20 クロック・ドメイン間のデータ転送 Expired - Fee Related JP6192065B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB1211425.2A GB2503473A (en) 2012-06-27 2012-06-27 Data transfer from lower frequency clock domain to higher frequency clock domain
GB1211425.2 2012-06-27
PCT/GB2013/051608 WO2014001765A1 (en) 2012-06-27 2013-06-20 Data transfer between clock domains

Publications (3)

Publication Number Publication Date
JP2015522188A JP2015522188A (ja) 2015-08-03
JP2015522188A5 true JP2015522188A5 (enExample) 2016-08-12
JP6192065B2 JP6192065B2 (ja) 2017-09-06

Family

ID=46704315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015519327A Expired - Fee Related JP6192065B2 (ja) 2012-06-27 2013-06-20 クロック・ドメイン間のデータ転送

Country Status (8)

Country Link
US (1) US9515812B2 (enExample)
EP (1) EP2847664B1 (enExample)
JP (1) JP6192065B2 (enExample)
KR (1) KR20150037900A (enExample)
CN (1) CN104412222B (enExample)
GB (1) GB2503473A (enExample)
TW (1) TWI604689B (enExample)
WO (1) WO2014001765A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2528481B (en) 2014-07-23 2016-08-17 Ibm Updating of shadow registers in N:1 clock domain
GB201907717D0 (en) * 2019-05-31 2019-07-17 Nordic Semiconductor Asa Apparatus and methods for dc-offset estimation
TWI740564B (zh) * 2020-07-03 2021-09-21 鴻海精密工業股份有限公司 跨時鐘域信號傳輸方法、電路以及電子裝置
GB202014083D0 (en) * 2020-09-08 2020-10-21 Nordic Semiconductor Asa Clock domain crossing
CN114461009B (zh) * 2022-01-07 2024-04-26 山东云海国创云计算装备产业创新中心有限公司 一种应用于fpga单比特信号自动识别时钟域转换的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150313A (en) 1990-04-12 1992-09-22 Regents Of The University Of California Parallel pulse processing and data acquisition for high speed, low error flow cytometry
US6112307A (en) * 1993-12-30 2000-08-29 Intel Corporation Method and apparatus for translating signals between clock domains of different frequencies
US6260152B1 (en) 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6359479B1 (en) * 1998-08-04 2002-03-19 Juniper Networks, Inc. Synchronizing data transfers between two distinct clock domains
DE10128396B4 (de) * 2001-06-12 2005-02-24 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Übertragen von Daten von ein mit einem ersten Takt betriebenes System an ein mit einem zweiten Takt betriebenes System
US6928574B1 (en) * 2001-08-23 2005-08-09 Hewlett-Packard Development Company, L.P. System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain
US7085952B2 (en) * 2001-09-14 2006-08-01 Medtronic, Inc. Method and apparatus for writing data between fast and slow clock domains
JP4122204B2 (ja) * 2002-09-27 2008-07-23 松下電器産業株式会社 同期回路
US20040193931A1 (en) * 2003-03-26 2004-09-30 Akkerman Ryan L. System and method for transferring data from a first clock domain to a second clock domain
CN101199156A (zh) * 2005-06-13 2008-06-11 皇家飞利浦电子股份有限公司 利用时钟域进行数据传输的方法和接收机
KR101086426B1 (ko) 2007-01-23 2011-11-23 삼성전자주식회사 Ｉ２ｃ 컨트롤러에서 직렬 데이터 라인의 상태 변화의타이밍 제어 장치 및 그 제어 방법
US7809972B2 (en) * 2007-03-30 2010-10-05 Arm Limited Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain
US8024597B2 (en) * 2008-02-21 2011-09-20 International Business Machines Corporation Signal phase verification for systems incorporating two synchronous clock domains
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
US8089378B1 (en) * 2009-02-18 2012-01-03 Marvell Israel (M.I.S.L) Ltd. Synchronous multi-clock protocol converter
JP5483172B2 (ja) * 2009-10-19 2014-05-07 横河電機株式会社 データ転送装置およびデータ転送方法

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