JP2015514211A - エッジトリガ較正 - Google Patents

エッジトリガ較正 Download PDF

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Publication number
JP2015514211A
JP2015514211A JP2015503227A JP2015503227A JP2015514211A JP 2015514211 A JP2015514211 A JP 2015514211A JP 2015503227 A JP2015503227 A JP 2015503227A JP 2015503227 A JP2015503227 A JP 2015503227A JP 2015514211 A JP2015514211 A JP 2015514211A
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JP
Japan
Prior art keywords
input
circuit
edge
output
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015503227A
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English (en)
Japanese (ja)
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JP2015514211A5 (enExample
Inventor
ファンデルファグト、ジャン・ポール・アンソニー
サルツケフ、ロナルド・エイ
カンナル、グレゴリー・エイ
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Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of JP2015514211A publication Critical patent/JP2015514211A/ja
Publication of JP2015514211A5 publication Critical patent/JP2015514211A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2015503227A 2012-03-28 2013-03-05 エッジトリガ較正 Pending JP2015514211A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201213433154A 2012-03-28 2012-03-28
US13/433,154 2012-03-28
US13/450,123 2012-04-18
US13/450,123 US9147620B2 (en) 2012-03-28 2012-04-18 Edge triggered calibration
PCT/US2013/029121 WO2013148085A1 (en) 2012-03-28 2013-03-05 Edge triggered calibration

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017225875A Division JP2018054628A (ja) 2012-03-28 2017-11-24 エッジトリガ較正

Publications (2)

Publication Number Publication Date
JP2015514211A true JP2015514211A (ja) 2015-05-18
JP2015514211A5 JP2015514211A5 (enExample) 2016-03-31

Family

ID=49235557

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2015503227A Pending JP2015514211A (ja) 2012-03-28 2013-03-05 エッジトリガ較正
JP2017225875A Pending JP2018054628A (ja) 2012-03-28 2017-11-24 エッジトリガ較正

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2017225875A Pending JP2018054628A (ja) 2012-03-28 2017-11-24 エッジトリガ較正

Country Status (5)

Country Link
US (1) US9147620B2 (enExample)
JP (2) JP2015514211A (enExample)
KR (1) KR102135073B1 (enExample)
CN (1) CN104204822B (enExample)
WO (1) WO2013148085A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140046475A1 (en) * 2012-08-09 2014-02-13 Applied Materials, Inc. Method and apparatus deposition process synchronization
US9244126B2 (en) * 2013-11-06 2016-01-26 Teradyne, Inc. Automated test system with event detection capability
KR20150117775A (ko) * 2014-04-10 2015-10-21 에스케이하이닉스 주식회사 테스트 장치 및 그의 동작 방법
US10996272B2 (en) * 2014-08-27 2021-05-04 Teradyne, Inc. One-shot circuit
US11131706B2 (en) * 2015-12-08 2021-09-28 International Business Machines Corporation Degradation monitoring of semiconductor chips
US12041713B2 (en) 2017-08-23 2024-07-16 Teradyne, Inc. Reducing timing skew in a circuit path
US10276229B2 (en) 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing
CN109755147A (zh) * 2018-11-26 2019-05-14 北京铂阳顶荣光伏科技有限公司 薄膜光伏组件测试方法及薄膜光伏组件
US10761130B1 (en) 2019-04-25 2020-09-01 Teradyne, Inc. Voltage driver circuit calibration
US11119155B2 (en) 2019-04-25 2021-09-14 Teradyne, Inc. Voltage driver circuit
US11283436B2 (en) 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line
US10942220B2 (en) 2019-04-25 2021-03-09 Teradyne, Inc. Voltage driver with supply current stabilization
US11221365B2 (en) * 2020-03-11 2022-01-11 Teradyne, Inc. Calibrating an interface board
US11681324B2 (en) * 2021-10-01 2023-06-20 Achronix Semiconductor Corporation Synchronous reset deassertion circuit
US12278624B2 (en) * 2022-02-11 2025-04-15 Pratt & Whitney Canada Corp. Logic circuit for providing a signal value after a predetermined time period and method of using same
US11923853B2 (en) 2022-02-25 2024-03-05 Nvidia Corp. Circuit structures to measure flip-flop timing characteristics
CN118409627B (zh) * 2024-06-26 2024-09-27 悦芯科技股份有限公司 一种用于存储芯片ft测试机的校准板卡方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147371A (ja) * 1985-12-20 1987-07-01 Advantest Corp パルス幅測定器
JPH02198375A (ja) * 1989-01-27 1990-08-06 Advantest Corp Ｉｃ試験装置
JP2002260396A (ja) * 2001-03-02 2002-09-13 Kawasaki Microelectronics Kk 半導体記憶装置
JP2007243964A (ja) * 2006-02-02 2007-09-20 Sharp Corp パルス発生回路、半導体集積回路、及び、そのテスト方法

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
JPS52144253A (en) * 1976-05-27 1977-12-01 Mitsubishi Electric Corp Flip-flop circuit
IT1204621B (it) * 1987-05-15 1989-03-10 Montedison Spa Circuito flip-flop rs asincrono con scatto comandato dalle transizioni applicate agli ingressi
JPH01144719A (ja) * 1987-11-30 1989-06-07 Toshiba Corp リトリガブル・マルチバイブレータ
JPH02214325A (ja) * 1989-02-15 1990-08-27 Nec Corp フリップフロップ回路
JPH0537306A (ja) * 1991-07-30 1993-02-12 Nec Corp フリツプフロツプ回路
JP3080701B2 (ja) * 1991-08-06 2000-08-28 日本電気アイシーマイコンシステム株式会社 セットリセット型フリップフロップ回路
JPH0548399A (ja) 1991-08-08 1993-02-26 Fujitsu Ltd 半導体装置
SE507139C2 (sv) * 1992-08-31 1998-04-06 Asea Brown Boveri Sätt och anordning för funktionskontroll av ljustända halvledarventilenheter i HVDC-ventilanläggningar
JP3688392B2 (ja) * 1996-05-31 2005-08-24 三菱電機株式会社 波形整形装置およびクロック供給装置
US6291981B1 (en) * 2000-07-26 2001-09-18 Teradyne, Inc. Automatic test equipment with narrow output pulses
US7187742B1 (en) * 2000-10-06 2007-03-06 Xilinx, Inc. Synchronized multi-output digital clock manager
US6380779B1 (en) 2001-07-12 2002-04-30 Hewlett-Packard Company Edge-triggered, self-resetting pulse generator
US7350132B2 (en) * 2003-09-10 2008-03-25 Hewlett-Packard Development Company, L.P. Nanoscale interconnection interface
US7873130B2 (en) * 2005-08-10 2011-01-18 Ludwig Lester F Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms
US7737671B2 (en) * 2005-12-05 2010-06-15 Texas Instruments Incorporated System and method for implementing high-resolution delay
US20080232146A1 (en) 2007-03-23 2008-09-25 Texas Instruments Incorporated Efficient Power Supplies and Methods for Creating Such
US7653850B2 (en) 2007-06-05 2010-01-26 Intel Corporation Delay fault detection using latch with error sampling
US7795920B2 (en) 2008-03-31 2010-09-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
JP5407551B2 (ja) * 2009-05-22 2014-02-05 富士通セミコンダクター株式会社 タイミング調整回路及びタイミング調整方法
US8228106B2 (en) * 2010-01-29 2012-07-24 Intel Mobile Communications GmbH On-chip self calibrating delay monitoring circuitry

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147371A (ja) * 1985-12-20 1987-07-01 Advantest Corp パルス幅測定器
JPH02198375A (ja) * 1989-01-27 1990-08-06 Advantest Corp Ｉｃ試験装置
JP2002260396A (ja) * 2001-03-02 2002-09-13 Kawasaki Microelectronics Kk 半導体記憶装置
JP2007243964A (ja) * 2006-02-02 2007-09-20 Sharp Corp パルス発生回路、半導体集積回路、及び、そのテスト方法

Also Published As

Publication number Publication date
CN104204822A (zh) 2014-12-10
JP2018054628A (ja) 2018-04-05
US20130260485A1 (en) 2013-10-03
US9147620B2 (en) 2015-09-29
CN104204822B (zh) 2017-05-03
KR102135073B1 (ko) 2020-07-20
KR20140136983A (ko) 2014-12-01
WO2013148085A1 (en) 2013-10-03

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