JP2015505160A - 低減されたトランジスタリーク電流のためのゲート丸め - Google Patents

低減されたトランジスタリーク電流のためのゲート丸め Download PDF

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Publication number
JP2015505160A
JP2015505160A JP2014546267A JP2014546267A JP2015505160A JP 2015505160 A JP2015505160 A JP 2015505160A JP 2014546267 A JP2014546267 A JP 2014546267A JP 2014546267 A JP2014546267 A JP 2014546267A JP 2015505160 A JP2015505160 A JP 2015505160A
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JP
Japan
Prior art keywords
gate
region
tip
tips
main
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Pending
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JP2014546267A
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English (en)
Japanese (ja)
Inventor
カイ、ヤンフェイ
リ、ジ
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Qualcomm Inc
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Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2015505160A publication Critical patent/JP2015505160A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D64/013—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2014546267A 2011-12-14 2011-12-14 低減されたトランジスタリーク電流のためのゲート丸め Pending JP2015505160A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/083934 WO2013086693A1 (en) 2011-12-14 2011-12-14 Gate rounding for reduced transistor leakage current

Publications (1)

Publication Number Publication Date
JP2015505160A true JP2015505160A (ja) 2015-02-16

Family

ID=48611805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014546267A Pending JP2015505160A (ja) 2011-12-14 2011-12-14 低減されたトランジスタリーク電流のためのゲート丸め

Country Status (7)

Country Link
US (1) US9153659B2 (cg-RX-API-DMAC10.html)
EP (1) EP2791974A4 (cg-RX-API-DMAC10.html)
JP (1) JP2015505160A (cg-RX-API-DMAC10.html)
KR (1) KR101858545B1 (cg-RX-API-DMAC10.html)
CN (1) CN103988309A (cg-RX-API-DMAC10.html)
IN (1) IN2014CN03984A (cg-RX-API-DMAC10.html)
WO (1) WO2013086693A1 (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024500117A (ja) * 2020-12-29 2024-01-04 蘇州能訊高能半導体有限公司 半導体装置およびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN2014CN03984A (cg-RX-API-DMAC10.html) 2011-12-14 2015-10-23 Qualcomm Inc
US10417369B2 (en) * 2017-05-26 2019-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, corresponding mask and method for generating layout of same
US10468490B2 (en) * 2017-11-09 2019-11-05 Nanya Technology Corporation Transistor device and semiconductor layout structure
US11183576B2 (en) * 2019-02-13 2021-11-23 Micron Technology, Inc. Gate electrode layout with expanded portions over active and isolation regions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156778A (ja) * 2004-11-30 2006-06-15 Matsushita Electric Ind Co Ltd 半導体装置及びそのレイアウト設計方法
JP2007121867A (ja) * 2005-10-31 2007-05-17 Fujitsu Ltd パターンレイアウト及びレイアウトデータの生成方法
WO2010021785A1 (en) * 2008-08-19 2010-02-25 Freescale Semiconductor Inc. Transistor with gain variation compensation
JP2011129550A (ja) * 2009-12-15 2011-06-30 Renesas Electronics Corp 半導体集積回路装置

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US5874754A (en) * 1993-07-01 1999-02-23 Lsi Logic Corporation Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates
US5742086A (en) * 1994-11-02 1998-04-21 Lsi Logic Corporation Hexagonal DRAM array
US5973376A (en) * 1994-11-02 1999-10-26 Lsi Logic Corporation Architecture having diamond shaped or parallelogram shaped cells
US7008832B1 (en) * 2000-07-20 2006-03-07 Advanced Micro Devices, Inc. Damascene process for a T-shaped gate electrode
US6630388B2 (en) 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6974998B1 (en) * 2001-09-19 2005-12-13 Altera Corporation Field effect transistor with corner diffusions for reduced leakage
CN1310337C (zh) 2003-01-08 2007-04-11 台湾积体电路制造股份有限公司 隧道偏压金属氧化物半导体晶体管
US6876042B1 (en) * 2003-09-03 2005-04-05 Advanced Micro Devices, Inc. Additional gate control for a double-gate MOSFET
JP4598483B2 (ja) * 2004-11-10 2010-12-15 パナソニック株式会社 半導体装置およびその製造方法
US7595523B2 (en) * 2007-02-16 2009-09-29 Power Integrations, Inc. Gate pullback at ends of high-voltage vertical transistor structure
US8283221B2 (en) * 2010-01-25 2012-10-09 Ishiang Shih Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits
CN102184955B (zh) * 2011-04-07 2012-12-19 清华大学 互补隧道穿透场效应晶体管及其形成方法
US9065749B2 (en) 2011-11-21 2015-06-23 Qualcomm Incorporated Hybrid networking path selection and load balancing
IN2014CN03984A (cg-RX-API-DMAC10.html) 2011-12-14 2015-10-23 Qualcomm Inc

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156778A (ja) * 2004-11-30 2006-06-15 Matsushita Electric Ind Co Ltd 半導体装置及びそのレイアウト設計方法
JP2007121867A (ja) * 2005-10-31 2007-05-17 Fujitsu Ltd パターンレイアウト及びレイアウトデータの生成方法
WO2010021785A1 (en) * 2008-08-19 2010-02-25 Freescale Semiconductor Inc. Transistor with gain variation compensation
JP2011129550A (ja) * 2009-12-15 2011-06-30 Renesas Electronics Corp 半導体集積回路装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024500117A (ja) * 2020-12-29 2024-01-04 蘇州能訊高能半導体有限公司 半導体装置およびその製造方法
JP7709528B2 (ja) 2020-12-29 2025-07-16 蘇州能訊高能半導体有限公司 半導体装置およびその製造方法

Also Published As

Publication number Publication date
KR101858545B1 (ko) 2018-05-17
KR20140105007A (ko) 2014-08-29
IN2014CN03984A (cg-RX-API-DMAC10.html) 2015-10-23
US9153659B2 (en) 2015-10-06
EP2791974A1 (en) 2014-10-22
CN103988309A (zh) 2014-08-13
WO2013086693A1 (en) 2013-06-20
EP2791974A4 (en) 2015-08-05
US20140346606A1 (en) 2014-11-27

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