JP2015502669A - オプトエレクトロニクス半導体素子の製造方法、導体フレーム結合体及びオプトエレクトロニクス半導体素子 - Google Patents
オプトエレクトロニクス半導体素子の製造方法、導体フレーム結合体及びオプトエレクトロニクス半導体素子 Download PDFInfo
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Abstract
Description
−複数の導体フレームを含む導体フレーム結合体を準備するステップ。ここで、各導体フレームは各半導体素子に対して一つずつ設けられており、且つ、少なくとも二つの導体フレーム部を有しており、また、各導体フレームは接続ウェブを介して少なくとも部分的に相互に電気的に接続されている、
−付加的な電気的な接続手段、特にボンディングワイヤを隣接する導体フレーム間に取り付けるステップ、
−個々の半導体素子のケーシングボディのための注型ボディを作製するステップ。ここで、注型ボディは、導体フレーム及び導体フレーム部を相互に機械的に接続する、
−接続ウェブの少なくとも一部を除去及び/又は分断するステップ。
−複数の半導体素子に個別化するステップ。
Claims (14)
- オプトエレクトロニクス半導体素子(1)の製造方法において、
複数の導体フレーム(3)を含む導体フレーム結合体(2)を準備するステップであって、各導体フレーム(3)は、各半導体素子(1)に対して一つずつ設けられており、少なくとも二つの導体フレーム部(34,38)を有しており、且つ、各導体フレーム(3)は接続ウェブ(6)を介して少なくとも部分的に相互に接続されているステップと、
付加的な電気的な接続手段(4)を隣接する導体フレーム(3)間に取り付けるステップと、
個々の半導体素子(1)のケーシングボディ(5)のための注型ボディ(50)を作製するステップであって、前記注型ボディ(50)は、複数の前記導体フレーム(3)を相互に機械的に接続し、且つ、複数の前記導体フレーム部(34,38)を相互に機械的に接続するステップと、
前記接続ウェブ(6)の少なくとも一部を除去及び/又は分断するステップと、
複数の半導体素子(1)に個別化するステップと、
を備えていることを特徴とする、方法。 - 前記接続ウェブ(6)の少なくとも一部を除去するステップの後に、各導体フレーム(3)における複数の前記導体フレーム部(34,38)は相互に直接的に電気的には接触しておらず、
第1の導体フレーム部(38)は列(C)を成すよう電気的に接続されており、且つ、第2の導体フレーム部(34)は行(R)を成すよう電気的に接続されており、
隣接する行(R)は相互に電気的に絶縁されており、且つ、隣接する列(C)は相互に電気的に絶縁されている、請求項1に記載の方法。 - 前記注型ボディ(50)を作製するステップを、前記電気的な接続手段(4)を取り付けるステップの後、且つ、前記接続ウェブ(6)の少なくとも一部を除去するステップの前に実施する、請求項1又は2に記載の方法。
- 前記接続ウェブ(6)の一部を除去するステップの際に除去される接続ウェブ(6)は、前記導体フレーム部(34,38)よりも薄い平均厚さを有しており、且つ、前記導体フレーム結合体(2)の、前記接続手段(4)側とは反対側の下面(20)において、前記導体フレーム部(34,38)と面一で終端している、請求項1乃至3のいずれか一項に記載の方法。
- 前記接続手段(4)はボンディングワイヤであり、
前記接続手段(4)を前記個別化の際に部分的又は完全に除去する、請求項1乃至4のいずれか一項に記載の方法。 - 静電放電による損傷に対する保護ダイオード(7)を取り付けるステップを更に備えており、
該ステップを、前記注型ボディ(50)を作製するステップの前に実施し、続けて前記保護ダイオード(7)を前記注型ボディ(50)によって覆う、請求項1乃至5のいずれか一項に記載の方法。 - 発光ダイオードチップ(8)を、各導体フレーム部(38)に、又は各導体フレーム(3)の各二つの導体フレーム部(34,38)に取り付けるステップを更に備えており、
該ステップを、前記注型ボディ(50)を作製するステップの後、且つ、前記個別化の前に実施する、請求項1乃至6のいずれか一項に記載の方法。 - 隣接する二つの第1の導体フレーム部(38)の間において、前記列(C)に沿って、第1の接続ウェブ(6a)が設けられており、
該第1の接続ウェブ(6a)を前記個別化の際に部分的又は完全に除去する、請求項7に記載の方法。 - まだ個別化されていない半導体素子(1)を電気的に検査するステップを更に備えており、
該検査の際に、前記発光ダイオードチップ(8)及び/又は前記保護ダイオード(7)は、行毎及び列毎に相互に独立して給電可能である、請求項1乃至8のいずれか一項に記載の方法。 - 前記接続ウェブ(6)の一部を除去するステップの後に残存している接続ウェブ(6)を、前記注型ボディ(50)を作製する際に、前記導体フレーム結合体(2)の、前記接続手段(4)側とは反対側の下面(20)において前記注型ボディ(50)の材料と接触させ、且つ、前記下面(20)に対して垂直な方向における平面において、前記注型ボディの材料によって周囲を包囲する、請求項1乃至9のいずれか一項に記載の方法。
- 前記導体フレーム結合体(2)を二つの主面(20,25)側からエッチングする、請求項1乃至10のいずれか一項に記載の方法。
- 前記下面(20)側からのエッチングを、前記注型ボディ(50)を作製するステップの前後に実施し、
前記下面(20)とは反対側の上面(25)側からのエッチングを、前記接続手段(4)を取り付けるステップの前にのみ実施する、請求項11に記載の方法。 - 複数の導体フレーム(3)を備えているオプトエレクトロニクス半導体素子(1)のための導体フレーム結合体(2)において、
前記導体フレーム結合体(2)はワンピースであり、
前記導体フレーム(3)はマトリクス状に前記導体フレーム結合体(2)に配置されており、
前記導体フレーム(3)は各半導体素子(1)に対して一つずつ設けられており、
前記導体フレーム(3)はそれぞれ少なくとも一つの第1の導体フレーム部(38)と少なくとも一つの第2の導体フレーム部(34)とを含んでおり、
少なくとも、前記第1の導体フレーム部(38)は、一つの発光ダイオードチップ(8)を取り付けるために設けられており、
前記導体フレーム結合体(2)は複数の接続ウェブ(6)を含んでおり、
前記導体フレーム(3)は少なくとも部分的に、前記接続ウェブ(6)を介して電気的且つ機械的に相互に接続されており、
隣接する第1の導体フレーム部(38)間には第1の接続ウェブ(6a)が設けられており、
前記第1の接続ウェブ(6a)はそれぞれ、前記導体フレーム(3)の前記第1の導体フレーム部(38)と前記第2の導体フレーム部(34)との間の接続線に平行に延在しており、
前記接続ウェブ(6,6a)は前記導体フレーム部(34,38)とは異なる、
ことを特徴とする、導体フレーム結合体(2)。 - オプトエレクトロニクス半導体素子(1)において、
少なくとも一つの第1の導体フレーム部(38)及び少なくとも一つの第2の導体フレーム部(32)を備えている導体フレーム(3)と、
少なくとも前記第1の導体フレーム部(38)に固定されている少なくとも一つの発光ダイオードチップ(8)と、
前記導体フレーム部(32,38)を相互に機械的に接続し、且つ開口部(58)を有しているケーシングボディ(5)と、
ボンディングワイヤである少なくとも一つの電気的な接続手段(4)とを備えており、
前記半導体チップ(8)は前記開口部(58)内に設けられており、
前記導体フレーム部(32、38)は、半導体素子(1)の実装のために設けられている実装面(20)においてのみ前記ケーシングボディ(5)から突出しているか、又は、前記ケーシングボディ(5)と面一で終端しており、
前記ケーシングボディ(5)の少なくとも一つの側面(54)において前記接続手段(4)に自由にアクセスすることができ、前記側面(54)を平面で見て、前記接続手段(4)の周囲は前記ケーシングボディ(5)の材料によって包囲されていることを特徴とする、オプトエレクトロニクス半導体素子(1)。
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