JP2015501532A5 - - Google Patents

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Publication number
JP2015501532A5
JP2015501532A5 JP2014534632A JP2014534632A JP2015501532A5 JP 2015501532 A5 JP2015501532 A5 JP 2015501532A5 JP 2014534632 A JP2014534632 A JP 2014534632A JP 2014534632 A JP2014534632 A JP 2014534632A JP 2015501532 A5 JP2015501532 A5 JP 2015501532A5
Authority
JP
Japan
Prior art keywords
microelectronic
package
terminal
terminals
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2014534632A
Other languages
English (en)
Japanese (ja)
Other versions
JP5857130B2 (ja
JP2015501532A (ja
Filing date
Publication date
Priority claimed from US13/440,290 external-priority patent/US8659142B2/en
Application filed filed Critical
Priority claimed from PCT/US2012/058407 external-priority patent/WO2013052448A1/en
Publication of JP2015501532A publication Critical patent/JP2015501532A/ja
Publication of JP2015501532A5 publication Critical patent/JP2015501532A5/ja
Application granted granted Critical
Publication of JP5857130B2 publication Critical patent/JP5857130B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014534632A 2011-10-03 2012-10-02 窓なしのワイヤボンドアセンブリのためのスタブ最小化 Active JP5857130B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201161542488P 2011-10-03 2011-10-03
US201161542553P 2011-10-03 2011-10-03
US61/542,488 2011-10-03
US61/542,553 2011-10-03
US201261600271P 2012-02-17 2012-02-17
US61/600,271 2012-02-17
US13/440,290 US8659142B2 (en) 2011-10-03 2012-04-05 Stub minimization for wirebond assemblies without windows
US13/440,290 2012-04-05
PCT/US2012/058407 WO2013052448A1 (en) 2011-10-03 2012-10-02 Stub minimization for wirebond assemblies without windows

Publications (3)

Publication Number Publication Date
JP2015501532A JP2015501532A (ja) 2015-01-15
JP2015501532A5 true JP2015501532A5 (enExample) 2015-11-19
JP5857130B2 JP5857130B2 (ja) 2016-02-10

Family

ID=47146660

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014534623A Active JP5857129B2 (ja) 2011-10-03 2012-10-01 窓なしのワイヤボンドアセンブリのためのスタブ最小化
JP2014534632A Active JP5857130B2 (ja) 2011-10-03 2012-10-02 窓なしのワイヤボンドアセンブリのためのスタブ最小化

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2014534623A Active JP5857129B2 (ja) 2011-10-03 2012-10-01 窓なしのワイヤボンドアセンブリのためのスタブ最小化

Country Status (5)

Country Link
EP (2) EP2766931B1 (enExample)
JP (2) JP5857129B2 (enExample)
KR (2) KR101945334B1 (enExample)
TW (3) TWI459537B (enExample)
WO (3) WO2013052411A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR112015021244A2 (en) 2014-10-03 2018-05-08 Intel Coproration stacked stacked matrix package with vertical columns
KR102497239B1 (ko) * 2015-12-17 2023-02-08 삼성전자주식회사 고속 신호 특성을 갖는 반도체 모듈
JP7353729B2 (ja) 2018-02-09 2023-10-02 キヤノン株式会社 半導体装置、半導体装置の製造方法
US11227846B2 (en) * 2019-01-30 2022-01-18 Mediatek Inc. Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
US11587919B2 (en) 2020-07-17 2023-02-21 Micron Technology, Inc. Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
JP3685947B2 (ja) * 1999-03-15 2005-08-24 新光電気工業株式会社 半導体装置及びその製造方法
JP2000315776A (ja) * 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6713854B1 (en) * 2000-10-16 2004-03-30 Legacy Electronics, Inc Electronic circuit module with a carrier having a mounting pad array
WO2001071806A1 (en) * 2000-03-21 2001-09-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, method of manufacturing electronic device, electronic device, and portable information terminal
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
DE10055001A1 (de) * 2000-11-07 2002-05-16 Infineon Technologies Ag Speicheranordnung mit einem zentralen Anschlussfeld
DE10139085A1 (de) 2001-08-16 2003-05-22 Infineon Technologies Ag Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung
JP3785083B2 (ja) * 2001-11-07 2006-06-14 株式会社東芝 半導体装置、電子カード及びパッド再配置基板
JP2004128155A (ja) * 2002-10-01 2004-04-22 Renesas Technology Corp 半導体パッケージ
JP2004221215A (ja) * 2003-01-14 2004-08-05 Renesas Technology Corp 半導体装置
US7260691B2 (en) 2004-06-30 2007-08-21 Intel Corporation Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins
US7372169B2 (en) 2005-10-11 2008-05-13 Via Technologies, Inc. Arrangement of conductive pads on grid array package and on circuit board
JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
DE102006042775B3 (de) 2006-09-12 2008-03-27 Qimonda Ag Schaltungsmodul und Verfahren zur Herstellung eines Schaltungsmoduls
JP4913640B2 (ja) * 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
TW200842998A (en) * 2007-04-18 2008-11-01 Siliconware Precision Industries Co Ltd Semiconductor device and manufacturing method thereof
US8228679B2 (en) * 2008-04-02 2012-07-24 Spansion Llc Connections for electronic devices on double-sided circuit board
KR20100020772A (ko) * 2008-08-13 2010-02-23 주식회사 하이닉스반도체 반도체 패키지
KR20100046760A (ko) 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US8304286B2 (en) * 2009-12-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with shielded package and method of manufacture thereof

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