TWI511264B - 用於無窗之導線接合總成之短線最小化 - Google Patents

用於無窗之導線接合總成之短線最小化 Download PDF

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TWI511264B
TWI511264B TW101136606A TW101136606A TWI511264B TW I511264 B TWI511264 B TW I511264B TW 101136606 A TW101136606 A TW 101136606A TW 101136606 A TW101136606 A TW 101136606A TW I511264 B TWI511264 B TW I511264B
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Prior art keywords
microelectronic
semiconductor wafer
package
terminals
contacts
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TW101136606A
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English (en)
Chinese (zh)
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TW201322417A (zh
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理查 狄威特 柯斯伯
華爾 柔伊
畢哥辛 哈芭
法蘭克 藍布里奇
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英帆薩斯公司
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Priority claimed from US13/440,299 external-priority patent/US8659143B2/en
Application filed by 英帆薩斯公司 filed Critical 英帆薩斯公司
Publication of TW201322417A publication Critical patent/TW201322417A/zh
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
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    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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JP2014534625A (ja) 2014-12-18
EP2764545B1 (en) 2018-07-04
TWI459537B (zh) 2014-11-01
WO2013052441A3 (en) 2013-08-15
TW201324734A (zh) 2013-06-16
TWI491015B (zh) 2015-07-01
TW201322417A (zh) 2013-06-01
KR20140085489A (ko) 2014-07-07
KR20140085490A (ko) 2014-07-07
EP2764545A1 (en) 2014-08-13
KR101945334B1 (ko) 2019-02-07
KR101895017B1 (ko) 2018-10-04
JP5857130B2 (ja) 2016-02-10
TW201322415A (zh) 2013-06-01
WO2013052448A1 (en) 2013-04-11
WO2013052411A1 (en) 2013-04-11
JP5857129B2 (ja) 2016-02-10
JP2015501532A (ja) 2015-01-15
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WO2013052411A4 (en) 2013-07-04
EP2766931B1 (en) 2021-12-01

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