JP2015177170A - ウェーハの加工方法 - Google Patents
ウェーハの加工方法 Download PDFInfo
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- JP2015177170A JP2015177170A JP2014054955A JP2014054955A JP2015177170A JP 2015177170 A JP2015177170 A JP 2015177170A JP 2014054955 A JP2014054955 A JP 2014054955A JP 2014054955 A JP2014054955 A JP 2014054955A JP 2015177170 A JP2015177170 A JP 2015177170A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Abstract
【解決手段】本発明の加工方法は、デバイス形成領域(A1)に対応する裏面(12)のみを研削することで、デバイス形成領域を囲繞する外周余剰領域(A2)に対応する裏面に補強用の環状凸部(16)が形成されたウェーハ(W)を分割するものであり、ウェーハの表面に保護テープ(T1)を貼着させた状態でウェーハの環状凸部と凹部(15)の境界に分割溝(17)を形成し、ウェーハの裏面側にダイシングテープ(T2)を貼着すると共にウェーハの表面から保護テープ及び環状凸部を除去し、ウェーハのデバイス形成領域を個々のデバイス(D)に分割するように構成した。
【選択図】図4
Description
12 ウェーハの裏面
15 凹部
16 環状凸部
17 分割溝
18 分割予定ライン
A1 デバイス形成領域
A2 外周余剰領域
T1 保護テープ
T2 ダイシングテープ
D デバイス
W ウェーハ
Claims (1)
- 表面に複数のデバイスが分割予定ラインによって形成された略円形状のデバイス形成領域と、該デバイス形成領域を囲繞する外周余剰領域とを有するウェーハの加工方法であって、
ウェーハ表面側に保護テープを貼着し、ウェーハの該デバイス形成領域に対応する裏面側の領域のみを所定厚さ研削して該デバイス形成領域を所望厚さに薄化し、該裏面に凹部を形成するとともに、該外周余剰領域に裏面側に突出する環状凸部を形成する凹部形成工程と、
該凹部形成工程を実施した後に、該環状凸部と該凹部の境界に円形の分割溝を形成し該環状凸部と該凹部を分割する環状凸部分割工程と、
該環状凸部分割工程を実施した後に、ウェーハの裏面の該分割溝の内側全面にダイシングテープを貼着すると共に該保護テープを剥離し該環状凸部を除去する転写工程と、
該転写工程を実施した後に、該デバイス形成領域の分割予定ラインに沿って分割を行うデバイス形成領域分割工程と、
からなるウェーハの加工方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014054955A JP6341709B2 (ja) | 2014-03-18 | 2014-03-18 | ウェーハの加工方法 |
TW104104558A TWI640036B (zh) | 2014-03-18 | 2015-02-11 | 晶圓之加工方法 |
CN201510113149.5A CN104934309B (zh) | 2014-03-18 | 2015-03-16 | 晶片的加工方法 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2014054955A JP6341709B2 (ja) | 2014-03-18 | 2014-03-18 | ウェーハの加工方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015177170A true JP2015177170A (ja) | 2015-10-05 |
JP6341709B2 JP6341709B2 (ja) | 2018-06-13 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014054955A Active JP6341709B2 (ja) | 2014-03-18 | 2014-03-18 | ウェーハの加工方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP6341709B2 (ja) |
CN (1) | CN104934309B (ja) |
TW (1) | TWI640036B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105428220A (zh) * | 2015-12-22 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | 太鼓减薄工艺的环切工艺方法 |
EP3346503A1 (en) | 2017-01-10 | 2018-07-11 | Renesas Electronics Corporation | Semiconductor device manufacturing method and semiconductor wafer |
CN109979878A (zh) * | 2017-12-28 | 2019-07-05 | 株式会社迪思科 | 被加工物的加工方法 |
CN111987146A (zh) * | 2020-09-21 | 2020-11-24 | 上海擎茂微电子科技有限公司 | 一种用于制备半导体器件的晶圆及晶圆的背面减薄方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6854707B2 (ja) * | 2017-06-02 | 2021-04-07 | 株式会社ディスコ | ウエーハの加工方法 |
JP7049801B2 (ja) * | 2017-10-12 | 2022-04-07 | 株式会社ディスコ | 被加工物の研削方法 |
DE102018202254A1 (de) * | 2018-02-14 | 2019-08-14 | Disco Corporation | Verfahren zum Bearbeiten eines Wafers |
JP7218055B2 (ja) * | 2019-01-25 | 2023-02-06 | 株式会社ディスコ | チャックテーブル |
CN112475627A (zh) * | 2020-11-17 | 2021-03-12 | 华虹半导体(无锡)有限公司 | Taiko减薄晶圆的去环方法 |
CN114536215A (zh) * | 2022-04-27 | 2022-05-27 | 绍兴中芯集成电路制造股份有限公司 | 取环装置及方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008283025A (ja) * | 2007-05-11 | 2008-11-20 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
JP2011049431A (ja) * | 2009-08-28 | 2011-03-10 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5356890B2 (ja) * | 2009-04-02 | 2013-12-04 | 株式会社ディスコ | ウェーハの加工方法 |
JP5500942B2 (ja) * | 2009-10-28 | 2014-05-21 | 株式会社ディスコ | ウエーハの加工方法 |
-
2014
- 2014-03-18 JP JP2014054955A patent/JP6341709B2/ja active Active
-
2015
- 2015-02-11 TW TW104104558A patent/TWI640036B/zh active
- 2015-03-16 CN CN201510113149.5A patent/CN104934309B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008283025A (ja) * | 2007-05-11 | 2008-11-20 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
JP2011049431A (ja) * | 2009-08-28 | 2011-03-10 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105428220A (zh) * | 2015-12-22 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | 太鼓减薄工艺的环切工艺方法 |
EP3346503A1 (en) | 2017-01-10 | 2018-07-11 | Renesas Electronics Corporation | Semiconductor device manufacturing method and semiconductor wafer |
KR20180082334A (ko) | 2017-01-10 | 2018-07-18 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치의 제조 방법 및 반도체 웨이퍼 |
US10741504B2 (en) | 2017-01-10 | 2020-08-11 | Renesas Electronics Corporation | Semiconductor device manufacturing method and semiconductor wafer |
CN109979878A (zh) * | 2017-12-28 | 2019-07-05 | 株式会社迪思科 | 被加工物的加工方法 |
JP2019121653A (ja) * | 2017-12-28 | 2019-07-22 | 株式会社ディスコ | 被加工物の加工方法 |
JP7084718B2 (ja) | 2017-12-28 | 2022-06-15 | 株式会社ディスコ | 被加工物の加工方法 |
CN109979878B (zh) * | 2017-12-28 | 2024-02-09 | 株式会社迪思科 | 被加工物的加工方法 |
CN111987146A (zh) * | 2020-09-21 | 2020-11-24 | 上海擎茂微电子科技有限公司 | 一种用于制备半导体器件的晶圆及晶圆的背面减薄方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104934309A (zh) | 2015-09-23 |
JP6341709B2 (ja) | 2018-06-13 |
TWI640036B (zh) | 2018-11-01 |
TW201539562A (zh) | 2015-10-16 |
CN104934309B (zh) | 2019-05-31 |
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