JP2015172960A - 原子メモリ装置 - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2024—Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
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Abstract
Description
Claims (27)
- 集積回路メモリ装置内の動作方法であって、
メモリアクセスコマンドに応じて、前記メモリ装置のメモリコア内におけるアドレス指定された位置から第1のデータ値を検索すること、
前記メモリアクセスコマンドに応じて、前記メモリ装置から前記第1のデータ値を出力すること、および、
前記メモリアクセスコマンドに応じて、前記メモリコア内の前記アドレス指定された位置に第2のデータ値を記憶すること、
を含む方法。 - 前記メモリ装置のメモリコア内におけるアドレス指定された位置から第1のデータ値を検索することが、前記メモリ装置のセンス増幅器バンク内のセンス増幅器の列から第1のデータ値を検索することを含む、請求項1に記載の方法。
- 前記メモリアクセスコマンドの受信前に実行される行アクティブ動作において、記憶セルの行から前記センス増幅器バンクにデータを転送することをさらに含み、前記記憶セルの行が、前記メモリコア内の記憶アレイの一部を形成する、請求項2に記載の方法。
- 前記メモリコア内の前記アドレス指定された位置に第2のデータ値を記憶することが、前記センス増幅器の列内に前記第2の値を記憶することを含む、請求項2に記載の方法。
- 前記メモリアクセスコマンドに応じて、前記メモリ装置から前記第1のデータ値を出力することが、前記メモリ装置外のデータ経路上に前記第1のデータ値を出力することを含む、請求項1に記載の方法。
- 前記メモリアクセスコマンドに応じて前記第1のデータ値を修正して、前記第2のデータ値を生成することをさらに含む、請求項1に記載の方法。
- 前記第1のデータ値を修正することが、前記第2のデータ値が前記第1のデータ値のインクリメントされたバージョンであるように、前記メモリアクセスコマンドに応じて前記第1のデータ値をインクリメントすることを含む、請求項6に記載の方法。
- 前記第1のデータ値を修正することが、前記第1のデータ値が第1のオペランドを構成しかつ第3のデータ値が第2のオペランド構成する論理演算を実行することを含む、請求項6に記載の方法。
- 前記メモリ装置内のレジスタから前記第3のデータ値を受信することをさらに含む、請求項8に記載の方法。
- 外部データ経路を介して前記第3のデータ値を受信することをさらに含む、請求項8に記載の方法。
- 外部データ経路を介して前記第3のデータ値を受信することが、外部コマンド経路を介して前記メモリアクセスコマンドを受信するのと平行して、前記外部データ経路を介して前記第3のデータ値を受信することを含む、請求項10に記載の方法。
- 前記論理演算が算術演算を含む、請求項8に記載の方法。
- 前記メモリ装置から前記第1のデータ値を出力する前に、外部データ経路を介して前記第2のデータ値を受信することをさらに含み、前記メモリ装置から前記第1のデータ値を出力することが、前記外部データ経路を介して前記第1のデータ値を出力することを含む、請求項1に記載の方法。
- 前記第1のデータ値を前記第2と比較して比較結果を生成することをさらに含み、前記メモリコア内の前記アドレス指定された位置に前記第2のデータ値を記憶することが、前記比較結果に従って前記アドレス指定された位置に前記第2のデータ値を条件付きで記憶することを含む、請求項1に記載の方法。
- 前記比較結果に従って前記アドレス指定された位置に前記第2のデータ値を条件付きで記憶することが、前記第2のデータ値の態様が前記第1のデータ値の対応する態様を超えることを前記比較結果が示す場合にのみ、前記アドレス指定された位置に前記第2のデータ値を記憶することを含む、請求項14に記載の方法。
- メモリコアと、
メモリアクセスコマンドに応じて、前記メモリコア内のアドレス指定された位置から第1のデータ値を検索し、かつ前記メモリアクセスコマンドに応じて、前記メモリコア内の前記アドレス指定された位置に第2のデータ値を記憶するコアアクセス回路と、
を含む集積回路メモリ装置。 - 前記コアアクセス回路が、
前記メモリアクセスコマンドおよび対応するメモリアドレスを受信し、かつ前記メモリアクセスコマンドおよび対応するメモリアドレスに応じて、前記アドレス指定された位置へのアクセスを可能にする制御論理と、
前記制御論理を介して、前記メモリコアにおける前記アドレス指定された位置から前記第1のデータ値を受信し、かつ前記集積回路メモリ装置から前記第1のデータ値を出力するデータ入力/出力(I/O)回路と、
を含む、請求項16に記載の集積回路メモリ装置。 - 前記データI/O回路が、前記メモリアクセスコマンドに応じ、外部シグナリング経路を介して前記第2のデータ値を受信するデータ受信回路を含む、請求項17に記載の集積回路装置。
- 前記データI/O回路が、前記メモリアクセスコマンドに関連する外部シグナリング経路を介して第3のデータ値を受信するデータ受信回路と、前記データ受信回路から前記第3のデータ値を受信し、かつ前記メモリコアから前記第1のデータ値を受信するように結合された修正論理回路と、を含み、前記修正論理回路が、前記第1および第3のデータ値を用いて前記第2のデータを生成する回路を含む、請求項17に記載の集積回路装置。
- 前記データI/O回路が、前記メモリコアから前記第1のデータ値を受信するように結合された修正論理回路であって、前記第1のデータ値を修正することによって前記第2のデータ値を生成する回路を有する修正論理回路を含む、請求項17に記載の集積回路メモリ装置。
- 前記データI/O回路が、前記メモリアクセスコマンドに応じ、外部シグナリング経路を介して前記第2のデータ値を受信するデータ受信回路を含む、請求項17に記載の集積回路メモリ装置。
- 前記データ受信回路から前記第2のデータ値を受信し、かつ前記メモリコアから前記第1のデータ値を受信するように結合された修正論理をさらに含み、前記修正論理回路が、前記第1および第2のデータ値を比較して比較結果を生成し、かつ前記比較結果に依存して、前記メモリコア内の前記アドレス指定された位置に前記第2のデータ値を条件付きで記憶できるようにする回路を含む、請求項21に記載の集積回路メモリ装置。
- 前記メモリアクセスコマンドの受信前に前記第2のデータ値を記憶するレジスタをさらに含む、請求項17に記載の集積回路メモリ装置。
- 前記メモリコアが、複数のダイナミックランダムアクセスメモリセルを含む、請求項16に記載の集積回路メモリ装置。
- 前記メモリコアが、複数のフラッシュメモリセルを含む、請求項16に記載の集積回路メモリ装置。
- メモリコアと、
メモリアクセスコマンドに応じて、前記メモリコア内のアドレス指定された位置から第1のデータ値を検索するための手段と、
前記メモリアクセスコマンドに応じて、前記メモリ装置から前記第1のデータ値を出力するための手段と、
前記メモリアクセスコマンドに応じて、前記メモリコア内の前記アドレス指定された位置に第2のデータ値を記憶するための手段と、
を含む集積回路メモリ装置。 - 1つ以上のコンピュータ可読記憶媒体を含む製品であって、前記コンピュータ可読記憶媒体が、集積回路装置の物理的インプリメンテーションを説明する情報を自身に具体化し、前記情報が、
メモリコアと、
メモリアクセスコマンドに応じて、前記メモリコア内のアドレス指定された位置から第1のデータ値を検索し、かつ前記メモリアクセスコマンドに応じて、前記メモリコア内の前記アドレス指定された位置に第2のデータ値を記憶するコアアクセス回路と、
の説明を含む製品。
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US20170293552A1 (en) | 2017-10-12 |
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