JP2015133119A5 - - Google Patents

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Publication number
JP2015133119A5
JP2015133119A5 JP2015005870A JP2015005870A JP2015133119A5 JP 2015133119 A5 JP2015133119 A5 JP 2015133119A5 JP 2015005870 A JP2015005870 A JP 2015005870A JP 2015005870 A JP2015005870 A JP 2015005870A JP 2015133119 A5 JP2015133119 A5 JP 2015133119A5
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Japan
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memory
memory row
row
entry
activation
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JP2015005870A
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Japanese (ja)
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JP6463141B2 (ja
JP2015133119A (ja
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Priority claimed from US14/560,674 external-priority patent/US9589606B2/en
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JP2015005870A 2014-01-15 2015-01-15 メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ Active JP6463141B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201461927636P 2014-01-15 2014-01-15
US61/927,636 2014-01-15
US14/560,674 US9589606B2 (en) 2014-01-15 2014-12-04 Handling maximum activation count limit and target row refresh in DDR4 SDRAM
US14/560,674 2014-12-04

Publications (3)

Publication Number Publication Date
JP2015133119A JP2015133119A (ja) 2015-07-23
JP2015133119A5 true JP2015133119A5 (enExample) 2018-02-15
JP6463141B2 JP6463141B2 (ja) 2019-01-30

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JP2015005870A Active JP6463141B2 (ja) 2014-01-15 2015-01-15 メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ

Country Status (5)

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US (1) US9589606B2 (enExample)
JP (1) JP6463141B2 (enExample)
KR (1) KR102223188B1 (enExample)
CN (1) CN104778013B (enExample)
TW (1) TWI646533B (enExample)

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KR102675313B1 (ko) * 2019-10-31 2024-06-17 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법
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KR20230065470A (ko) 2021-11-05 2023-05-12 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
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