JP6463141B2 - メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ - Google Patents

メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ Download PDF

Info

Publication number
JP6463141B2
JP6463141B2 JP2015005870A JP2015005870A JP6463141B2 JP 6463141 B2 JP6463141 B2 JP 6463141B2 JP 2015005870 A JP2015005870 A JP 2015005870A JP 2015005870 A JP2015005870 A JP 2015005870A JP 6463141 B2 JP6463141 B2 JP 6463141B2
Authority
JP
Japan
Prior art keywords
memory
row
memory row
activation
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015005870A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015133119A5 (enExample
JP2015133119A (ja
Inventor
ジアン リン，
ジアン リン，
マシュー ギャレット，
マシュー ギャレット，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2015133119A publication Critical patent/JP2015133119A/ja
Publication of JP2015133119A5 publication Critical patent/JP2015133119A5/ja
Application granted granted Critical
Publication of JP6463141B2 publication Critical patent/JP6463141B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)
JP2015005870A 2014-01-15 2015-01-15 メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ Active JP6463141B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201461927636P 2014-01-15 2014-01-15
US61/927,636 2014-01-15
US14/560,674 US9589606B2 (en) 2014-01-15 2014-12-04 Handling maximum activation count limit and target row refresh in DDR4 SDRAM
US14/560,674 2014-12-04

Publications (3)

Publication Number Publication Date
JP2015133119A JP2015133119A (ja) 2015-07-23
JP2015133119A5 JP2015133119A5 (enExample) 2018-02-15
JP6463141B2 true JP6463141B2 (ja) 2019-01-30

Family

ID=53521912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015005870A Active JP6463141B2 (ja) 2014-01-15 2015-01-15 メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ

Country Status (5)

Country Link
US (1) US9589606B2 (enExample)
JP (1) JP6463141B2 (enExample)
KR (1) KR102223188B1 (enExample)
CN (1) CN104778013B (enExample)
TW (1) TWI646533B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12175099B2 (en) 2022-07-25 2024-12-24 Samsung Electronics Co., Ltd. Semiconductor memory device and memory system including the same
US12236997B2 (en) 2022-07-25 2025-02-25 Samsung Electronics Co., Ltd. Semiconductor memory device and memory system including the same

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236110B2 (en) 2012-06-30 2016-01-12 Intel Corporation Row hammer refresh command
US9384821B2 (en) * 2012-11-30 2016-07-05 Intel Corporation Row hammer monitoring based on stored row hammer threshold value
US9286964B2 (en) * 2012-12-21 2016-03-15 Intel Corporation Method, apparatus and system for responding to a row hammer event
US9478263B2 (en) * 2014-01-17 2016-10-25 Apple Inc. Systems and methods for monitoring and controlling repetitive accesses to volatile memory
JP6224483B2 (ja) * 2014-02-26 2017-11-01 Ｎｅｃプラットフォームズ株式会社 半導体記憶装置、メモリアクセス制御方法、およびコンピュータ・プログラム
CN105159853B (zh) * 2015-09-25 2018-04-24 中国船舶重工集团公司第七0九研究所 基于fpga的dfi标准ddr3控制器
US9812185B2 (en) 2015-10-21 2017-11-07 Invensas Corporation DRAM adjacent row disturb mitigation
RU2692136C1 (ru) * 2016-02-22 2019-06-21 ДжФЕ СТИЛ КОРПОРЕЙШН Способ изготовления листа из текстурированной электротехнической стали
JP6455468B2 (ja) * 2016-03-09 2019-01-23 Ｊｆｅスチール株式会社 方向性電磁鋼板の製造方法
WO2017155057A1 (ja) * 2016-03-09 2017-09-14 Ｊｆｅスチール株式会社 方向性電磁鋼板の製造方法
US10268585B2 (en) * 2016-06-28 2019-04-23 Intel Corporation Memory controller that forces prefetches in response to a present row address change timing constraint
CN109983536B (zh) * 2016-11-29 2023-07-21 Arm有限公司 响应标签匹配命令的存储电路
JP7008410B2 (ja) * 2017-02-10 2022-01-25 キヤノン株式会社 メモリコントローラおよび方法
CN108932205B (zh) * 2017-05-25 2021-01-29 华为技术有限公司 一种防御RowHammer攻击的方法及设备
US11054995B2 (en) * 2018-09-07 2021-07-06 Micron Technology, Inc. Row hammer protection for a memory device
KR102617016B1 (ko) 2018-09-17 2023-12-27 삼성전자주식회사 자주 접근되는 어드레스를 검출하는 레지스터 클럭 드라이버를 포함하는 메모리 모듈
US10726903B2 (en) * 2018-09-21 2020-07-28 Nanya Technology Corporation Row-determining circuit, DRAM, and method for refreshing a memory array
US10825534B2 (en) * 2018-10-26 2020-11-03 Intel Corporation Per row activation count values embedded in storage cell array storage cells
US10969997B2 (en) * 2018-11-07 2021-04-06 Intel Corporation Memory controller that filters a count of row activate commands collectively sent to a set of memory banks
US10943637B2 (en) * 2018-12-27 2021-03-09 Micron Technology, Inc. Apparatus with a row-hammer address latch mechanism
EP3675125A1 (en) * 2018-12-27 2020-07-01 Secure-IC SAS Device and method for protecting a memory
KR102687575B1 (ko) 2019-01-03 2024-07-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
CN110706733A (zh) * 2019-08-13 2020-01-17 浙江工商大学 一种dram内存行扰动错误解决方法
KR102675313B1 (ko) * 2019-10-31 2024-06-17 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법
JP6975298B1 (ja) 2020-09-03 2021-12-01 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. 半導体記憶装置
EP4182800A1 (en) * 2020-09-14 2023-05-24 Google LLC Memory request timeouts using a common counter
KR102412680B1 (ko) 2020-10-20 2022-06-23 윈본드 일렉트로닉스 코포레이션 반도체 기억장치
US11474746B2 (en) * 2020-12-10 2022-10-18 Advanced Micro Devices, Inc. Refresh management for DRAM
KR20220120771A (ko) 2021-02-23 2022-08-31 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
KR102453523B1 (ko) 2021-03-10 2022-10-11 윈본드 일렉트로닉스 코포레이션 반도체 기억장치
JP7574720B2 (ja) * 2021-04-05 2024-10-29 富士通株式会社 メモリ管理装置、メモリ管理方法及びメモリ管理プログラム
KR102504489B1 (ko) 2021-04-19 2023-02-27 윈본드 일렉트로닉스 코포레이션 반도체 기억장치
KR20220145667A (ko) 2021-04-22 2022-10-31 삼성전자주식회사 적응적 구동 전압을 생성하는 위상 고정 루프 및 이의 동작 방법
KR20230056339A (ko) 2021-10-20 2023-04-27 에스케이하이닉스 주식회사 스마트 리프레쉬 동작을 수행하기 위한 메모리 장치 및 이를 포함하는 메모리 시스템
KR20230059630A (ko) 2021-10-26 2023-05-03 삼성전자주식회사 로우 해머 제어 방법 및 메모리 장치
KR20230065470A (ko) 2021-11-05 2023-05-12 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
KR102892723B1 (ko) 2021-11-17 2025-11-28 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
US12236105B2 (en) 2022-01-11 2025-02-25 Samsung Electronics Co., Ltd. Semiconductor memory devices having enhanced refresh operations that inhibit row hammer hacking
US12248567B2 (en) * 2022-01-21 2025-03-11 Micron Technology, Inc. Row hammer interrupts to the operating system
JP2023130672A (ja) * 2022-03-08 2023-09-21 ソニーセミコンダクタソリューションズ株式会社 メモリコントローラおよびメモリ制御方法
US12080334B2 (en) 2022-04-11 2024-09-03 Samsung Electronics Co., Ltd. Semiconductor memory device and memory system including the same
US12230312B2 (en) 2022-06-17 2025-02-18 Samsung Electronics Co., Ltd. Memory device and defense method thereof
KR20240016023A (ko) 2022-07-28 2024-02-06 삼성전자주식회사 메모리 장치 및 그 리프레시 방법
US12488824B2 (en) * 2022-10-03 2025-12-02 Micron Technology, Inc. Memory with deterministic worst-case row address servicing, and associated systems, devices, and methods
KR20240059151A (ko) 2022-10-27 2024-05-07 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
KR20240062601A (ko) 2022-11-02 2024-05-09 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
KR20240143291A (ko) 2023-03-24 2024-10-02 에스케이하이닉스 주식회사 카운팅 동작을 수행하는 메모리, 메모리 시스템 및 메모리의 동작 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5883849A (en) * 1997-06-30 1999-03-16 Micron Technology, Inc. Method and apparatus for simultaneous memory subarray testing
US6725337B1 (en) * 2001-05-16 2004-04-20 Advanced Micro Devices, Inc. Method and system for speculatively invalidating lines in a cache
CN100375066C (zh) * 2005-10-28 2008-03-12 中国人民解放军国防科学技术大学 基于高速缓冲存储器行偏移量实现优先读取存储器的方法
JP4208895B2 (ja) * 2006-05-30 2009-01-14 株式会社東芝 キャッシュメモリ装置および処理方法
CN101123113B (zh) * 2007-09-20 2010-07-14 上海交通大学 同步动态随机访问存储器的访问方法及控制装置
TWI367486B (en) * 2007-12-25 2012-07-01 Ind Tech Res Inst Memory device and refresh method thereof
US8195891B2 (en) * 2009-03-30 2012-06-05 Intel Corporation Techniques to perform power fail-safe caching without atomic metadata
JP2010237739A (ja) * 2009-03-30 2010-10-21 Fujitsu Ltd キャッシュ制御装置，情報処理装置およびキャッシュ制御プログラム
US9257169B2 (en) * 2012-05-14 2016-02-09 Samsung Electronics Co., Ltd. Memory device, memory system, and operating methods thereof
US9236110B2 (en) * 2012-06-30 2016-01-12 Intel Corporation Row hammer refresh command
US8938573B2 (en) * 2012-06-30 2015-01-20 Intel Corporation Row hammer condition monitoring

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12175099B2 (en) 2022-07-25 2024-12-24 Samsung Electronics Co., Ltd. Semiconductor memory device and memory system including the same
US12236997B2 (en) 2022-07-25 2025-02-25 Samsung Electronics Co., Ltd. Semiconductor memory device and memory system including the same

Also Published As

Publication number Publication date
US20150200002A1 (en) 2015-07-16
CN104778013B (zh) 2019-06-25
KR20150085485A (ko) 2015-07-23
TW201535366A (zh) 2015-09-16
US9589606B2 (en) 2017-03-07
CN104778013A (zh) 2015-07-15
KR102223188B1 (ko) 2021-03-05
TWI646533B (zh) 2019-01-01
JP2015133119A (ja) 2015-07-23

Similar Documents

Publication Publication Date Title
JP6463141B2 (ja) メモリローに対するアクティベーションをトラッキングする方法及びそのためのメモリコントローラ
KR102480349B1 (ko) 집적 프로세서를 갖는 dram의 로우 해머 수정 로직
CN113342615B (zh) 命令监控方法、装置、控制器、系统、设备和存储介质
KR102048762B1 (ko) 다이나믹 랜덤 액세스 메모리(dram)를 리프레시하기 위한 방법, 장치 및 시스템
EP3367251B1 (en) Storage system and solid state hard disk
US11899580B2 (en) Cache space management method and apparatus
US10901619B2 (en) Selecting pages implementing leaf nodes and internal nodes of a data set index for reuse
US8560767B2 (en) Optimizing EDRAM refresh rates in a high performance cache architecture
US20180190340A1 (en) Memory device and memory system performing request-based refresh, and operating method of the memory device
US20240079042A1 (en) Counter-based selective row hammer refresh apparatus and method for row hammer prevention
US20110179248A1 (en) Adaptive bandwidth allocation for memory
US11361811B2 (en) Method and circuit for protecting a DRAM memory device from the row hammer effect
US20150206558A1 (en) Systems and methods for monitoring and controlling repetitive accesses to volatile memory
JP2017511545A (ja) メモリコントローラにおける細粒度帯域幅プロビジョニング
CN110556139B (zh) 用以控制存储器的电路及相关的方法
JP2018081642A (ja) メモリコントローラおよび方法
JP2018128991A (ja) メモリコントローラおよび方法
US10007557B2 (en) Computing resource controller and control method for multiple engines to share a shared resource
JP2590712B2 (ja) メモリ制御装置
CN120215835A (zh) 一种磁盘冗余阵列缓存空间调整方法、装置、设备及介质
JP2005135443A (ja) アクセス制御方法およびアクセス制御回路

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171220

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20171220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20181218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181228

R150 Certificate of patent or registration of utility model

Ref document number: 6463141

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250