CN104778013B - 追踪对存储器的行的激活的方法和设备 - Google Patents
追踪对存储器的行的激活的方法和设备 Download PDFInfo
- Publication number
- CN104778013B CN104778013B CN201510021504.6A CN201510021504A CN104778013B CN 104778013 B CN104778013 B CN 104778013B CN 201510021504 A CN201510021504 A CN 201510021504A CN 104778013 B CN104778013 B CN 104778013B
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461927636P | 2014-01-15 | 2014-01-15 | |
| US61/927,636 | 2014-01-15 | ||
| US14/560,674 US9589606B2 (en) | 2014-01-15 | 2014-12-04 | Handling maximum activation count limit and target row refresh in DDR4 SDRAM |
| US14/560,674 | 2014-12-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104778013A CN104778013A (zh) | 2015-07-15 |
| CN104778013B true CN104778013B (zh) | 2019-06-25 |
Family
ID=53521912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510021504.6A Active CN104778013B (zh) | 2014-01-15 | 2015-01-15 | 追踪对存储器的行的激活的方法和设备 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9589606B2 (enExample) |
| JP (1) | JP6463141B2 (enExample) |
| KR (1) | KR102223188B1 (enExample) |
| CN (1) | CN104778013B (enExample) |
| TW (1) | TWI646533B (enExample) |
Families Citing this family (49)
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| US9236110B2 (en) | 2012-06-30 | 2016-01-12 | Intel Corporation | Row hammer refresh command |
| US9384821B2 (en) * | 2012-11-30 | 2016-07-05 | Intel Corporation | Row hammer monitoring based on stored row hammer threshold value |
| US9286964B2 (en) * | 2012-12-21 | 2016-03-15 | Intel Corporation | Method, apparatus and system for responding to a row hammer event |
| US9478263B2 (en) * | 2014-01-17 | 2016-10-25 | Apple Inc. | Systems and methods for monitoring and controlling repetitive accesses to volatile memory |
| JP6224483B2 (ja) * | 2014-02-26 | 2017-11-01 | Ｎｅｃプラットフォームズ株式会社 | 半導体記憶装置、メモリアクセス制御方法、およびコンピュータ・プログラム |
| CN105159853B (zh) * | 2015-09-25 | 2018-04-24 | 中国船舶重工集团公司第七0九研究所 | 基于fpga的dfi标准ddr3控制器 |
| US9812185B2 (en) | 2015-10-21 | 2017-11-07 | Invensas Corporation | DRAM adjacent row disturb mitigation |
| RU2692136C1 (ru) * | 2016-02-22 | 2019-06-21 | ДжФЕ СТИЛ КОРПОРЕЙШН | Способ изготовления листа из текстурированной электротехнической стали |
| JP6455468B2 (ja) * | 2016-03-09 | 2019-01-23 | Ｊｆｅスチール株式会社 | 方向性電磁鋼板の製造方法 |
| WO2017155057A1 (ja) * | 2016-03-09 | 2017-09-14 | Ｊｆｅスチール株式会社 | 方向性電磁鋼板の製造方法 |
| US10268585B2 (en) * | 2016-06-28 | 2019-04-23 | Intel Corporation | Memory controller that forces prefetches in response to a present row address change timing constraint |
| CN109983536B (zh) * | 2016-11-29 | 2023-07-21 | Arm有限公司 | 响应标签匹配命令的存储电路 |
| JP7008410B2 (ja) * | 2017-02-10 | 2022-01-25 | キヤノン株式会社 | メモリコントローラおよび方法 |
| CN108932205B (zh) * | 2017-05-25 | 2021-01-29 | 华为技术有限公司 | 一种防御RowHammer攻击的方法及设备 |
| US11054995B2 (en) * | 2018-09-07 | 2021-07-06 | Micron Technology, Inc. | Row hammer protection for a memory device |
| KR102617016B1 (ko) | 2018-09-17 | 2023-12-27 | 삼성전자주식회사 | 자주 접근되는 어드레스를 검출하는 레지스터 클럭 드라이버를 포함하는 메모리 모듈 |
| US10726903B2 (en) * | 2018-09-21 | 2020-07-28 | Nanya Technology Corporation | Row-determining circuit, DRAM, and method for refreshing a memory array |
| US10825534B2 (en) * | 2018-10-26 | 2020-11-03 | Intel Corporation | Per row activation count values embedded in storage cell array storage cells |
| US10969997B2 (en) * | 2018-11-07 | 2021-04-06 | Intel Corporation | Memory controller that filters a count of row activate commands collectively sent to a set of memory banks |
| US10943637B2 (en) * | 2018-12-27 | 2021-03-09 | Micron Technology, Inc. | Apparatus with a row-hammer address latch mechanism |
| EP3675125A1 (en) * | 2018-12-27 | 2020-07-01 | Secure-IC SAS | Device and method for protecting a memory |
| KR102687575B1 (ko) | 2019-01-03 | 2024-07-24 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작방법 |
| CN110706733A (zh) * | 2019-08-13 | 2020-01-17 | 浙江工商大学 | 一种dram内存行扰动错误解决方法 |
| KR102675313B1 (ko) * | 2019-10-31 | 2024-06-17 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러 및 그 동작 방법 |
| JP6975298B1 (ja) | 2020-09-03 | 2021-12-01 | 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. | 半導体記憶装置 |
| EP4182800A1 (en) * | 2020-09-14 | 2023-05-24 | Google LLC | Memory request timeouts using a common counter |
| KR102412680B1 (ko) | 2020-10-20 | 2022-06-23 | 윈본드 일렉트로닉스 코포레이션 | 반도체 기억장치 |
| US11474746B2 (en) * | 2020-12-10 | 2022-10-18 | Advanced Micro Devices, Inc. | Refresh management for DRAM |
| KR20220120771A (ko) | 2021-02-23 | 2022-08-31 | 삼성전자주식회사 | 메모리 장치 및 그것의 동작 방법 |
| KR102453523B1 (ko) | 2021-03-10 | 2022-10-11 | 윈본드 일렉트로닉스 코포레이션 | 반도체 기억장치 |
| JP7574720B2 (ja) * | 2021-04-05 | 2024-10-29 | 富士通株式会社 | メモリ管理装置、メモリ管理方法及びメモリ管理プログラム |
| KR102504489B1 (ko) | 2021-04-19 | 2023-02-27 | 윈본드 일렉트로닉스 코포레이션 | 반도체 기억장치 |
| KR20220145667A (ko) | 2021-04-22 | 2022-10-31 | 삼성전자주식회사 | 적응적 구동 전압을 생성하는 위상 고정 루프 및 이의 동작 방법 |
| KR20230056339A (ko) | 2021-10-20 | 2023-04-27 | 에스케이하이닉스 주식회사 | 스마트 리프레쉬 동작을 수행하기 위한 메모리 장치 및 이를 포함하는 메모리 시스템 |
| KR20230059630A (ko) | 2021-10-26 | 2023-05-03 | 삼성전자주식회사 | 로우 해머 제어 방법 및 메모리 장치 |
| KR20230065470A (ko) | 2021-11-05 | 2023-05-12 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
| KR102892723B1 (ko) | 2021-11-17 | 2025-11-28 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
| US12236105B2 (en) | 2022-01-11 | 2025-02-25 | Samsung Electronics Co., Ltd. | Semiconductor memory devices having enhanced refresh operations that inhibit row hammer hacking |
| US12248567B2 (en) * | 2022-01-21 | 2025-03-11 | Micron Technology, Inc. | Row hammer interrupts to the operating system |
| JP2023130672A (ja) * | 2022-03-08 | 2023-09-21 | ソニーセミコンダクタソリューションズ株式会社 | メモリコントローラおよびメモリ制御方法 |
| US12080334B2 (en) | 2022-04-11 | 2024-09-03 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system including the same |
| US12230312B2 (en) | 2022-06-17 | 2025-02-18 | Samsung Electronics Co., Ltd. | Memory device and defense method thereof |
| US12236997B2 (en) | 2022-07-25 | 2025-02-25 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system including the same |
| US12175099B2 (en) | 2022-07-25 | 2024-12-24 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system including the same |
| KR20240016023A (ko) | 2022-07-28 | 2024-02-06 | 삼성전자주식회사 | 메모리 장치 및 그 리프레시 방법 |
| US12488824B2 (en) * | 2022-10-03 | 2025-12-02 | Micron Technology, Inc. | Memory with deterministic worst-case row address servicing, and associated systems, devices, and methods |
| KR20240059151A (ko) | 2022-10-27 | 2024-05-07 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
| KR20240062601A (ko) | 2022-11-02 | 2024-05-09 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
| KR20240143291A (ko) | 2023-03-24 | 2024-10-02 | 에스케이하이닉스 주식회사 | 카운팅 동작을 수행하는 메모리, 메모리 시스템 및 메모리의 동작 방법 |
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| CN1509436A (zh) * | 2001-05-16 | 2004-06-30 | 先进微装置公司 | 以推测方式使高速缓存中的缓存行失效的方法及系统 |
| CN1858720A (zh) * | 2005-10-28 | 2006-11-08 | 中国人民解放军国防科学技术大学 | 基于高速缓冲存储器行偏移量实现优先读取存储器的方法 |
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| CN101123113A (zh) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | 同步动态随机访问存储器的访问方法及控制装置 |
| CN101923499A (zh) * | 2009-03-30 | 2010-12-22 | 英特尔公司 | 执行防电源故障高速缓存而无需原子元数据的技术 |
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| US8938573B2 (en) * | 2012-06-30 | 2015-01-20 | Intel Corporation | Row hammer condition monitoring |
-
2014
- 2014-12-04 US US14/560,674 patent/US9589606B2/en active Active
- 2014-12-31 TW TW103146557A patent/TWI646533B/zh active
-
2015
- 2015-01-14 KR KR1020150006906A patent/KR102223188B1/ko active Active
- 2015-01-15 CN CN201510021504.6A patent/CN104778013B/zh active Active
- 2015-01-15 JP JP2015005870A patent/JP6463141B2/ja active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1509436A (zh) * | 2001-05-16 | 2004-06-30 | 先进微装置公司 | 以推测方式使高速缓存中的缓存行失效的方法及系统 |
| CN1858720A (zh) * | 2005-10-28 | 2006-11-08 | 中国人民解放军国防科学技术大学 | 基于高速缓冲存储器行偏移量实现优先读取存储器的方法 |
| CN101082882A (zh) * | 2006-05-30 | 2007-12-05 | 株式会社东芝 | 高速缓冲存储器装置和高速缓冲存储方法 |
| CN101123113A (zh) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | 同步动态随机访问存储器的访问方法及控制装置 |
| CN101923499A (zh) * | 2009-03-30 | 2010-12-22 | 英特尔公司 | 执行防电源故障高速缓存而无需原子元数据的技术 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150200002A1 (en) | 2015-07-16 |
| KR20150085485A (ko) | 2015-07-23 |
| TW201535366A (zh) | 2015-09-16 |
| JP6463141B2 (ja) | 2019-01-30 |
| US9589606B2 (en) | 2017-03-07 |
| CN104778013A (zh) | 2015-07-15 |
| KR102223188B1 (ko) | 2021-03-05 |
| TWI646533B (zh) | 2019-01-01 |
| JP2015133119A (ja) | 2015-07-23 |
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