TWI646533B - 處理第四代雙倍資料率同步動態隨機存取記憶體中的最大啓動計數限制及目標列再新之技術 - Google Patents
處理第四代雙倍資料率同步動態隨機存取記憶體中的最大啓動計數限制及目標列再新之技術 Download PDFInfo
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- TWI646533B TWI646533B TW103146557A TW103146557A TWI646533B TW I646533 B TWI646533 B TW I646533B TW 103146557 A TW103146557 A TW 103146557A TW 103146557 A TW103146557 A TW 103146557A TW I646533 B TWI646533 B TW I646533B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461927636P | 2014-01-15 | 2014-01-15 | |
| US61/927,636 | 2014-01-15 | ||
| US14/560,674 US9589606B2 (en) | 2014-01-15 | 2014-12-04 | Handling maximum activation count limit and target row refresh in DDR4 SDRAM |
| US14/560,674 | 2014-12-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201535366A TW201535366A (zh) | 2015-09-16 |
| TWI646533B true TWI646533B (zh) | 2019-01-01 |
Family
ID=53521912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103146557A TWI646533B (zh) | 2014-01-15 | 2014-12-31 | 處理第四代雙倍資料率同步動態隨機存取記憶體中的最大啓動計數限制及目標列再新之技術 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9589606B2 (enExample) |
| JP (1) | JP6463141B2 (enExample) |
| KR (1) | KR102223188B1 (enExample) |
| CN (1) | CN104778013B (enExample) |
| TW (1) | TWI646533B (enExample) |
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| US9286964B2 (en) * | 2012-12-21 | 2016-03-15 | Intel Corporation | Method, apparatus and system for responding to a row hammer event |
| US9478263B2 (en) * | 2014-01-17 | 2016-10-25 | Apple Inc. | Systems and methods for monitoring and controlling repetitive accesses to volatile memory |
| JP6224483B2 (ja) * | 2014-02-26 | 2017-11-01 | Ｎｅｃプラットフォームズ株式会社 | 半導体記憶装置、メモリアクセス制御方法、およびコンピュータ・プログラム |
| CN105159853B (zh) * | 2015-09-25 | 2018-04-24 | 中国船舶重工集团公司第七0九研究所 | 基于fpga的dfi标准ddr3控制器 |
| US9812185B2 (en) | 2015-10-21 | 2017-11-07 | Invensas Corporation | DRAM adjacent row disturb mitigation |
| RU2692136C1 (ru) * | 2016-02-22 | 2019-06-21 | ДжФЕ СТИЛ КОРПОРЕЙШН | Способ изготовления листа из текстурированной электротехнической стали |
| JP6455468B2 (ja) * | 2016-03-09 | 2019-01-23 | Ｊｆｅスチール株式会社 | 方向性電磁鋼板の製造方法 |
| WO2017155057A1 (ja) * | 2016-03-09 | 2017-09-14 | Ｊｆｅスチール株式会社 | 方向性電磁鋼板の製造方法 |
| US10268585B2 (en) * | 2016-06-28 | 2019-04-23 | Intel Corporation | Memory controller that forces prefetches in response to a present row address change timing constraint |
| CN109983536B (zh) * | 2016-11-29 | 2023-07-21 | Arm有限公司 | 响应标签匹配命令的存储电路 |
| JP7008410B2 (ja) * | 2017-02-10 | 2022-01-25 | キヤノン株式会社 | メモリコントローラおよび方法 |
| CN108932205B (zh) * | 2017-05-25 | 2021-01-29 | 华为技术有限公司 | 一种防御RowHammer攻击的方法及设备 |
| US11054995B2 (en) * | 2018-09-07 | 2021-07-06 | Micron Technology, Inc. | Row hammer protection for a memory device |
| KR102617016B1 (ko) | 2018-09-17 | 2023-12-27 | 삼성전자주식회사 | 자주 접근되는 어드레스를 검출하는 레지스터 클럭 드라이버를 포함하는 메모리 모듈 |
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| CN110706733A (zh) * | 2019-08-13 | 2020-01-17 | 浙江工商大学 | 一种dram内存行扰动错误解决方法 |
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| KR102504489B1 (ko) | 2021-04-19 | 2023-02-27 | 윈본드 일렉트로닉스 코포레이션 | 반도체 기억장치 |
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-
2014
- 2014-12-04 US US14/560,674 patent/US9589606B2/en active Active
- 2014-12-31 TW TW103146557A patent/TWI646533B/zh active
-
2015
- 2015-01-14 KR KR1020150006906A patent/KR102223188B1/ko active Active
- 2015-01-15 CN CN201510021504.6A patent/CN104778013B/zh active Active
- 2015-01-15 JP JP2015005870A patent/JP6463141B2/ja active Active
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| US5883849A (en) * | 1997-06-30 | 1999-03-16 | Micron Technology, Inc. | Method and apparatus for simultaneous memory subarray testing |
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| TWI367486B (en) * | 2007-12-25 | 2012-07-01 | Ind Tech Res Inst | Memory device and refresh method thereof |
| US20140006703A1 (en) * | 2012-06-30 | 2014-01-02 | Kuljit S. Bains | Row hammer refresh command |
| US20140006704A1 (en) * | 2012-06-30 | 2014-01-02 | Zvika Greenfield | Row hammer condition monitoring |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150200002A1 (en) | 2015-07-16 |
| CN104778013B (zh) | 2019-06-25 |
| KR20150085485A (ko) | 2015-07-23 |
| TW201535366A (zh) | 2015-09-16 |
| JP6463141B2 (ja) | 2019-01-30 |
| US9589606B2 (en) | 2017-03-07 |
| CN104778013A (zh) | 2015-07-15 |
| KR102223188B1 (ko) | 2021-03-05 |
| JP2015133119A (ja) | 2015-07-23 |
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