JP2019525324A5 - - Google Patents

Download PDF

Info

Publication number
JP2019525324A5
JP2019525324A5 JP2019501571A JP2019501571A JP2019525324A5 JP 2019525324 A5 JP2019525324 A5 JP 2019525324A5 JP 2019501571 A JP2019501571 A JP 2019501571A JP 2019501571 A JP2019501571 A JP 2019501571A JP 2019525324 A5 JP2019525324 A5 JP 2019525324A5
Authority
JP
Japan
Prior art keywords
batch
memory requests
memory
group
threads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019501571A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019525324A (ja
Filing date
Publication date
Priority claimed from US15/209,346 external-priority patent/US10572399B2/en
Application filed filed Critical
Publication of JP2019525324A publication Critical patent/JP2019525324A/ja
Publication of JP2019525324A5 publication Critical patent/JP2019525324A5/ja
Pending legal-status Critical Current

Links

JP2019501571A 2016-07-13 2017-05-22 メモリ要求仲裁 Pending JP2019525324A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,346 US10572399B2 (en) 2016-07-13 2016-07-13 Memory request arbitration
US15/209,346 2016-07-13
PCT/US2017/033818 WO2018013225A1 (en) 2016-07-13 2017-05-22 Memory request arbitration

Publications (2)

Publication Number Publication Date
JP2019525324A JP2019525324A (ja) 2019-09-05
JP2019525324A5 true JP2019525324A5 (enExample) 2020-06-11

Family

ID=59014755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019501571A Pending JP2019525324A (ja) 2016-07-13 2017-05-22 メモリ要求仲裁

Country Status (7)

Country Link
US (1) US10572399B2 (enExample)
EP (1) EP3485384B1 (enExample)
JP (1) JP2019525324A (enExample)
KR (1) KR20190028427A (enExample)
CN (1) CN109416673A (enExample)
BR (1) BR112019000310A8 (enExample)
WO (1) WO2018013225A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10095431B2 (en) * 2015-06-18 2018-10-09 John Edward Benkert Device controller and method of enforcing time-based sector level security
JP6971063B2 (ja) * 2017-06-13 2021-11-24 株式会社小糸製作所 監視装置及びランプの配光制御装置
US11321146B2 (en) 2019-05-09 2022-05-03 International Business Machines Corporation Executing an atomic primitive in a multi-core processor system
US11681567B2 (en) 2019-05-09 2023-06-20 International Business Machines Corporation Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive
US11321135B2 (en) * 2019-10-31 2022-05-03 Oracle International Corporation Rate limiting compliance assessments with multi-layer fair share scheduling
US11709711B2 (en) * 2020-09-27 2023-07-25 Advanced Micro Devices, Inc. Allocation of memory access bandwidth to clients in an electronic device
CN113176911B (zh) * 2021-04-29 2024-07-12 上海阵量智能科技有限公司 一种配置方法、数据处理方法、芯片和电子设备
US11443479B1 (en) * 2021-05-19 2022-09-13 Apple Inc. Snapshot arbitration techniques for memory requests
US20240176647A1 (en) * 2022-11-30 2024-05-30 Vmware, Inc. Blockchain request prescreening for parallel request processing
US20240311199A1 (en) * 2023-03-13 2024-09-19 Advanced Micro Devices, Inc. Software-defined compute unit resource allocation mode
US20250077084A1 (en) * 2023-09-06 2025-03-06 Micron Technology, Inc. Write processing using queue and thread identification

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107371B1 (en) * 1997-09-22 2006-09-12 Intel Corporation Method and apparatus for providing and embedding control information in a bus system
US6816947B1 (en) * 2000-07-20 2004-11-09 Silicon Graphics, Inc. System and method for memory arbitration
US7406554B1 (en) * 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
US6961834B2 (en) 2001-10-12 2005-11-01 Sonics, Inc. Method and apparatus for scheduling of requests to dynamic random access memory device
US6891543B2 (en) * 2002-05-08 2005-05-10 Intel Corporation Method and system for optimally sharing memory between a host processor and graphics processor
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7617368B2 (en) * 2006-06-14 2009-11-10 Nvidia Corporation Memory interface with independent arbitration of precharge, activate, and read/write
US7796137B1 (en) 2006-10-24 2010-09-14 Nvidia Corporation Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US9170844B2 (en) * 2009-01-02 2015-10-27 International Business Machines Corporation Prioritization for conflict arbitration in transactional memory management
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8607234B2 (en) * 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US8667493B2 (en) * 2010-05-07 2014-03-04 Advanced Micro Devices, Inc. Memory-controller-parallelism-aware scheduling for multiple memory controllers
US8453150B2 (en) 2010-06-08 2013-05-28 Advanced Micro Devices, Inc. Multithread application-aware memory scheduling scheme for multi-core processors
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US9256915B2 (en) * 2012-01-27 2016-02-09 Qualcomm Incorporated Graphics processing unit buffer management
US8775762B2 (en) 2012-05-07 2014-07-08 Advanced Micro Devices, Inc. Method and apparatus for batching memory requests
US8886886B2 (en) 2012-09-28 2014-11-11 Apple Inc. System cache with sticky removal engine
US9405688B2 (en) * 2013-03-05 2016-08-02 Intel Corporation Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
US9135179B2 (en) * 2013-05-01 2015-09-15 Qualcomm, Incorporated System and method of arbitrating cache requests
JP6311330B2 (ja) * 2014-01-29 2018-04-18 日本電気株式会社 情報処理装置、情報処理方法およびプログラム
US9575807B2 (en) 2014-04-15 2017-02-21 Intel Corporation Processing accelerator with queue threads and methods therefor
US9928564B2 (en) * 2014-06-26 2018-03-27 Intel Corporation Efficient hardware mechanism to ensure shared resource data coherency across draw calls

Similar Documents

Publication Publication Date Title
JP2019525324A5 (enExample)
JP2019525271A5 (enExample)
JP2010211696A5 (ja) プログラムおよび情報処理装置
JP2016511489A5 (enExample)
JP2017192696A5 (enExample)
US20170255392A1 (en) Storage control device, storage control method, and recording medium
JP2017192693A5 (enExample)
JP2018027369A5 (enExample)
JP2017527883A5 (enExample)
JP2019532450A5 (enExample)
JP2017192697A5 (enExample)
JP2017512340A5 (enExample)
JP2016510458A5 (enExample)
JP2018020060A5 (enExample)
JP2018020055A5 (enExample)
RU2015134169A (ru) Определение профиля пути, используя комбинацию аппаратных и программных средств
JP2018102336A5 (enExample)
JP2018020056A5 (enExample)
JP2018020054A5 (enExample)
JP2018020053A5 (enExample)
JP2011118900A5 (enExample)
JP2016076223A5 (enExample)
JP2016515269A5 (enExample)
JP2017185306A5 (enExample)
JP2018020059A5 (enExample)