JP2019525271A5 - - Google Patents

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Publication number
JP2019525271A5
JP2019525271A5 JP2018524749A JP2018524749A JP2019525271A5 JP 2019525271 A5 JP2019525271 A5 JP 2019525271A5 JP 2018524749 A JP2018524749 A JP 2018524749A JP 2018524749 A JP2018524749 A JP 2018524749A JP 2019525271 A5 JP2019525271 A5 JP 2019525271A5
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JP
Japan
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sub
memory
arbitration
command
controller
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JP2018524749A
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English (en)
Japanese (ja)
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JP2019525271A (ja
JP6840145B2 (ja
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Priority claimed from US15/211,815 external-priority patent/US10684969B2/en
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Publication of JP2019525271A5 publication Critical patent/JP2019525271A5/ja
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Publication of JP6840145B2 publication Critical patent/JP6840145B2/ja
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JP2018524749A 2016-07-15 2016-09-22 高速メモリインタフェースのためのコマンドアービトレーション Active JP6840145B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/211,815 US10684969B2 (en) 2016-07-15 2016-07-15 Command arbitration for high speed memory interfaces
US15/211,815 2016-07-15
PCT/US2016/053131 WO2018013157A1 (en) 2016-07-15 2016-09-22 Command arbitration for high speed memory interfaces

Publications (3)

Publication Number Publication Date
JP2019525271A JP2019525271A (ja) 2019-09-05
JP2019525271A5 true JP2019525271A5 (enExample) 2019-11-07
JP6840145B2 JP6840145B2 (ja) 2021-03-10

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Family Applications (1)

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JP2018524749A Active JP6840145B2 (ja) 2016-07-15 2016-09-22 高速メモリインタフェースのためのコマンドアービトレーション

Country Status (5)

Country Link
US (1) US10684969B2 (enExample)
JP (1) JP6840145B2 (enExample)
KR (1) KR102442078B1 (enExample)
CN (1) CN107924375B (enExample)
WO (1) WO2018013157A1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
CN110729006B (zh) * 2018-07-16 2022-07-05 超威半导体(上海)有限公司 存储器控制器中的刷新方案
US11126375B2 (en) * 2019-07-18 2021-09-21 Micron Technology, Inc. Arbiter circuit for commands from multiple physical functions in a memory sub-system
US11200106B2 (en) * 2019-08-12 2021-12-14 Advanced Micro Devices, Inc. Data integrity for persistent memory systems and the like
US12253961B2 (en) * 2019-12-27 2025-03-18 Advanced Micro Devices, Inc. Staging memory access requests
US12056065B2 (en) * 2020-03-13 2024-08-06 Altera Corporation Orthogonal multi-phase scheduling circuitry
US11222685B2 (en) * 2020-05-15 2022-01-11 Advanced Micro Devices, Inc. Refresh management for DRAM
US11625352B2 (en) * 2020-06-12 2023-04-11 Advanced Micro Devices, Inc. DRAM command streak management
CN111984387B (zh) * 2020-08-26 2024-06-25 上海兆芯集成电路股份有限公司 用于调度发布队列中指令的方法及处理器
CN112466361B (zh) * 2020-11-25 2023-11-21 海光信息技术股份有限公司 一种dimm的数据初始化方法、装置、系统及设备
US11687281B2 (en) * 2021-03-31 2023-06-27 Advanced Micro Devices, Inc. DRAM command streak efficiency management
US11669274B2 (en) * 2021-03-31 2023-06-06 Advanced Micro Devices, Inc. Write bank group mask during arbitration
US11379388B1 (en) * 2021-03-31 2022-07-05 Advanced Micro Devices, Inc. Credit scheme for multi-queue memory controllers
US11995008B2 (en) * 2021-06-22 2024-05-28 Advanced Micro Devices, Inc. Memory controller with hybrid DRAM/persistent memory channel arbitration
US11755246B2 (en) * 2021-06-24 2023-09-12 Advanced Micro Devices, Inc. Efficient rank switching in multi-rank memory controller
US12073114B2 (en) * 2021-09-30 2024-08-27 Advanced Micro Devices, Inc. Stacked command queue
CN116069715B (zh) * 2021-11-04 2025-09-05 瑞昱半导体股份有限公司 存储装置共享系统及存储装置共享方法
US12117945B2 (en) 2022-06-24 2024-10-15 Advanced Micro Devices, Inc. Memory controller with pseudo-channel support
US12154657B2 (en) 2022-06-29 2024-11-26 Advanced Micro Devices, Inc. Channel and sub-channel throttling for memory controllers
US20240078017A1 (en) * 2022-09-01 2024-03-07 Advanced Micro Devices, Inc. Memory controller and near-memory support for sparse accesses
US12079144B1 (en) 2022-09-21 2024-09-03 Apple Inc. Arbitration sub-queues for a memory circuit
CN115632665B (zh) * 2022-12-20 2023-07-14 苏州浪潮智能科技有限公司 一种存储校验的系统和服务器
CN116974963B (zh) * 2023-09-25 2023-12-15 上海云豹创芯智能科技有限公司 一种访问存储器的装置及其方法、芯片、存储介质
US20250139022A1 (en) * 2023-11-01 2025-05-01 Advanced Micro Devices, Inc. Multiplexed bus streak management

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6138197A (en) * 1998-09-17 2000-10-24 Sun Microsystems, Inc. Apparatus and method for limit-based arbitration scheme
US6295586B1 (en) 1998-12-04 2001-09-25 Advanced Micro Devices, Inc. Queue based memory controller
US6804758B2 (en) 2001-06-29 2004-10-12 Xgi Technology Inc. Method for adaptive arbitration of requests for memory access in a multi-stage pipeline engine
US7426621B2 (en) 2005-12-09 2008-09-16 Advanced Micro Devices, Inc. Memory access request arbitration
US7617368B2 (en) 2006-06-14 2009-11-10 Nvidia Corporation Memory interface with independent arbitration of precharge, activate, and read/write
US8271746B1 (en) * 2006-11-03 2012-09-18 Nvidia Corporation Tiering of linear clients
US7734856B2 (en) 2007-08-22 2010-06-08 Lantiq Deutschland Gmbh Method for operating a plurality of arbiters and arbiter system
US9195618B2 (en) 2009-06-16 2015-11-24 Nvidia Corporation Method and system for scheduling memory requests
US8615629B2 (en) 2010-01-18 2013-12-24 Marvell International Ltd. Access scheduler
US8838853B2 (en) * 2010-01-18 2014-09-16 Marvell International Ltd. Access buffer
US8285892B2 (en) 2010-05-05 2012-10-09 Lsi Corporation Quantum burst arbiter and memory controller
US9009414B2 (en) 2010-09-21 2015-04-14 Texas Instruments Incorporated Prefetch address hit prediction to reduce memory access latency
US9911477B1 (en) * 2014-04-18 2018-03-06 Altera Corporation Memory controller architecture with improved memory scheduling efficiency
US9697118B1 (en) * 2015-12-09 2017-07-04 Nxp Usa, Inc. Memory controller with interleaving and arbitration scheme

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