JP2016173836A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2016173836A5 JP2016173836A5 JP2016090769A JP2016090769A JP2016173836A5 JP 2016173836 A5 JP2016173836 A5 JP 2016173836A5 JP 2016090769 A JP2016090769 A JP 2016090769A JP 2016090769 A JP2016090769 A JP 2016090769A JP 2016173836 A5 JP2016173836 A5 JP 2016173836A5
- Authority
- JP
- Japan
- Prior art keywords
- thread
- gpu
- host cpu
- access
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 8
- 230000011664 signaling Effects 0.000 claims 4
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/193,779 US9633407B2 (en) | 2011-07-29 | 2011-07-29 | CPU/GPU synchronization mechanism |
| US13/193,779 | 2011-07-29 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014522839A Division JP5933000B2 (ja) | 2011-07-29 | 2012-06-29 | 中央処理ユニット及び画像処理ユニットの同期機構 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016173836A JP2016173836A (ja) | 2016-09-29 |
| JP2016173836A5 true JP2016173836A5 (enExample) | 2017-05-18 |
| JP6219445B2 JP6219445B2 (ja) | 2017-10-25 |
Family
ID=47596851
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014522839A Active JP5933000B2 (ja) | 2011-07-29 | 2012-06-29 | 中央処理ユニット及び画像処理ユニットの同期機構 |
| JP2016090769A Active JP6219445B2 (ja) | 2011-07-29 | 2016-04-28 | 中央処理ユニット及び画像処理ユニットの同期機構 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014522839A Active JP5933000B2 (ja) | 2011-07-29 | 2012-06-29 | 中央処理ユニット及び画像処理ユニットの同期機構 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9633407B2 (enExample) |
| EP (2) | EP3211525B1 (enExample) |
| JP (2) | JP5933000B2 (enExample) |
| CN (2) | CN106648552B (enExample) |
| WO (1) | WO2013019350A2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9633407B2 (en) | 2011-07-29 | 2017-04-25 | Intel Corporation | CPU/GPU synchronization mechanism |
| CN104205042B (zh) | 2012-03-30 | 2019-01-08 | 英特尔公司 | 用于具有通用cpu核心和紧密耦合的加速器的处理核心的上下文切换机制 |
| US9436395B2 (en) | 2014-03-14 | 2016-09-06 | Advanced Micro Devices, Inc. | Mechanisms to save user/kernel copy for cross device communications |
| US20160381050A1 (en) | 2015-06-26 | 2016-12-29 | Intel Corporation | Processors, methods, systems, and instructions to protect shadow stacks |
| US9830676B2 (en) | 2015-07-28 | 2017-11-28 | Intel Corporation | Packet processing on graphics processing units using continuous threads |
| US10394556B2 (en) | 2015-12-20 | 2019-08-27 | Intel Corporation | Hardware apparatuses and methods to switch shadow stack pointers |
| US10430580B2 (en) | 2016-02-04 | 2019-10-01 | Intel Corporation | Processor extensions to protect stacks during ring transitions |
| MY190157A (en) | 2016-08-31 | 2022-03-31 | Asahi Chemical Ind | Method for producing catalyst and method for producing acrylonitrile |
| CN107291559A (zh) * | 2017-06-30 | 2017-10-24 | 武汉斗鱼网络科技有限公司 | 一种控制cpu线程和gpu线程同步的方法及装置 |
| CN113358924B (zh) * | 2021-04-30 | 2022-12-06 | 南方电网数字电网研究院有限公司 | 一种多线程双芯智能电表分时计量处理方法及装置 |
| US12182635B2 (en) * | 2021-08-18 | 2024-12-31 | Micron Technology, Inc. | Chained resource locking |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5440746A (en) | 1992-11-06 | 1995-08-08 | Seiko Epson Corporation | System and method for synchronizing processors in a parallel processing environment |
| US7234144B2 (en) * | 2002-01-04 | 2007-06-19 | Microsoft Corporation | Methods and system for managing computational resources of a coprocessor in a computing system |
| US7673304B2 (en) | 2003-02-18 | 2010-03-02 | Microsoft Corporation | Multithreaded kernel for graphics processing unit |
| US7487502B2 (en) | 2003-02-19 | 2009-02-03 | Intel Corporation | Programmable event driven yield mechanism which may activate other threads |
| US7788669B2 (en) * | 2003-05-02 | 2010-08-31 | Microsoft Corporation | System for isolating first computing environment from second execution environment while sharing resources by copying data from first portion to second portion of memory |
| US20050050305A1 (en) * | 2003-08-28 | 2005-03-03 | Kissell Kevin D. | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor |
| US7765547B2 (en) * | 2004-11-24 | 2010-07-27 | Maxim Integrated Products, Inc. | Hardware multithreading systems with state registers having thread profiling data |
| US7937709B2 (en) * | 2004-12-29 | 2011-05-03 | Intel Corporation | Synchronizing multiple threads efficiently |
| JP2007258873A (ja) | 2006-03-22 | 2007-10-04 | Toshiba Corp | 再生装置および再生方法 |
| US7773090B1 (en) | 2006-06-13 | 2010-08-10 | Nvidia Corporation | Kernel mode graphics driver for dual-core computer system |
| US8996846B2 (en) | 2007-09-27 | 2015-03-31 | Nvidia Corporation | System, method and computer program product for performing a scan operation |
| US8140823B2 (en) * | 2007-12-03 | 2012-03-20 | Qualcomm Incorporated | Multithreaded processor with lock indicator |
| US8413151B1 (en) * | 2007-12-19 | 2013-04-02 | Nvidia Corporation | Selective thread spawning within a multi-threaded processing system |
| US8933953B2 (en) * | 2008-06-30 | 2015-01-13 | Intel Corporation | Managing active thread dependencies in graphics processing |
| US8368701B2 (en) | 2008-11-06 | 2013-02-05 | Via Technologies, Inc. | Metaprocessor for GPU control and synchronization in a multiprocessor environment |
| US8397241B2 (en) * | 2008-11-13 | 2013-03-12 | Intel Corporation | Language level support for shared virtual memory |
| US7930519B2 (en) * | 2008-12-17 | 2011-04-19 | Advanced Micro Devices, Inc. | Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit |
| US20130125133A1 (en) * | 2009-05-29 | 2013-05-16 | Michael D. Schuster | System and Method for Load Balancing of Fully Strict Thread-Level Parallel Programs |
| US20110063305A1 (en) | 2009-09-16 | 2011-03-17 | Nvidia Corporation | Co-processing techniques on heterogeneous graphics processing units |
| US8868848B2 (en) | 2009-12-21 | 2014-10-21 | Intel Corporation | Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform |
| US9229779B2 (en) * | 2009-12-28 | 2016-01-05 | Empire Technology Development Llc | Parallelizing heterogeneous network communications in smart devices based on selection of task allocation strategy |
| US9633407B2 (en) | 2011-07-29 | 2017-04-25 | Intel Corporation | CPU/GPU synchronization mechanism |
-
2011
- 2011-07-29 US US13/193,779 patent/US9633407B2/en active Active
-
2012
- 2012-06-29 CN CN201611216183.6A patent/CN106648552B/zh active Active
- 2012-06-29 JP JP2014522839A patent/JP5933000B2/ja active Active
- 2012-06-29 EP EP17165984.0A patent/EP3211525B1/en active Active
- 2012-06-29 CN CN201280037791.4A patent/CN103718156B/zh active Active
- 2012-06-29 EP EP12819390.1A patent/EP2737396A4/en not_active Ceased
- 2012-06-29 WO PCT/US2012/044805 patent/WO2013019350A2/en not_active Ceased
-
2016
- 2016-04-28 JP JP2016090769A patent/JP6219445B2/ja active Active
- 2016-09-28 US US15/278,316 patent/US9892481B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2016173836A5 (enExample) | ||
| JP6961686B2 (ja) | トリガ動作を用いたｇｐｕリモート通信 | |
| US11467834B2 (en) | In-memory computing with cache coherent protocol | |
| US9715464B2 (en) | Direct memory access descriptor processing | |
| CN107003812B (zh) | 用于虚拟串行存在检测的控制器及其方法 | |
| US20190286610A1 (en) | System, method and computer readable medium for offloaded computation of distributed application protocols within a cluster of data processing nodes | |
| JP5112449B2 (ja) | スレッドをキューに供給する方法及び装置 | |
| JP2016534484A5 (enExample) | ||
| JP6219445B2 (ja) | 中央処理ユニット及び画像処理ユニットの同期機構 | |
| WO2013180691A1 (en) | Peer-to-peer interrupt signaling between devices coupled via interconnects | |
| CN106462395A (zh) | 多线程处理器架构中的线程等待 | |
| JP2014508982A5 (enExample) | ||
| JP2019525271A5 (enExample) | ||
| JP2014534529A5 (enExample) | ||
| CN114168301B (zh) | 线程调度方法、处理器以及电子装置 | |
| JP2019525324A (ja) | メモリ要求仲裁 | |
| JP2013156984A5 (enExample) | ||
| CN112313636B (zh) | 用于实现网络分组模板化的系统、装置和方法 | |
| CN104866443A (zh) | 可中断存储独占 | |
| CN107025142A (zh) | 一种线程间消息传递方法、装置及电子设备 | |
| CN105159785A (zh) | 处理单元之间的硬件同步屏障 | |
| US20160274936A1 (en) | Multi-core system for processing data packets | |
| US8122167B1 (en) | Polling in a virtualized information handling system | |
| US10713188B2 (en) | Inter-process signaling system and method | |
| US8453157B2 (en) | Thread synchronization in simultaneous multi-threaded processor machines |