JP5933000B2 - 中央処理ユニット及び画像処理ユニットの同期機構 - Google Patents

中央処理ユニット及び画像処理ユニットの同期機構 Download PDF

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JP5933000B2
JP5933000B2 JP2014522839A JP2014522839A JP5933000B2 JP 5933000 B2 JP5933000 B2 JP 5933000B2 JP 2014522839 A JP2014522839 A JP 2014522839A JP 2014522839 A JP2014522839 A JP 2014522839A JP 5933000 B2 JP5933000 B2 JP 5933000B2
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processing unit
thread
image processing
central processing
mutex
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JP2014522038A (ja
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ギンスブルグ,ボリス
ナタンゾン,エスフィルシュ
オサドチー,イリヤ
ザック,ヨアヴ
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インテル コーポレイション
インテル コーポレイション
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Multi Processors (AREA)
  • Image Generation (AREA)
  • Advance Control (AREA)
  • Processing Or Creating Images (AREA)
  • Digital Computer Display Output (AREA)
JP2014522839A 2011-07-29 2012-06-29 中央処理ユニット及び画像処理ユニットの同期機構 Active JP5933000B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/193,779 US9633407B2 (en) 2011-07-29 2011-07-29 CPU/GPU synchronization mechanism
US13/193,779 2011-07-29
PCT/US2012/044805 WO2013019350A2 (en) 2011-07-29 2012-06-29 Cpu/gpu synchronization mechanism

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JP2016090769A Division JP6219445B2 (ja) 2011-07-29 2016-04-28 中央処理ユニット及び画像処理ユニットの同期機構

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JP2014522038A JP2014522038A (ja) 2014-08-28
JP5933000B2 true JP5933000B2 (ja) 2016-06-08

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JP2014522839A Active JP5933000B2 (ja) 2011-07-29 2012-06-29 中央処理ユニット及び画像処理ユニットの同期機構
JP2016090769A Active JP6219445B2 (ja) 2011-07-29 2016-04-28 中央処理ユニット及び画像処理ユニットの同期機構

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US (2) US9633407B2 (enExample)
EP (2) EP3211525B1 (enExample)
JP (2) JP5933000B2 (enExample)
CN (2) CN106648552B (enExample)
WO (1) WO2013019350A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9633407B2 (en) 2011-07-29 2017-04-25 Intel Corporation CPU/GPU synchronization mechanism
CN104205042B (zh) 2012-03-30 2019-01-08 英特尔公司 用于具有通用cpu核心和紧密耦合的加速器的处理核心的上下文切换机制
US9436395B2 (en) 2014-03-14 2016-09-06 Advanced Micro Devices, Inc. Mechanisms to save user/kernel copy for cross device communications
US20160381050A1 (en) 2015-06-26 2016-12-29 Intel Corporation Processors, methods, systems, and instructions to protect shadow stacks
US9830676B2 (en) 2015-07-28 2017-11-28 Intel Corporation Packet processing on graphics processing units using continuous threads
US10394556B2 (en) 2015-12-20 2019-08-27 Intel Corporation Hardware apparatuses and methods to switch shadow stack pointers
US10430580B2 (en) 2016-02-04 2019-10-01 Intel Corporation Processor extensions to protect stacks during ring transitions
MY190157A (en) 2016-08-31 2022-03-31 Asahi Chemical Ind Method for producing catalyst and method for producing acrylonitrile
CN107291559A (zh) * 2017-06-30 2017-10-24 武汉斗鱼网络科技有限公司 一种控制cpu线程和gpu线程同步的方法及装置
CN113358924B (zh) * 2021-04-30 2022-12-06 南方电网数字电网研究院有限公司 一种多线程双芯智能电表分时计量处理方法及装置
US12182635B2 (en) * 2021-08-18 2024-12-31 Micron Technology, Inc. Chained resource locking

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440746A (en) 1992-11-06 1995-08-08 Seiko Epson Corporation System and method for synchronizing processors in a parallel processing environment
US7234144B2 (en) * 2002-01-04 2007-06-19 Microsoft Corporation Methods and system for managing computational resources of a coprocessor in a computing system
US7673304B2 (en) 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US7487502B2 (en) 2003-02-19 2009-02-03 Intel Corporation Programmable event driven yield mechanism which may activate other threads
US7788669B2 (en) * 2003-05-02 2010-08-31 Microsoft Corporation System for isolating first computing environment from second execution environment while sharing resources by copying data from first portion to second portion of memory
US20050050305A1 (en) * 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7765547B2 (en) * 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
US7937709B2 (en) * 2004-12-29 2011-05-03 Intel Corporation Synchronizing multiple threads efficiently
JP2007258873A (ja) 2006-03-22 2007-10-04 Toshiba Corp 再生装置および再生方法
US7773090B1 (en) 2006-06-13 2010-08-10 Nvidia Corporation Kernel mode graphics driver for dual-core computer system
US8996846B2 (en) 2007-09-27 2015-03-31 Nvidia Corporation System, method and computer program product for performing a scan operation
US8140823B2 (en) * 2007-12-03 2012-03-20 Qualcomm Incorporated Multithreaded processor with lock indicator
US8413151B1 (en) * 2007-12-19 2013-04-02 Nvidia Corporation Selective thread spawning within a multi-threaded processing system
US8933953B2 (en) * 2008-06-30 2015-01-13 Intel Corporation Managing active thread dependencies in graphics processing
US8368701B2 (en) 2008-11-06 2013-02-05 Via Technologies, Inc. Metaprocessor for GPU control and synchronization in a multiprocessor environment
US8397241B2 (en) * 2008-11-13 2013-03-12 Intel Corporation Language level support for shared virtual memory
US7930519B2 (en) * 2008-12-17 2011-04-19 Advanced Micro Devices, Inc. Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
US20130125133A1 (en) * 2009-05-29 2013-05-16 Michael D. Schuster System and Method for Load Balancing of Fully Strict Thread-Level Parallel Programs
US20110063305A1 (en) 2009-09-16 2011-03-17 Nvidia Corporation Co-processing techniques on heterogeneous graphics processing units
US8868848B2 (en) 2009-12-21 2014-10-21 Intel Corporation Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform
US9229779B2 (en) * 2009-12-28 2016-01-05 Empire Technology Development Llc Parallelizing heterogeneous network communications in smart devices based on selection of task allocation strategy
US9633407B2 (en) 2011-07-29 2017-04-25 Intel Corporation CPU/GPU synchronization mechanism

Also Published As

Publication number Publication date
US9633407B2 (en) 2017-04-25
CN103718156B (zh) 2018-05-01
EP2737396A2 (en) 2014-06-04
EP2737396A4 (en) 2015-06-10
CN106648552A (zh) 2017-05-10
CN106648552B (zh) 2019-02-22
US20130027410A1 (en) 2013-01-31
EP3211525B1 (en) 2020-04-29
JP2016173836A (ja) 2016-09-29
EP3211525A1 (en) 2017-08-30
JP2014522038A (ja) 2014-08-28
WO2013019350A2 (en) 2013-02-07
US20170018051A1 (en) 2017-01-19
WO2013019350A3 (en) 2013-05-10
US9892481B2 (en) 2018-02-13
JP6219445B2 (ja) 2017-10-25
CN103718156A (zh) 2014-04-09

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