CN109416673A - 存储器请求仲裁 - Google Patents

存储器请求仲裁 Download PDF

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Publication number
CN109416673A
CN109416673A CN201780041796.7A CN201780041796A CN109416673A CN 109416673 A CN109416673 A CN 109416673A CN 201780041796 A CN201780041796 A CN 201780041796A CN 109416673 A CN109416673 A CN 109416673A
Authority
CN
China
Prior art keywords
memory requests
memory
batch
thread
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201780041796.7A
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English (en)
Chinese (zh)
Inventor
马克西姆·卡扎科夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN109416673A publication Critical patent/CN109416673A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)
CN201780041796.7A 2016-07-13 2017-05-22 存储器请求仲裁 Pending CN109416673A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,346 US10572399B2 (en) 2016-07-13 2016-07-13 Memory request arbitration
US15/209,346 2016-07-13
PCT/US2017/033818 WO2018013225A1 (en) 2016-07-13 2017-05-22 Memory request arbitration

Publications (1)

Publication Number Publication Date
CN109416673A true CN109416673A (zh) 2019-03-01

Family

ID=59014755

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780041796.7A Pending CN109416673A (zh) 2016-07-13 2017-05-22 存储器请求仲裁

Country Status (7)

Country Link
US (1) US10572399B2 (enExample)
EP (1) EP3485384B1 (enExample)
JP (1) JP2019525324A (enExample)
KR (1) KR20190028427A (enExample)
CN (1) CN109416673A (enExample)
BR (1) BR112019000310A8 (enExample)
WO (1) WO2018013225A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113176911A (zh) * 2021-04-29 2021-07-27 上海阵量智能科技有限公司 一种配置方法、数据处理方法、芯片和电子设备

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10095431B2 (en) * 2015-06-18 2018-10-09 John Edward Benkert Device controller and method of enforcing time-based sector level security
JP6971063B2 (ja) * 2017-06-13 2021-11-24 株式会社小糸製作所 監視装置及びランプの配光制御装置
US11321146B2 (en) 2019-05-09 2022-05-03 International Business Machines Corporation Executing an atomic primitive in a multi-core processor system
US11681567B2 (en) 2019-05-09 2023-06-20 International Business Machines Corporation Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive
US11321135B2 (en) * 2019-10-31 2022-05-03 Oracle International Corporation Rate limiting compliance assessments with multi-layer fair share scheduling
US11709711B2 (en) * 2020-09-27 2023-07-25 Advanced Micro Devices, Inc. Allocation of memory access bandwidth to clients in an electronic device
US11443479B1 (en) * 2021-05-19 2022-09-13 Apple Inc. Snapshot arbitration techniques for memory requests
US20240176647A1 (en) * 2022-11-30 2024-05-30 Vmware, Inc. Blockchain request prescreening for parallel request processing
US20240311199A1 (en) * 2023-03-13 2024-09-19 Advanced Micro Devices, Inc. Software-defined compute unit resource allocation mode
US20250077084A1 (en) * 2023-09-06 2025-03-06 Micron Technology, Inc. Write processing using queue and thread identification

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1279788A (zh) * 1997-09-22 2001-01-10 英特尔公司 在总线系统中提供和嵌入控制信息的方法和装置
CN1666182A (zh) * 2002-05-08 2005-09-07 英特尔公司 用于在主机处理器和图形处理器之间优化存储器共享的方法和系统
CN101093435A (zh) * 2006-06-14 2007-12-26 辉达公司 具有预充电、激活和读取/写入的独立仲裁的存储器接口
US7406554B1 (en) * 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
US20100174840A1 (en) * 2009-01-02 2010-07-08 International Business Machines Corporation Prioritization for conflict arbitration in transactional memory management
US20110276972A1 (en) * 2010-05-07 2011-11-10 Jaewoong Chung Memory-controller-parallelism-aware scheduling for multiple memory controllers
CN102388372A (zh) * 2009-04-07 2012-03-21 想象技术有限公司 保证数据缓存与主存储器之间的一致性
US20130297906A1 (en) * 2012-05-07 2013-11-07 Gabriel H. Loh Method and apparatus for batching memory requests
US8607234B2 (en) * 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US20140258620A1 (en) * 2013-03-05 2014-09-11 Ramadass Nagarajan Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
CN104081449A (zh) * 2012-01-27 2014-10-01 高通股份有限公司 用于图形并行处理单元的缓冲器管理
CN105164652A (zh) * 2013-05-01 2015-12-16 高通股份有限公司 仲裁高速缓存请求的系统和方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6816947B1 (en) * 2000-07-20 2004-11-09 Silicon Graphics, Inc. System and method for memory arbitration
US6961834B2 (en) 2001-10-12 2005-11-01 Sonics, Inc. Method and apparatus for scheduling of requests to dynamic random access memory device
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7796137B1 (en) 2006-10-24 2010-09-14 Nvidia Corporation Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8453150B2 (en) 2010-06-08 2013-05-28 Advanced Micro Devices, Inc. Multithread application-aware memory scheduling scheme for multi-core processors
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8886886B2 (en) 2012-09-28 2014-11-11 Apple Inc. System cache with sticky removal engine
JP6311330B2 (ja) * 2014-01-29 2018-04-18 日本電気株式会社 情報処理装置、情報処理方法およびプログラム
US9575807B2 (en) 2014-04-15 2017-02-21 Intel Corporation Processing accelerator with queue threads and methods therefor
US9928564B2 (en) * 2014-06-26 2018-03-27 Intel Corporation Efficient hardware mechanism to ensure shared resource data coherency across draw calls

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1279788A (zh) * 1997-09-22 2001-01-10 英特尔公司 在总线系统中提供和嵌入控制信息的方法和装置
US7406554B1 (en) * 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
CN1666182A (zh) * 2002-05-08 2005-09-07 英特尔公司 用于在主机处理器和图形处理器之间优化存储器共享的方法和系统
CN101093435A (zh) * 2006-06-14 2007-12-26 辉达公司 具有预充电、激活和读取/写入的独立仲裁的存储器接口
US20100174840A1 (en) * 2009-01-02 2010-07-08 International Business Machines Corporation Prioritization for conflict arbitration in transactional memory management
CN102388372A (zh) * 2009-04-07 2012-03-21 想象技术有限公司 保证数据缓存与主存储器之间的一致性
US8607234B2 (en) * 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US20110276972A1 (en) * 2010-05-07 2011-11-10 Jaewoong Chung Memory-controller-parallelism-aware scheduling for multiple memory controllers
CN104081449A (zh) * 2012-01-27 2014-10-01 高通股份有限公司 用于图形并行处理单元的缓冲器管理
US20130297906A1 (en) * 2012-05-07 2013-11-07 Gabriel H. Loh Method and apparatus for batching memory requests
US20140258620A1 (en) * 2013-03-05 2014-09-11 Ramadass Nagarajan Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
CN105164652A (zh) * 2013-05-01 2015-12-16 高通股份有限公司 仲裁高速缓存请求的系统和方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113176911A (zh) * 2021-04-29 2021-07-27 上海阵量智能科技有限公司 一种配置方法、数据处理方法、芯片和电子设备

Also Published As

Publication number Publication date
US20180018097A1 (en) 2018-01-18
US10572399B2 (en) 2020-02-25
WO2018013225A1 (en) 2018-01-18
BR112019000310A2 (pt) 2019-04-16
BR112019000310A8 (pt) 2023-01-31
EP3485384A1 (en) 2019-05-22
EP3485384B1 (en) 2020-07-29
JP2019525324A (ja) 2019-09-05
KR20190028427A (ko) 2019-03-18

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Application publication date: 20190301