JP2014504014A - チャネルを用いたボイドフリーウェハ接合 - Google Patents
チャネルを用いたボイドフリーウェハ接合 Download PDFInfo
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- JP2014504014A JP2014504014A JP2013544739A JP2013544739A JP2014504014A JP 2014504014 A JP2014504014 A JP 2014504014A JP 2013544739 A JP2013544739 A JP 2013544739A JP 2013544739 A JP2013544739 A JP 2013544739A JP 2014504014 A JP2014504014 A JP 2014504014A
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- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 59
- 239000003989 dielectric material Substances 0.000 claims abstract description 37
- 238000004377 microelectronic Methods 0.000 claims abstract description 31
- 238000003825 pressing Methods 0.000 claims abstract description 19
- 230000009969 flowable effect Effects 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 238000013022 venting Methods 0.000 claims 1
- 239000011800 void material Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 162
- 239000007767 bonding agent Substances 0.000 description 44
- 239000000463 material Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 3
- 238000005304 joining Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Abstract
【選択図】図1(f)
Description
本出願は、2010年12月16日出願の米国特許出願第12/970,529号の継続出願であり、その開示内容は引用することにより本明細書の一部をなすものとする。
Claims (27)
- 内部に能動回路素子を有する第1の基板と第2の基板とを、前記各基板の対向する面の間にある流動性誘電材料とともに押圧するステップであって、前記第1の基板及び前記第2の基板の各々の熱膨張係数が10ppm/℃未満であり、前記対向する面の少なくとも一方は、該面の縁から延びている複数のチャネルを有し、それにより、前記対向する面によって定められる平面間の前記誘電材料の厚みが1ミクロンを超え、前記誘電材料の少なくとも一部が前記チャネルのうちの少なくともいくつかに流れ込むこととなる、ステップを含む、第1のマイクロ電子素子と第2のマイクロ電子素子とを接合する方法。
- 前記押圧するステップの後に、
前記第1の基板と前記第2の基板とを、それらの間にある前記流動性誘電材料とともにチャンバ内に配置するステップと、
前記流動性誘電材料と前記チャネルとの少なくとも一方にある空気を除去するために前記チャンバから空気を排出するステップと
を更に含む請求項1に記載の接合する方法。 - 前記押圧するステップの前に、
前記第1の基板と前記第2の基板とを、前記対向する面の少なくとも一方に接触している前記流動性誘電材料とともにチャンバ内に配置するステップと、
前記チャンバから空気を排出するステップと
を更に含む請求項1に記載の接合する方法。 - 前記第1の基板が、前記対向する面から離れたコンタクト支持面を有するものである、請求項1に記載の方法。
- 前記第1の基板の前記対向する面がそれ自体のコンタクト支持面である、請求項1に記載の方法。
- 前記第2の基板が内部に能動回路素子を有するものである、請求項1に記載の方法。
- 前記第2の基板が、前記チャネルを有する面とは反対側を向いているコンタクト支持面を有するものである、請求項6に記載の方法。
- 前記複数のチャネルが前記第2の基板のダイシングレーンに配置される、請求項6に記載の方法。
- 前記押圧するステップの後に、前記複数のチャネルの少なくともいくつかが、部分的にのみ前記流動性誘電材料により満たされる、請求項1に記載の方法。
- 前記誘電材料が接着剤を含むものである、請求項1に記載の方法。
- 前記誘電材料が部分的に硬化した誘電材料を含むものである、請求項1に記載の方法。
- 前記押圧するステップの後に、前記流動性誘電材料を硬化させるステップを更に含む請求項11に記載の方法。
- 少なくともいくつかのチャネルが第1の端部及び第2の端部を有し、各々が前記第2の基板の少なくとも1つの縁において露出している、請求項1に記載の方法。
- 前記複数のチャネルのうちの少なくとも2つが交差している、請求項13に記載の方法。
- 前記マイクロ電子素子が複数の縁を有する矩形形状であり、少なくともいくつかのチャネルが前記複数の縁のうちの少なくともいくつかにまで延びている、請求項1に記載の方法。
- 前記マイクロ電子素子が、少なくとも実質的に円形状のウェハであり、少なくともいくつかのチャネルが前記ウェハの縁まで延びている、請求項1に記載の方法。
- 各平面を定める対向する面と該平面間の空間を満たす誘電材料とを有する第1のマイクロ電子素子及び第2のマイクロ電子素子であって、前記対向する面のうちの少なくとも一方は、該面の縁から延びている複数のチャネルを有し、前記誘電材料は、前記平面間の空間における厚みが1ミクロンを超え、かつ前記チャネルの全てを満たすことなく前記チャネルのうちの少なくともいくつかに存在する、第1のマイクロ電子素子及び第2のマイクロ電子素子を備えたインプロセスユニット。
- 前記チャネルにおける前記対向する面からの深さが少なくとも5ミクロンである、請求項17に記載のインプロセスユニット。
- 前記第1の基板が、前記対向する面から離れたコンタクト支持面を有している、請求項17に記載のインプロセスユニット。
- 前記複数のチャネルが前記第2の基板のダイシングレーンに設けられている、請求項17に記載のインプロセスユニット。
- 前記誘電材料が接着剤を含むものである、請求項17に記載のインプロセスユニット。
- 前記誘電材料が部分的に硬化した誘電材料を含むものである、請求項17に記載のインプロセスユニット。
- 少なくともいくつかのチャネルが第1の端部及び第2の端部を有し、前記チャネルの各々が前記第2の基板の少なくとも1つの縁において露出している、請求項17に記載のインプロセスユニット。
- 前記チャネルのうちの少なくとも1つが誘電材料を含むものである、請求項17に記載のインプロセスユニット。
- 前記複数のチャネルのうちの少なくとも2つが交差している、請求項17に記載のインプロセスユニット。
- 前記第1のマイクロ電子素子及び前記第2のマイクロ電子素子が、複数の縁を有する矩形形状であり、少なくともいくつかのチャネルが、前記複数の縁のうちの少なくともいくつかにまで延びている、請求項17に記載のインプロセスユニット。
- 前記マイクロ電子素子が、少なくとも実質的に円形状のウェハであり、少なくともいくつかのチャネルが前記ウェハの縁まで延びている、請求項17に記載のインプロセスユニット。
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US12/970,529 US8652935B2 (en) | 2010-12-16 | 2010-12-16 | Void-free wafer bonding using channels |
US12/970,529 | 2010-12-16 | ||
PCT/US2011/064884 WO2012082881A2 (en) | 2010-12-16 | 2011-12-14 | Void-free wafer bonding using channels |
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EP (1) | EP2652782A2 (ja) |
JP (1) | JP2014504014A (ja) |
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US9067779B1 (en) | 2014-07-14 | 2015-06-30 | Butterfly Network, Inc. | Microfabricated ultrasonic transducers and related apparatus and methods |
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EP3758050A1 (en) | 2016-03-07 | 2020-12-30 | GlobalWafers Co., Ltd. | Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof |
CN111115555B (zh) * | 2019-12-20 | 2023-08-29 | 北京航天控制仪器研究所 | 一种用于mems晶圆级共晶键合封装的硅槽结构及制备方法 |
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- 2011-12-14 JP JP2013544739A patent/JP2014504014A/ja active Pending
- 2011-12-14 EP EP11805336.2A patent/EP2652782A2/en not_active Withdrawn
- 2011-12-14 KR KR1020137018118A patent/KR20140031183A/ko not_active Application Discontinuation
- 2011-12-14 CN CN201180067645.1A patent/CN103370783B/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
TWI479633B (zh) | 2015-04-01 |
US8652935B2 (en) | 2014-02-18 |
US20120153426A1 (en) | 2012-06-21 |
CN103370783B (zh) | 2016-02-03 |
CN103370783A (zh) | 2013-10-23 |
KR20140031183A (ko) | 2014-03-12 |
WO2012082881A3 (en) | 2012-08-23 |
WO2012082881A2 (en) | 2012-06-21 |
TW201241986A (en) | 2012-10-16 |
EP2652782A2 (en) | 2013-10-23 |
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