JP2014220489A - 半導体装置、およびその作製方法 - Google Patents
半導体装置、およびその作製方法 Download PDFInfo
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- JP2014220489A JP2014220489A JP2014075039A JP2014075039A JP2014220489A JP 2014220489 A JP2014220489 A JP 2014220489A JP 2014075039 A JP2014075039 A JP 2014075039A JP 2014075039 A JP2014075039 A JP 2014075039A JP 2014220489 A JP2014220489 A JP 2014220489A
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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Abstract
Description
本実施の形態では、本発明の一態様の半導体装置の例として、画像表示装置の構成例とその作製方法例について図面を参照して説明する。以下では、画像表示装置の一例として、有機EL素子を備える画像表示装置(以下、表示装置ともいう)について説明する。
図1(A)に上面射出(トップエミッション)方式が採用された表示装置100の上面概略図を示す。なお、図1(A)には明瞭化のため、構成要素の一部を省略して示している。
以下では、上述した各要素に用いることのできる材料及び形成方法について説明する。
可撓性を有する基板の材料としては、有機樹脂や可撓性を有する程度に薄いガラス材料などを用いることができる。
発光素子124において、光射出側に設ける電極にはEL層142からの発光に対して透光性を有する材料を用いる。
接着層、封止層としては、例えば、二液混合型樹脂、熱硬化性樹脂、光硬化性樹脂などの硬化性材料や、ゲルなどを用いることができる。例えば、エポキシ樹脂やアクリル樹脂、シリコーン樹脂、フェノール樹脂、ポリイミド、ポリビニルクロライド(PVC)、ポリビニルブチラル(PVB)、エチレンビニルアセテート(EVA)などを用いることができる。特に、エポキシ樹脂等の透湿性が低い材料が好ましい。
表示部102、信号線駆動回路103、走査線駆動回路104を構成するトランジスタの構造は特に限定されない。例えば、トランジスタの構成は、スタガ型のトランジスタ、逆スタガ型のトランジスタなどを用いてもよい。また、トップゲート型またはボトムゲート型のいずれのトランジスタ構造としてもよい。また、チャネルエッチ型のトランジスタ、または、チャネル保護型のトランジスタを用いてもよい。チャネル保護型の場合、チャネル領域の上にのみ、チャネル保護膜を設けてもよい。または、ソースドレイン電極と半導体層とを接触させる部分のみ開口し、その開口以外の場所にも、チャネル保護膜を設けてもよい。
被剥離層112は、基板101や接着層111を透過した不純物が拡散することを抑制する機能を有する。また、トランジスタの半導体層に接する被剥離層112や絶縁層138、またトランジスタを覆う絶縁層134や絶縁層135は、半導体層への不純物の拡散を抑制することが好ましい。これらの層には、例えばシリコンなどの半導体の酸化物または窒化物、アルミニウムなどの金属の酸化物または窒化物を用いることができる。また、このような無機絶縁材料の積層膜、または無機絶縁材料と有機絶縁材料の積層膜を用いてもよい。
カラーフィルタ145は、発光素子124からの発光色を調色し、色純度を高める目的で設けられている。例えば、白色発光の発光素子を用いてフルカラーの表示装置とする場合には、異なる色のカラーフィルタを設けた複数の画素を用いる。その場合、赤色(R)、緑色(G)、青色(B)の3色のカラーフィルタを用いてもよいし、これに黄色(Y)を加えた4色とすることもできる。また、R、G、B、(及びY)に加えて白色(W)の画素を用い、4色(または5色)としてもよい。
以下では、上記表示装置100の作製方法の一例について、図面を参照して説明する。特に本構成例では、多面取りを想定した表示装置100の作製方法例について説明する。
まず、支持基板151上に剥離層152を形成する。
続いて、剥離層152上に被剥離層112を形成する。
続いて、加熱処理を行い、酸化物層を変質させる。加熱処理を行うことにより、被剥離層112から水素が放出され、酸化物層に供給される。
続いて、被剥離層112上に半導体膜を成膜する。その後、半導体膜上にフォトリソグラフィ法等を用いてレジストマスクを形成し、半導体膜の不要な部分をエッチングにより除去する。その後レジストマスクを除去することにより、トランジスタを構成する半導体層131と、半導体層110を形成する(図4(B))。
続いて、半導体層110、半導体層131を覆って絶縁層138を形成する。
続いて、絶縁層138上に導電膜を成膜する。その後、導電膜上にフォトリソグラフィ法等を用いてレジストマスクを形成し、導電膜の不要な部分をエッチングにより除去する。その後レジストマスクを除去することにより、ゲート電極132を形成する。
続いて、トランジスタを構成する半導体層131の、ゲート電極132と重ならない領域に、不純物をドープする。ドーパントとしては、n型のドーパントであるリンやヒ素、p型のドーパントであるホウ素、アルミニウムなどを用いることができる。
続いて、絶縁層138、ゲート電極132を覆う絶縁層134と、絶縁層135を成膜する。
続いて、絶縁層138、絶縁層134及び絶縁層135に、半導体層131の不純物領域の一部に達する開口部を形成する。このとき同時に、半導体層110の上面の一部が露出するように、半導体層110上の絶縁層138、絶縁層134及び絶縁層135にも開口を形成する(図4(C))。
続いて、上記開口部、及び絶縁層135上に導電膜を成膜する。その後導電膜上にフォトリソグラフィ法等を用いてレジストマスクを形成し、導電膜の不要な部分をエッチングにより除去する。その後レジストマスクを除去することにより、トランジスタのソース電極またはドレイン電極として機能する電極133と、導電層120を形成する(図4(D))。
続いて、平坦化層として機能する絶縁層136を形成する。このとき、電流制御用のトランジスタ122の一方の電極133、半導体層110、及び外部接続端子105となる配線のそれぞれに達する開口部を絶縁層136に形成する。
続いて、絶縁層136上に導電膜を成膜する。その後導電膜上にフォトリソグラフィ法等を用いてレジストマスクを形成し、導電膜の不要な部分をエッチングにより除去する。その後レジストマスクを除去することにより、トランジスタの一方の電極133と電気的に接続する第1の電極141を形成する。
続いて、第1の電極141の端部を覆う絶縁層137を形成する(図5(A))。このとき、半導体層110、及び外部接続端子105となる配線のそれぞれに達する開口部を絶縁層137に形成する。
続いて、剥離層152と被剥離層112との間で剥離する(図5(B))。
その後、被剥離層112の剥離面側に接着層111を介して可撓性を有する基板101を貼り付ける。
続いて、第1の電極141上にEL層142、第2の電極143を順次形成することにより、発光素子124を形成する(図5(C))。
続いて、カラーフィルタ145及びブラックマトリクス146が形成された基板130を準備する。
続いて、基板101及び基板130をそれぞれ切断し、複数の表示装置100を個々に分断する(図6(B))。
本実施の形態では、実施の形態1で例示した表示装置とは異なる表示装置の構成例について説明する。なお以下では、実施の形態1と重複する部分については、説明を省略する。
以下では、表示素子として液晶素子が適用された画像表示装置の構成例について説明する。
本実施の形態では、本発明の一態様の半導体装置の例として、表示装置を備える電子機器の例について説明する。
まず、支持基板として用いるガラス基板上に厚さ約200nmの酸化窒化シリコン膜をプラズマCVD法により形成した。次いで、剥離層として厚さ約50nmのタングステン膜をスパッタリング法により成膜した。次いで、被剥離層として厚さ約600nmの酸化窒化シリコン膜、厚さ約200nmの窒化シリコン膜、厚さ約200nmの酸化窒化シリコン膜、厚さ約140nmの窒化酸化シリコン膜、及び厚さ約100nmの酸化窒化シリコン膜を連続してプラズマCVD法により成膜した。
続いて、基板の分断前後において、半導体層及び導電層近傍の光学顕微鏡による観察を行った。
101 基板
102 表示部
103 信号線駆動回路
104 走査線駆動回路
105 外部接続端子
110 半導体層
111 接着層
112 被剥離層
113 封止層
114 接着層
120 導電層
121 トランジスタ
122 トランジスタ
123 トランジスタ
124 発光素子
130 基板
131 半導体層
132 ゲート電極
133 電極
134 絶縁層
135 絶縁層
136 絶縁層
137 絶縁層
138 絶縁層
140 切断部
141 電極
142 EL層
143 電極
145 カラーフィルタ
146 ブラックマトリクス
151 支持基板
152 剥離層
200 表示装置
221 トランジスタ
222 トランジスタ
224 液晶素子
231 半導体層
232 ゲート電極
233 電極
238 絶縁層
241 電極
242 液晶
243 電極
245 カラーフィルタ
7100 携帯電話機
7101 筐体
7102 表示部
7103 操作ボタン
7104 外部接続ポート
7105 スピーカ
7106 マイク
7107 カメラ
7108 アイコン
7200 携帯表示装置
7201 筐体
7202 表示部
7203 操作ボタン
7204 送受信装置
7300 携帯情報端末
7301 筐体
7302 表示部
7303 バンド
7304 バックル
7305 操作ボタン
7306 入出力端子
7307 アイコン
Claims (5)
- 可撓性を有する基板の一表面上に、
トランジスタ及び表示素子を有する表示部と、
前記表示部の周囲を囲うように配置された半導体層と、
前記トランジスタ、及び前記半導体層上に、絶縁層と、を有し、
前記表面に垂直な方向から見て、
前記基板の端部と、前記半導体層の端部とが概略一致し、
且つ、前記絶縁層の端部が、前記半導体層上に位置する、
半導体装置。 - 前記半導体層は、前記トランジスタのチャネルが形成される半導体と同一の材料を含む、
請求項1に記載の、半導体装置。 - 前記表示部と、前記半導体層との間に、前記表示部を囲うように配置された導電層を有する、
請求項1または請求項2に記載の、半導体装置。 - 前記導電層は、前記トランジスタのゲート電極、ソース電極、またはドレイン電極と同一の材料を含む、
請求項3に記載の、半導体装置。 - 支持基板上に剥離層を形成し、
前記剥離層上に被剥離層を形成し、
前記被剥離層上に、トランジスタと、前記トランジスタの周囲を囲う半導体層と、を形成し、
前記トランジスタ及び半導体層上に、前記半導体層上に開口部を有する絶縁層を形成し、
前記被剥離層から、前記剥離層及び前記支持基板を剥離し、
前記被剥離層の剥離された面に可撓性基板を貼り付け、
前記開口部と重なる位置において、前記可撓性基板、前記被剥離層、及び前記半導体層を分断する、
半導体装置の作製方法。
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JP6321432B2 (ja) | 2018-05-09 |
KR20140122669A (ko) | 2014-10-20 |
JP2018141992A (ja) | 2018-09-13 |
US20140306288A1 (en) | 2014-10-16 |
TWI692108B (zh) | 2020-04-21 |
US10134904B2 (en) | 2018-11-20 |
CN104103677A (zh) | 2014-10-15 |
JP2020122972A (ja) | 2020-08-13 |
CN104103677B (zh) | 2018-12-21 |
DE102014206530A1 (de) | 2014-10-16 |
KR102212242B1 (ko) | 2021-02-04 |
TW201820635A (zh) | 2018-06-01 |
JP6895559B2 (ja) | 2021-06-30 |
US20160111550A1 (en) | 2016-04-21 |
TWI611582B (zh) | 2018-01-11 |
US9257560B2 (en) | 2016-02-09 |
TW201503370A (zh) | 2015-01-16 |
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