JP2014216562A - 多層基板およびこれを用いた電子装置 - Google Patents
多層基板およびこれを用いた電子装置 Download PDFInfo
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- JP2014216562A JP2014216562A JP2013094373A JP2013094373A JP2014216562A JP 2014216562 A JP2014216562 A JP 2014216562A JP 2013094373 A JP2013094373 A JP 2013094373A JP 2013094373 A JP2013094373 A JP 2013094373A JP 2014216562 A JP2014216562 A JP 2014216562A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
【解決手段】ランド61の下方においてビルドアップ層30内のガラスクロス30bをランド61側に変形させる。そして、樹脂層30cのうちガラスクロス30bからランド61側の表面までの厚みa1がコア層20側の表面までの厚みb1よりも厚くなるようにする。これにより、よりクラックが小さな段階からクラックの進展や拡大を抑制できる。したがって、クラックの進展および拡大を遅らせることが可能となる。その結果、クラックが発生しても、ランドと内層配線との間の絶縁性が確保され、これらの間がショートすることを抑制することが可能となる。
【選択図】図2
Description
本発明の第1実施形態について説明する。なお、本実施形態の電子装置は、例えば、自動車等の車両に搭載され、車両用の各種電子装置を駆動するために適用されると好適である。
なお、本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
20 コア層
30 ビルドアップ層
30b ガラスクロス
30c 樹脂層
51 内層配線
61 ランド
121〜123 電子部品
130 はんだ
150 モールド樹脂
Claims (4)
- 表面(20a)を有するコア層(20)と、
前記コア層の表面に形成された内層配線(51)と、
前記コア層の表面に前記内層配線を覆う状態で配置され、ガラス繊維を編み込んでフィルム状としたガラスクロス(30b)および該ガラスクロスの表裏両面を覆う樹脂層(30c)とを有して構成されたビルドアップ層(30)と、
前記ビルドアップ層のうち前記コア層と反対側の一面(30a)に形成され、はんだ(130)を介して電子部品(121〜123)が搭載されるランド(61)と、を備え、
前記ビルドアップ層のうち、前記ランドと前記コア層の間に位置する部分は、前記ガラスクロスが前記ランド側に押し出され、当該部分において、前記樹脂層のうち前記ガラスクロスから前記ランド側の表面までの厚み(a1)が前記ガラスクロスから前記コア層側の表面までの厚み(b1)よりも薄くされていることを特徴とする多層基板。 - 前記ランドの外側においては、前記樹脂層のうち前記ガラスクロスから前記ランド側の表面までの厚み(a2)が前記ガラスクロスから前記コア層側の表面までの厚み(b2)と等しくなっていることを特徴とする請求項1に記載の多層基板。
- 前記ランドと前記コア層との間に前記内層配線が備えられており、該内層配線を押出部材として、前記ガラスクロスが前記ランド側に押し出されていることを特徴とする請求項1または2に記載の多層基板。
- 請求項1ないし3のいずれか1つに記載の多層基板と、
前記ランドの前記一面にのみ配置された前記はんだと、
前記はんだを介して前記ランドに搭載された前記電子部品と、
前記電子部品および前記ランドを封止し、前記ランドの側面と密着するモールド樹脂(150)と、を備える電子装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013094373A JP6075187B2 (ja) | 2013-04-26 | 2013-04-26 | 多層基板およびこれを用いた電子装置 |
US14/785,422 US20160105958A1 (en) | 2013-04-26 | 2014-04-21 | Multi-layer substrate, electronic device using multi-layer substrate, manufacturing method for multilayer substrate, substrate, and electronic device using substrate |
CN201480023607.XA CN105247972A (zh) | 2013-04-26 | 2014-04-21 | 多层基板、使用多层基板的电子装置、多层基板的制造方法、基板以及使用基板的电子装置 |
PCT/JP2014/002233 WO2014174827A1 (ja) | 2013-04-26 | 2014-04-21 | 多層基板、多層基板を用いた電子装置、多層基板の製造方法、基板、および基板を用いた電子装置 |
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JP2013094373A JP6075187B2 (ja) | 2013-04-26 | 2013-04-26 | 多層基板およびこれを用いた電子装置 |
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JP2014216562A true JP2014216562A (ja) | 2014-11-17 |
JP6075187B2 JP6075187B2 (ja) | 2017-02-08 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002158442A (ja) * | 2000-11-20 | 2002-05-31 | Nippon Mektron Ltd | 多層プリント基板およびその積層方法 |
JP2013021306A (ja) * | 2011-06-17 | 2013-01-31 | Sumitomo Bakelite Co Ltd | プリント配線板および製造方法 |
JP2013089745A (ja) * | 2011-10-18 | 2013-05-13 | Panasonic Corp | 多層プリント配線基板とその製造方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002158442A (ja) * | 2000-11-20 | 2002-05-31 | Nippon Mektron Ltd | 多層プリント基板およびその積層方法 |
JP2013021306A (ja) * | 2011-06-17 | 2013-01-31 | Sumitomo Bakelite Co Ltd | プリント配線板および製造方法 |
JP2013089745A (ja) * | 2011-10-18 | 2013-05-13 | Panasonic Corp | 多層プリント配線基板とその製造方法 |
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