JP2014165491A - 基板ストリップ - Google Patents
基板ストリップ Download PDFInfo
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- JP2014165491A JP2014165491A JP2013234019A JP2013234019A JP2014165491A JP 2014165491 A JP2014165491 A JP 2014165491A JP 2013234019 A JP2013234019 A JP 2013234019A JP 2013234019 A JP2013234019 A JP 2013234019A JP 2014165491 A JP2014165491 A JP 2014165491A
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- 239000000758 substrate Substances 0.000 title claims abstract description 90
- 239000002184 metal Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000000463 material Substances 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000000465 moulding Methods 0.000 description 29
- 239000004065 semiconductor Substances 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000003795 chemical substances by application Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】本発明の実施形態による基板ストリップは、複数の基板ユニットが形成された基板領域と、前記基板領域を囲むダミー領域と、前記ダミー領域に所定の大きさに形成された複数の金属パターンと、前記金属パターンの間に形成されたリブパターンと、を含む。
【選択図】図1
Description
110 基板ユニット
200 ダミー領域
210 金属パターン
211 第1金属パターン
212 第2金属パターン
220 リブパターン
Claims (13)
- 複数の基板ユニットが形成された基板領域と、
前記基板領域を囲むダミー領域と、
前記ダミー領域に所定の大きさに形成された複数の金属パターンと、
前記複数の金属パターンの間に形成されたリブパターンと、を含む、基板ストリップ。 - 前記複数の金属パターンのそれぞれは、
所定の間隔で配列された複数の第1金属パターンと、
前記複数の第1金属パターンの間に形成された第2金属パターンと、を含む、請求項1に記載の基板ストリップ。 - 前記複数の金属パターンのそれぞれは、円形状に形成される、請求項2に記載の基板ストリップ。
- 前記複数の第1金属パターンのそれぞれは、500μm〜650μmの直径に形成される、請求項3に記載の基板ストリップ。
- 前記第2金属パターンは、前記複数の第1金属パターンのそれぞれの直径より小さい直径を有する、請求項3又は4に記載の基板ストリップ。
- 前記第2金属パターンは、前記複数の第1金属パターンのそれぞれの直径の1/3〜1/2の直径に形成される、請求項3から5のいずれか一項に記載の基板ストリップ。
- 前記複数の金属パターンのそれぞれは多角形状に形成される、請求項2に記載の基板ストリップ。
- 前記複数の第1金属パターンのそれぞれは、0.78mm2〜1.32mm2の面積に形成される、請求項7に記載の基板ストリップ。
- 前記第2金属パターンは、前記複数の第1金属パターンのそれぞれの面積より小さい面積を有する、請求項7又は8に記載の基板ストリップ。
- 前記リブパターンは、前記複数の金属パターンを連結するために形成される、請求項1から9のいずれか一項に記載の基板ストリップ。
- 前記リブパターンは、90〜100μmの幅を有する直線形状に形成される、請求項1から10のいずれか一項に記載の基板ストリップ。
- 前記複数の金属パターンとリブパターンとは、前記ダミー領域の全面積の50〜70%を占めるように形成される、請求項1から11のいずれか一項に記載の基板ストリップ。
- 前記複数の金属パターンとリブパターンは銅材質で形成される、請求項1から12のいずれか一項に記載の基板ストリップ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2013-0019129 | 2013-02-22 | ||
KR1020130019129A KR101472660B1 (ko) | 2013-02-22 | 2013-02-22 | 기판 스트립 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014165491A true JP2014165491A (ja) | 2014-09-08 |
JP5754864B2 JP5754864B2 (ja) | 2015-07-29 |
Family
ID=51387925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013234019A Expired - Fee Related JP5754864B2 (ja) | 2013-02-22 | 2013-11-12 | 基板ストリップ |
Country Status (3)
Country | Link |
---|---|
US (1) | US9318356B2 (ja) |
JP (1) | JP5754864B2 (ja) |
KR (1) | KR101472660B1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017183532A (ja) * | 2016-03-30 | 2017-10-05 | 富士通株式会社 | 配線基板の製造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101853838B1 (ko) * | 2016-01-11 | 2018-06-15 | (주)심텍 | 인쇄회로 스트립 기판 및 이의 제조 방법 |
KR20230116165A (ko) * | 2022-01-28 | 2023-08-04 | 엘지이노텍 주식회사 | 스마트 ic 기판 모듈 및 스마트 ic 기판 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0479465U (ja) * | 1990-11-20 | 1992-07-10 | ||
JP2003168848A (ja) * | 2001-11-30 | 2003-06-13 | Nec Kansai Ltd | 配線基板 |
JP2006108289A (ja) * | 2004-10-04 | 2006-04-20 | Yazaki Corp | プリント配線板 |
JP2008004631A (ja) * | 2006-06-20 | 2008-01-10 | Sharp Corp | フレキシブルプリント配線板の基板母材およびフレキシブルプリント配線板の製造方法 |
JP2009500830A (ja) * | 2005-06-30 | 2009-01-08 | サンディスク コーポレイション | 封止された集積回路パッケージにおける歪みを減らす方法 |
JP2009290080A (ja) * | 2008-05-30 | 2009-12-10 | Ngk Spark Plug Co Ltd | 多層配線基板の中間製品、多層配線基板の製造方法 |
JP2011243876A (ja) * | 2010-05-20 | 2011-12-01 | Furukawa Electric Co Ltd:The | プリント配線基板 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100194130B1 (ko) * | 1994-03-30 | 1999-06-15 | 니시무로 타이죠 | 반도체 패키지 |
JP3310617B2 (ja) * | 1998-05-29 | 2002-08-05 | シャープ株式会社 | 樹脂封止型半導体装置及びその製造方法 |
KR20060065245A (ko) * | 2004-12-10 | 2006-06-14 | 삼성테크윈 주식회사 | 반도체 팩키지용 기판 스트립 |
KR101068263B1 (ko) | 2009-08-13 | 2011-09-28 | 삼성전기주식회사 | 기판 스트립 |
-
2013
- 2013-02-22 KR KR1020130019129A patent/KR101472660B1/ko active IP Right Grant
- 2013-11-12 JP JP2013234019A patent/JP5754864B2/ja not_active Expired - Fee Related
- 2013-11-13 US US14/079,024 patent/US9318356B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0479465U (ja) * | 1990-11-20 | 1992-07-10 | ||
JP2003168848A (ja) * | 2001-11-30 | 2003-06-13 | Nec Kansai Ltd | 配線基板 |
JP2006108289A (ja) * | 2004-10-04 | 2006-04-20 | Yazaki Corp | プリント配線板 |
JP2009500830A (ja) * | 2005-06-30 | 2009-01-08 | サンディスク コーポレイション | 封止された集積回路パッケージにおける歪みを減らす方法 |
JP2008004631A (ja) * | 2006-06-20 | 2008-01-10 | Sharp Corp | フレキシブルプリント配線板の基板母材およびフレキシブルプリント配線板の製造方法 |
JP2009290080A (ja) * | 2008-05-30 | 2009-12-10 | Ngk Spark Plug Co Ltd | 多層配線基板の中間製品、多層配線基板の製造方法 |
JP2011243876A (ja) * | 2010-05-20 | 2011-12-01 | Furukawa Electric Co Ltd:The | プリント配線基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017183532A (ja) * | 2016-03-30 | 2017-10-05 | 富士通株式会社 | 配線基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140240949A1 (en) | 2014-08-28 |
KR101472660B1 (ko) | 2014-12-12 |
JP5754864B2 (ja) | 2015-07-29 |
KR20140105200A (ko) | 2014-09-01 |
US9318356B2 (en) | 2016-04-19 |
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