JP2014164054A5 - - Google Patents

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Publication number
JP2014164054A5
JP2014164054A5 JP2013033870A JP2013033870A JP2014164054A5 JP 2014164054 A5 JP2014164054 A5 JP 2014164054A5 JP 2013033870 A JP2013033870 A JP 2013033870A JP 2013033870 A JP2013033870 A JP 2013033870A JP 2014164054 A5 JP2014164054 A5 JP 2014164054A5
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JP
Japan
Prior art keywords
pattern
target pattern
pattern elements
target
substrate
Prior art date
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Application number
JP2013033870A
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English (en)
Japanese (ja)
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JP6141044B2 (ja
JP2014164054A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP2013033870A external-priority patent/JP6141044B2/ja
Priority to JP2013033870A priority Critical patent/JP6141044B2/ja
Priority to TW103102266A priority patent/TWI536093B/zh
Priority to US14/174,083 priority patent/US8943446B2/en
Priority to KR1020140017053A priority patent/KR20140105379A/ko
Priority to CN201410053642.8A priority patent/CN104007607B/zh
Publication of JP2014164054A publication Critical patent/JP2014164054A/ja
Publication of JP2014164054A5 publication Critical patent/JP2014164054A5/ja
Priority to KR1020160097715A priority patent/KR101682336B1/ko
Publication of JP6141044B2 publication Critical patent/JP6141044B2/ja
Application granted granted Critical
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2013033870A 2013-02-22 2013-02-22 生成方法、プログラム及び情報処理装置 Expired - Fee Related JP6141044B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2013033870A JP6141044B2 (ja) 2013-02-22 2013-02-22 生成方法、プログラム及び情報処理装置
TW103102266A TWI536093B (zh) 2013-02-22 2014-01-22 產生方法，儲存媒體及資訊處理裝置
US14/174,083 US8943446B2 (en) 2013-02-22 2014-02-06 Generation method, storage medium and information processing apparatus
KR1020140017053A KR20140105379A (ko) 2013-02-22 2014-02-14 생성 방법, 기억 매체 및 정보 처리 장치
CN201410053642.8A CN104007607B (zh) 2013-02-22 2014-02-18 产生方法和信息处理装置
KR1020160097715A KR101682336B1 (ko) 2013-02-22 2016-08-01 생성 방법, 기억 매체 및 정보 처리 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013033870A JP6141044B2 (ja) 2013-02-22 2013-02-22 生成方法、プログラム及び情報処理装置

Publications (3)

Publication Number Publication Date
JP2014164054A JP2014164054A (ja) 2014-09-08
JP2014164054A5 true JP2014164054A5 (enExample) 2016-04-14
JP6141044B2 JP6141044B2 (ja) 2017-06-07

Family

ID=51368335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013033870A Expired - Fee Related JP6141044B2 (ja) 2013-02-22 2013-02-22 生成方法、プログラム及び情報処理装置

Country Status (5)

Country Link
US (1) US8943446B2 (enExample)
JP (1) JP6141044B2 (enExample)
KR (2) KR20140105379A (enExample)
CN (1) CN104007607B (enExample)
TW (1) TWI536093B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6712527B2 (ja) * 2016-09-30 2020-06-24 株式会社ブイ・テクノロジー プロキシミティ露光方法
US10318698B2 (en) * 2016-12-14 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for assigning color pattern
CN114638189A (zh) * 2022-03-16 2022-06-17 东方晶源微电子科技（北京）有限公司 一种解决掩模版着色边界冲突的方法、装置和计算机设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7018753B2 (en) * 2003-05-05 2006-03-28 Lsi Logic Corporation Variable mask field exposure
JP4585197B2 (ja) * 2003-12-22 2010-11-24 ルネサスエレクトロニクス株式会社 レイアウト設計方法およびフォトマスク
JP4229829B2 (ja) * 2003-12-26 2009-02-25 Ｎｅｃエレクトロニクス株式会社 ホールパターン設計方法、およびフォトマスク
US7310797B2 (en) 2005-05-13 2007-12-18 Cadence Design Systems, Inc. Method and system for printing lithographic images with multiple exposures
US7745067B2 (en) * 2005-07-28 2010-06-29 Texas Instruments Incorporated Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements
JP2007258366A (ja) * 2006-03-22 2007-10-04 Toshiba Corp パターン処理方法
US8073808B2 (en) * 2007-04-19 2011-12-06 D-Wave Systems Inc. Systems, methods, and apparatus for automatic image recognition
JP4779003B2 (ja) * 2007-11-13 2011-09-21 エーエスエムエル ネザーランズ ビー．ブイ． フルチップ設計のパターン分解を行うための方法
JP5100625B2 (ja) * 2008-12-11 2012-12-19 株式会社東芝 パターンレイアウト設計方法
US8402396B2 (en) 2009-09-29 2013-03-19 The Regents Of The University Of California Layout decomposition for double patterning lithography
US8448120B2 (en) * 2011-05-09 2013-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. RC extraction for single patterning spacer technique

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