JP2014154205A5 - - Google Patents

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Publication number
JP2014154205A5
JP2014154205A5 JP2014021382A JP2014021382A JP2014154205A5 JP 2014154205 A5 JP2014154205 A5 JP 2014154205A5 JP 2014021382 A JP2014021382 A JP 2014021382A JP 2014021382 A JP2014021382 A JP 2014021382A JP 2014154205 A5 JP2014154205 A5 JP 2014154205A5
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JP
Japan
Prior art keywords
cell
resistance
bias signal
data
tracking
Prior art date
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Application number
JP2014021382A
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English (en)
Japanese (ja)
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JP2014154205A (ja
JP5918284B2 (ja
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Publication date
Priority claimed from US13/761,301 external-priority patent/US9058869B2/en
Application filed filed Critical
Publication of JP2014154205A publication Critical patent/JP2014154205A/ja
Publication of JP2014154205A5 publication Critical patent/JP2014154205A5/ja
Application granted granted Critical
Publication of JP5918284B2 publication Critical patent/JP5918284B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014021382A 2013-02-07 2014-02-06 メモリセルの抵抗偏移を逆転させるためのバイアス信号のメモリセルへの印加 Expired - Fee Related JP5918284B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/761,301 US9058869B2 (en) 2013-02-07 2013-02-07 Applying a bias signal to memory cells to reverse a resistance shift of the memory cells
US13/761,301 2013-02-07

Publications (3)

Publication Number Publication Date
JP2014154205A JP2014154205A (ja) 2014-08-25
JP2014154205A5 true JP2014154205A5 (enExample) 2014-10-02
JP5918284B2 JP5918284B2 (ja) 2016-05-18

Family

ID=51259092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014021382A Expired - Fee Related JP5918284B2 (ja) 2013-02-07 2014-02-06 メモリセルの抵抗偏移を逆転させるためのバイアス信号のメモリセルへの印加

Country Status (4)

Country Link
US (1) US9058869B2 (enExample)
JP (1) JP5918284B2 (enExample)
KR (1) KR101677583B1 (enExample)
CN (1) CN103985416B (enExample)

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US9798623B2 (en) * 2012-05-11 2017-10-24 Seagate Technology Llc Using cache to manage errors in primary storage
US9785499B2 (en) * 2014-02-12 2017-10-10 Seagate Technology Llc Hot-read data aggregation and code selection
WO2016042902A1 (ja) * 2014-09-16 2016-03-24 ソニー株式会社 メモリコントローラ、記憶装置、情報処理システムおよび不揮発メモリの制御方法
US9583183B2 (en) * 2014-09-26 2017-02-28 Sandisk Technologies Llc Reading resistive random access memory based on leakage current
KR102298607B1 (ko) 2015-02-17 2021-09-06 삼성전자주식회사 저항성 메모리 시스템 및 저항성 메모리 시스템의 동작 방법
US9690656B2 (en) * 2015-02-27 2017-06-27 Microsoft Technology Licensing, Llc Data encoding on single-level and variable multi-level cell storage
US9786386B2 (en) * 2015-02-27 2017-10-10 Microsoft Technology Licensing, Llc Dynamic approximate storage for custom applications
US10008277B2 (en) * 2016-09-12 2018-06-26 Sandisk Technologies Llc Block health monitoring using threshold voltage of dummy memory cells
US10283212B2 (en) 2016-11-29 2019-05-07 International Business Machines Corporation Built-in self-test for embedded spin-transfer torque magnetic random access memory
DE102018132503B4 (de) * 2018-12-17 2020-09-17 Infineon Technologies Ag Detektion von Codewörtern
KR102161833B1 (ko) * 2018-12-31 2020-10-05 성균관대학교산학협력단 온도 정보를 활용한 멀티 레벨 셀 상변화 메모리 스크러빙 장치
JP2020149752A (ja) 2019-03-15 2020-09-17 キオクシア株式会社 記憶装置
CN111210858B (zh) * 2019-12-24 2021-11-09 山东大学 一种缓解相变存储器写干扰的方法及系统
WO2021152338A1 (en) * 2020-01-28 2021-08-05 Micron Technology, Inc. Analog storage using memory device
CN113687773B (zh) * 2021-07-16 2023-08-11 深圳智慧林网络科技有限公司 数据压缩模型训练方法及装置、存储介质
DE102021121750A1 (de) * 2021-08-23 2023-02-23 Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen, Körperschaft des öffentlichen Rechts Verfahren zum Betreiben einer elektrisch programmierbaren Speicherzelle mit einem Chalkogenid für Mehrfach-Pegel Datenspeicher
JP2023137091A (ja) * 2022-03-17 2023-09-29 キオクシア株式会社 メモリシステムおよびメモリ制御方法

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JPS62256575A (ja) 1986-04-30 1987-11-09 Fuji Xerox Co Ltd 感熱記録装置
US5657332A (en) 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
JP4129170B2 (ja) 2002-12-05 2008-08-06 シャープ株式会社 半導体記憶装置及びメモリセルの記憶データ補正方法
US6930909B2 (en) * 2003-06-25 2005-08-16 Micron Technology, Inc. Memory device and methods of controlling resistance variation and resistance profile drift
US8531863B2 (en) 2005-05-20 2013-09-10 Adesto Technologies Corporation Method for operating an integrated circuit having a resistivity changing memory cell
WO2007132457A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US7623401B2 (en) * 2006-10-06 2009-11-24 Qimonda North America Corp. Semiconductor device including multi-bit memory cells and a temperature budget sensor
KR101374319B1 (ko) * 2007-08-24 2014-03-17 삼성전자주식회사 가변 저항 메모리 장치 및 그것의 동작 방법
JP5262402B2 (ja) 2008-08-04 2013-08-14 富士通株式会社 記憶装置及びデータ保持方法
US7929338B2 (en) * 2009-02-24 2011-04-19 International Business Machines Corporation Memory reading method for resistance drift mitigation
KR20100096616A (ko) 2009-02-25 2010-09-02 삼성전자주식회사 저항성 메모리 장치 및 저항성 메모리 장치에서의 입출력 제어 방법
US8053255B2 (en) 2009-03-03 2011-11-08 Seagate Technology Llc STRAM with compensation element and method of making the same
US8467237B2 (en) 2010-10-15 2013-06-18 Micron Technology, Inc. Read distribution management for phase change memory
US8719647B2 (en) * 2011-12-15 2014-05-06 Micron Technology, Inc. Read bias management to reduce read errors for phase change memory

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