JP2014120529A - Circuit board, led module and led package, and method of manufacturing circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board in which sulfurization of silver plating is suppressed on the LED reflection surface, and to provide an LED module using such a circuit board, and an LED package.SOLUTION: A circuit board comprises a metal substrate (base metal substrate 2) composed of one kind selected from copper, a copper alloy, aluminum, a columnar metal part (metal bump 3) formed on the metal substrate and comprises one kind selected from copper, a copper alloy, aluminum, nickel, an insulation resin layer (insulation resin layer 4) formed around the side face of the columnar metal part, a metal layer (pad 6c) formed on the insulation resin layer and columnar metal part, and a silver plating layer (LED side silver plating layer 10) formed at least above a metal layer on the columnar metal part. A zinc oxide film (surface zinc oxide film 11) is formed on the silver plating layer surface.

Description

  The present invention relates to a circuit board for mounting an LED (Light Emitting Diode), an LED module and an LED package having an LED chip mounted on the circuit board, and a method for manufacturing the circuit board.

Conventionally, an LED module and an LED package in which an LED chip is directly mounted on a resin circuit board, a ceramic substrate, or a lead frame are used as a light source of a backlight such as an illumination light source or a liquid crystal television device ( For example, see Patent Documents 1 to 3.
In recent years, LEDs have been required to maintain luminance for more than 50,000 hours at the same time as the increase in luminance, and the temperature of the LED chip is lowered for the circuit board on which the LED chip is mounted. Accordingly, there is a demand for circuit boards that have high heat dissipation and are not easily affected by sulfur in the atmosphere.

In the circuit board, a columnar metal portion (hereinafter also referred to as “metal bump”) for mounting an LED chip is formed on a metal substrate (hereinafter also referred to as “base metal substrate”) as a base substrate. .
The metal bumps electrically connect the base metal substrate and the LED chip and radiate heat generated by the LED chip to the base metal substrate.

JP 2009-278012 A Japanese Patent Laid-Open No. 4-338692 Japanese Patent Laid-Open No. 5-29371

In recent LEDs, there is a problem of luminance reduction due to insufficient heat dissipation due to high power, and improvement in reliability reduction is also required due to outdoor use in severe environments.
In particular, in the case of a high power LED module, there is an increased chance of being used outdoors, and there is a problem of reliability that the brightness is significantly reduced due to exposure to moisture and impurities in the atmosphere at high temperatures in the atmosphere.
Sulfur as an atmospheric impurity causes a sulfurization action on the LED chip mounted on the circuit board and the silver plating layer formed to reflect the light emitted by the LED chip with high brightness, There is a problem in that the corrosion is caused by the generated silver sulfide, the reflectance is lowered, and the luminance is lowered.

As a result of diligent research, the present inventors first discovered a technique for forming (covering) an inorganic film on a silver plating layer on a bump using a circuit board on which a metal bump is formed in order to improve heat dissipation. An LED module having an LED chip mounted on the circuit board and an LED package have been provided.
The present invention has been completed based on these points. Specifically, a zinc oxide film was formed on the silver plating layer on the circuit board on which metal bumps having high heat dissipation were formed by electrolytic treatment, thereby obtaining a circuit board with less luminance reduction due to sulfurization.

  That is, the circuit board of the present invention is formed on a metal substrate (base metal substrate 2) selected from copper, copper alloy, and aluminum, and selected from copper, copper alloy, aluminum, and nickel. A columnar metal portion (metal bump 3) using one kind of metal, an insulating resin layer (insulating resin layer 4) formed around the side surface of the columnar metal portion, an insulating resin layer, and a columnar metal portion A metal layer (metal plating layer 6) formed on the substrate, and a nickel plating layer and a palladium plating are formed on all metal layers (first peripheral pattern portion 6a, second peripheral pattern portion 6b, pad 6c) of the metal substrate. A layer and a gold plating layer are formed as necessary, and at least on the pad 6c on the columnar metal part, a silver plating layer (silver plating layer 10) is further formed on the uppermost layer of the formed plating layer. Forming a zinc oxide film (the surface zinc oxide film 11) in the silver-plated layer (see FIG. 1 (i)).

  In the LED module and the LED package of the present invention, the LED chip is mounted on such a metal layer.

  In the circuit board manufacturing method of the present invention, a columnar metal portion is formed on a metal substrate (base metal substrate 2), and a columnar hole portion (hole portion 4a) corresponding to the shape of the columnar metal portion is formed. A columnar metal part (metal bump 3) is inserted into the hole of the insulating resin layer (insulating resin layer 4). Next, a metal layer is arrange | positioned on an insulating resin layer, and a metal substrate, an insulating resin layer, and a metal layer (metal layer 5) are crimped | bonded by heating and pressurizing the obtained laminated body. Thereafter, a metal layer (metal plating layer 6) is formed on the columnar metal portion, and at least a silver plating layer (silver plating layer 10) is formed above the metal layer (metal plating layer 6) on the columnar metal portion. A zinc oxide film (surface zinc oxide film 11) is formed on the surface of the plating layer.

  Alternatively, in the method for manufacturing a circuit board according to the present invention, a columnar metal portion (metal bump 3) is formed on a metal substrate (base metal substrate 2), and an insulating resin layer is disposed on the metal substrate and the columnar metal portion. Next, a metal layer (metal layer 5) is disposed on the insulating resin layer, and the resulting laminate is heated and pressed to pressure-bond the metal substrate, the insulating resin layer, and the metal layer. Thereafter, the insulating resin layer on the columnar metal part is removed, and a metal layer (metal plating layer 6) is formed on the columnar metal part. At least a silver plating layer (silver plating layer 10) is formed above the metal layer (metal plating layer 6) on the columnar metal portion, and a zinc oxide film (surface zinc oxide film 11) is formed on the surface of the silver plating layer.

  According to such a circuit board manufacturing method of the present invention, since the metal bump is provided, the heat dissipation is high, and the highly reliable circuit board capable of suppressing the sulfidation of the silver plating layer by the zinc oxide film. Can be easily manufactured.

  ADVANTAGE OF THE INVENTION According to this invention, the circuit board by which the sulfidation of the silver plating in the surface (henceforth "LED reflective surface") which receives the reflected light of the light which a LED chip light-emits was suppressed can be provided. It is possible to provide an LED module on which an LED chip is mounted on a metal layer of a circuit board, and further an LED package having an external terminal and mounting the LED chip.

It is a schematic diagram for demonstrating an example of the preparation process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (1) in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the bump formation process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the layer arrangement | positioning process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the press process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the convex part removal process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the metal plating process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (2) in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the pattern formation process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the multilayer metal plating process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the zinc oxide process process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating the other example of the zinc oxide process process in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating formation of the hole part to the insulating resin layer in the manufacturing method of the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the preparation process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (1) in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the bump formation process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the layer arrangement | positioning process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the press process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the convex part removal process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the metal plating process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (2) in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the pattern formation process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the multilayer metal plating process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating an example of the zinc oxide process process in the manufacturing method of the circuit board of 2nd Embodiment. It is a schematic diagram for demonstrating the other example of the zinc oxide process process in the manufacturing method of the circuit board of 1st Embodiment. It is side surface sectional drawing of the LED module using the circuit board of 1st Embodiment. It is a schematic diagram for demonstrating an example of the preparation process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (1) in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the circuit formation process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the layer arrangement | positioning process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the press process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the convex part removal process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the metal plating process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (2) in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the surface pattern formation process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the resist arrangement | positioning process (3) in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the back surface pattern formation process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the multilayer metal plating process in the manufacturing method of the circuit board of 3rd Embodiment. It is a schematic diagram for demonstrating an example of the zinc oxide process process in the manufacturing method of the circuit board of 3rd Embodiment. It is side surface sectional drawing of the LED package using the circuit board of 3rd Embodiment.

Embodiments to which the present invention is applied will be described below.
The circuit board according to the present invention includes, for example, a base metal substrate 2 made of one selected from copper, copper alloy, and aluminum, as shown in FIG. A metal bump 3 made of one selected from copper, copper alloy, aluminum and nickel, an insulating resin layer 4 formed around the side surface of the metal bump 3, and the metal bump 3 and the insulating resin layer 4 In the circuit board having the metal layer (the metal layer 5 and the metal plating layer 6 (first peripheral pattern portion 6a, second peripheral pattern portion 6b, pad 6c)) formed on the metal bump 3, at least the pad 6c is formed on the metal bump 3. An LED side silver plating layer 10 is formed above the surface, and a surface zinc oxide film 11 is formed on the LED side silver plating layer 10. LED side nickel plating layer 7c, LED side palladium plating layer 8c, and LED side on all circuit parts (first peripheral pattern part 6a, second peripheral pattern part 6b, pad 6c on metal bump 3) on the circuit board The gold plating layer 9c and the LED side silver plating layer 10 are formed. Thereafter, a treatment for forming the surface zinc oxide film 11 may be performed, and the metal layers (metal layer 5, first peripheral pattern portion 6a, second peripheral pattern portion 6b) other than the pad 6c are respectively provided with the first. You may make it form the electrode side nickel plating layer 7a and the 1st electrode side gold plating layer 9a, the 2nd electrode side nickel plating layer 7b, and the 2nd electrode side gold plating layer 9b.

  Next, a manufacturing method for manufacturing such a circuit board of the present invention will be described.

<First Embodiment>
An example of a manufacturing process for manufacturing the circuit board according to the first embodiment will be described.
The manufacturing process of the circuit board according to the first embodiment includes the following steps.
1-1. Preparation step 1-2. Resist placement process (1)
1-3. Bump formation process 1-4. Layer arrangement step 1-5. Pressing process 1-6. Convex part removal process 1-7. Metal plating step 1-8. Resist placement process (2)
1-9. Pattern forming step 1-10. Multi-layer metal plating (nickel, palladium, gold, silver plating) step 1-11. Zinc oxide treatment process

(1-1. Preparation process)
First, as shown in FIG. 1A, a metal plate 1 for forming a base metal substrate 2 and metal bumps 3 in a later bump formation step is prepared.
Although the thickness of the metal plate 1 is not specifically limited, For example, it can be set as 10 micrometers-30000 micrometers.
The metal constituting the metal plate 1 is preferably a metal with high heat dissipation and high electrical conductivity since the metal bumps 3 are formed. Specifically, one type of metal selected from copper, a copper alloy, and aluminum is preferable, and copper is particularly preferable from the viewpoint of thermal conductivity and electrical conductivity.

(1-2. Resist placement step (1))
Next, as shown in FIG. 1B, the etching resist M is disposed at a position where the metal bump 3 is formed on the metal plate 1.
(1-3. Bump formation process)
Next, as shown in FIG. 1C, by selectively etching the metal plate 1 using the etching resist M, metal bumps (columnar metal portions) are formed on the LED chip mounting position on the circuit board. 3 is formed. The shape of the metal bump 3 is not particularly limited and may be, for example, a triangle or a quadrangle, but is usually a columnar shape with a circular upper surface.

  As described above, the metal constituting the metal bump 3 is preferably a metal with high heat dissipation and high electrical conductivity, and specifically, from one selected from copper, copper alloy, aluminum, and nickel. In particular, copper is more preferable from the viewpoint of thermal conductivity and electrical conductivity.

  Examples of the etching resist M include a photosensitive resin and a dry film resist (photoresist).

As an etching method, an etching method using various etching liquids according to the type of each metal constituting the metal plate 1 can be used.
When the metal plate 1 is copper, a commercially available alkaline etching solution such as ammonium persulfate or hydrogen peroxide-sulfuric acid can be used. After etching a portion of the metal plate 1 other than the portion whose surface is masked with the etching resist M, the etching resist M is removed.

  The method for removing the etching resist M may be selected as appropriate according to the type of the etching resist M, such as chemical removal and peeling removal. For example, in the case of photosensitive ink formed by screen printing, it is removed with chemicals such as alkali.

  The formation method of the metal bump is not limited to the example of forming the metal bump 3 described above. For example, metal bumps may be formed by the methods described in Japanese Patent Nos. 3217381 and 3178777.

Thus, by using the circuit board on which the metal bumps 3 are formed, an LED module with high heat dissipation can be obtained later. Moreover, by making the area (bump area) of the upper surface of the metal bump 3 larger (for example, an area of 9 mm ² or more) than before, higher heat dissipation can be ensured in the LED module.

(1-4. Layer arrangement process)
Next, as shown in FIG. 1D, the insulating resin layer 4 is disposed on the base metal substrate 2, and the metal layer 5 is disposed on the insulating resin layer 4.
As the insulating resin layer 4, a layer in which a columnar hole portion 4 a corresponding to the shape of the metal bump 3 is formed is used. This layer arranging step includes a bump insertion step of inserting the metal bump 3 into the hole portion 4 a of the insulating resin layer 4.
The area of the hole portion on the upper surface side of the insulating resin layer 4 (hereinafter also referred to as “hole area”) is slightly larger than the bump area of the metal bump 3.

In the bump insertion step, the center of the upper surface of the metal bump 3 formed on the base metal substrate 2 and the center of the hole portion on the upper surface side of the insulating resin layer 4 overlap so that the hole portion 4a of the insulating resin layer 4 is overlapped. Insert metal bumps 3 into Thereby, the insulating resin layer 4 is arrange | positioned in the position where the metal bump 3 on the base metal substrate 2 is not formed.
In this way, the insulating resin layer 4 is disposed on the base metal substrate 2, and the insulating resin layer is formed at least around the side surface of the metal bump 3.
By using the insulating resin layer 4 in which the hole portion 4a is formed, even when the bump area of the metal bump 3 is large, no resin exists on the metal bump 3, so that connection reliability (electrical and electrical) A high-performance circuit board with high mechanical properties can be manufactured.

  The insulating material constituting the insulating resin layer 4 is not particularly limited. For example, a material containing a predetermined material for increasing the strength of the insulating resin layer 4 is included in the insulating resin having heat resistance required for a normal wiring board while being deformed and solidified by heating and pressing. it can. For example, composites (prepregs) in which fibers such as glass fibers (glass cloth), ceramic fibers, and aramid fibers are combined with insulating resins made of various reaction curable resins such as polyimide resins, phenol resins, and epoxy resins. Can be mentioned.

By forming the insulating resin layer 4 as such a composite, it is possible to prevent the insulating resin layer 4 from undergoing a shape change such as cracking or peeling when the hole portion 4a is formed by drilling or the like.
In particular, glass cloth is preferable because the strength of the insulating resin layer 4 can be easily increased.
Examples of the insulating resin in the composite of the insulating resin layer 4 include resins that are excellent in bonding strength with the base metal substrate 2 in a cured state and that do not impair the withstand voltage characteristics.

As such a resin, for example, in addition to an epoxy resin, a phenol resin, and a polyimide resin, various engineering plastics can be used alone or in admixture of two or more. Among these, an epoxy resin is preferable because it is excellent in bonding strength between metals.
Among epoxy resins, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, hydrogenated bisphenol A type epoxy resin, hydrogenated bisphenol F type epoxy resin, and bisphenol A type epoxy resin structure with high fluidity at both ends A triblock polymer having a bisphenol F type epoxy resin structure at both ends is preferable.

  The insulating resin of the insulating resin layer 4 may contain a heat conductive filler in order to increase the heat conductivity.

  As shown in FIG. 2A, the insulating resin layer 4 for forming the hole portion 4a is an insulating member having a predetermined thickness. The thickness of the insulating resin layer 4 is not particularly limited, but is preferably about the same as the height of the metal bump 3. In consideration of pressurization in a subsequent pressing step, the metal bump 3 may be slightly thicker than the height.

The hole 4a in the insulating resin layer 4 can be formed by the following forming method, for example.
As shown in FIG. 2B, when the hole portion 4a is formed in the insulating resin layer 4, drilling is performed using a processing tool 30 such as a drill or a router having a convex tip processing portion 30a.
Thereby, as shown in the top view of the insulating resin layer 4 in FIG. 2C, a circular hole portion 4a penetrating the upper and lower surfaces of the insulating resin layer 4 is formed.

  Instead of such drilling, the hole portion 4a is formed by punching the insulating resin layer 4 with a conventional press working such as metal pressing using a metal mold or a Thomson blade. It may be.

  Furthermore, as shown in FIG. 2 (c), the shape of the hole portion 4a is assumed to be a cylindrical shape whose upper surface is circular when viewed from above the insulating resin layer 4. It is not intended to be limited to. According to the shape of the metal bump 3, the shape of the upper surface may be a square, a rectangle, a triangle, or the like, or any shape. In addition, the shape of the column need not be the same length from the upper side to the lower side of the insulating resin layer 4. For example, the shape of the hole may be a truncated cone.

  The metal layer 5 is not particularly limited, but can be a copper foil. Various commercially available copper foils can be used.

(1-5. Pressing process)
Next, as shown in FIG.1 (e), the upper surface of the metal layer 5 is heated and pressurized (hot press). Thereby, the base metal substrate 2, the insulating resin layer 4, and the metal layer 5 are pressure-bonded.
Due to the presence of the metal bump 3, a convex portion A is formed on the metal bump 3 in response to the metal layer 5 being deformed into a concave shape by hot pressing, and in the pressing step, a laminate having the convex portion A is formed. .

  As a heating and pressurizing method, a heating / pressurizing device (thermal laminator, heating press device) or the like may be used. In this case, in order to avoid air contamination, the atmosphere is set to a vacuum (vacuum laminator, etc.). Also good. Various conditions such as heating temperature and pressure may be set as appropriate according to the material and thickness of the insulating resin layer 4, and the pressure may be set to 0.5 MPa to 30 MPa, for example.

  The sheet material only needs to be a material that allows concave deformation at the time of heating press, and examples thereof include cushion paper, rubber sheet, elastomer sheet, nonwoven fabric, woven fabric, porous sheet, foam sheet, metal foil, and composites thereof. be able to. In particular, elastically deformable materials such as cushion paper, rubber sheets, elastomer sheets, foam sheets, and composites thereof are preferable.

(1-6. Projection removal process)
Next, as shown in FIG. 1 (f), a process of removing the protrusion A on the metal bump 3 is performed, and the upper surface of the metal bump 3 is exposed to form a flat surface B. When removing the protrusion A, the protrusion A is removed so that the upper surface of the metal layer 5 and the upper surface of the metal bump 3 are flattened. Thus, the height from the bottom surface of the base metal substrate 2 to the top surface of the metal bump 3 is made equal to the height from the bottom surface of the base metal substrate 2 to the top surface of the metal layer 5.

Examples of the method for removing the convex portion A include grinding and polishing.
For example, a method using a grinding apparatus having a hard rotating blade in which a plurality of hard blades made of diamond or the like are arranged in the radial direction of the rotating plate, a sander, a belt sander, a grinder, a surface grinder, a hard abrasive molded product, or the like is used. Methods and the like.
When the grinding apparatus is used, the upper surface of the metal bump 3 can be flattened by moving the hard rotary blade along the upper surface of the wiring substrate fixedly supported.
Examples of the polishing method include a method of lightly polishing by a belt sander, buffing or the like.

(1-7. Metal plating process)
Next, as shown in FIG. 1G, a metal plating layer is formed by, for example, electroless plating and electrolytic plating so as to cover the exposed metal bump 3 upper surface, insulating resin layer 4 upper surface, and metal layer 5 upper surface. 6 is formed. Alternatively, although not shown, only the exposed upper surface of the metal bump 3 may be metal-plated.
As the plating metal species of the metal plating layer 6, for example, copper, silver, nickel and the like are preferable. Examples of the method for forming the metal plating layer 6 include a panel plating method for forming a pattern using an etching resist, and a pattern plating method for forming by plating using a resist for pattern plating.

(1-8. Resist placement step (2))
Next, as shown in FIG. 1H, etching resists N ₁ , N ₂ , and N ₃ are formed to form a first peripheral pattern portion 6a, a second peripheral pattern portion 6b, and a pad 6c, which will be described later, of the metal plating layer 6, respectively. It arranges on the upper surface of the part to do.

(1-9. Pattern formation step)
Next, as shown in FIG. 1I, the metal plating layer 6 is partially etched with a predetermined pattern by etching resists N ₁ , N ₂ , and N ₃ . Thereby, the pattern part, that is, the pad 6c on which the LED chip is mounted, the first peripheral pattern part 6a, and the second peripheral pattern part 6b are formed. Thereby, the insulating resin layer 4 comes to be exposed from the part (non-pattern part 4b) in which these pattern parts are not formed.

The first peripheral pattern portion 6a and the second peripheral pattern portion 6b sandwiching the metal bump 3 are electrodes that are anodes or cathodes.
When the first peripheral pattern portion 6a forms a cathode, the second peripheral pattern portion 6b forms an anode. The anode or cathode relationship may be reversed.

  The width of the pad 6c is not particularly limited, but needs to be smaller than the width of the LED chip to be mounted. The shape of the upper surface of the pad 6c may be any of a quadrangle and a circle. The width of the non-pattern part 4b is not particularly limited as long as a short circuit can be prevented.

As a method for removing the etching resist _{N 1, N 2, N 3} , drug removed, peeled off or the like may be appropriately selected depending on the type of the etching resist _{N 1, N 2, N 3} . For example, in the case of photosensitive ink formed by screen printing, it is removed with chemicals such as alkali.

(1-10. Multi-layer metal plating (nickel plating, palladium plating, gold plating, silver plating) process)
As shown in FIG. 1 (j), a first electrode side nickel plating layer 7a, a first electrode side palladium plating layer 8a, and a first electrode side gold plating layer 9a are sequentially formed on the first peripheral pattern portion 6a. Thus, the first electrode portion 13 is configured.
Further, the second electrode portion 14 is formed by sequentially forming the second electrode side nickel plating layer 7b, the second electrode side palladium plating layer 8b, and the second electrode side gold plating layer 9b on the second peripheral pattern portion 6b. Configure.
On the pad 6c, an LED side nickel plating layer 7c, an LED side palladium plating layer 8c, an LED side gold plating layer 9c, and an LED side silver plating layer 10 are formed in this order.

  These multilayer metal plating (nickel plating, palladium plating, gold plating, silver plating) will be described in detail below.

The LED side silver plating layer 10 is formed in order to improve the reflection efficiency of the light which a LED chip light-emits in the LED module which mounts an LED chip on a circuit board. The plating treatment for forming the LED side silver plating layer 10 may be either electrolytic silver plating or electroless silver plating, but in order to achieve high reflectivity, electrolytic silver plating is desirable and the thickness is 0.1 μm. It is desirable to be 10 μm.
When performing electrolytic silver plating, an electrode is taken from the base metal substrate 2 (copper plate or the like), and the electrolytic plating is selectively performed on the conductive pad 6c.

  The LED side nickel plating layer 7c is formed to suppress diffusion of metal (copper or the like) from the metal layer 5 and the pad 6c (copper layer or the like) into the LED side silver plating layer 10 inside. The LED side nickel plating layer 7c is formed to a thickness of 0.1 μm to 30 μm by electrolytic plating or electroless plating. Note that the LED-side nickel plating layer 7c is not necessarily formed.

As will be described later, metal wires (gold wires) (first metal wire 42a and second metal wire 42b shown in FIG. 4 later) are wire-bonded above the first peripheral pattern portion 6a and the second peripheral pattern portion 6b. To do. Therefore, in order to improve the reliability in wire bonding, the first electrode side nickel plating layer 7a and the second electrode side nickel plating layer 7b are formed on the first peripheral pattern portion 6a and the second peripheral pattern portion 6b, respectively. The first electrode side palladium plating layer 8b and the second electrode side palladium plating layer 8b are formed on the first electrode side nickel plating layer 7a and the second electrode side nickel plating layer 7b, respectively. A first electrode side gold plating layer 9a and a second electrode side gold plating layer 9b are respectively formed on 8a and the second electrode side palladium plating layer 8b.
The first electrode side nickel plating layer 7a and the second electrode side nickel plating layer 7b are formed by electroless plating, for example, with a thickness of 0.1 μm to 30 μm on the first peripheral pattern portion 6a and the second peripheral pattern portion 6b, respectively. To do.
The first electrode side palladium plating layer 8a and the second electrode side palladium plating layer 8b are electroless plating, for example, 0.01 μm to 5 μm on the first electrode side nickel plating layer 7a and the second electrode side nickel plating layer 7b. Each is formed with a thickness.
The first electrode side gold plating layer 9a and the second electrode side gold plating layer 9b are electroless plating, for example, 0.0001 μm to 5 μm on the first electrode side palladium plating layer 8a and the second electrode side palladium plating layer 8b. Each is formed with a thickness.

  In addition, the 1st electrode side nickel plating layer 7a, the 2nd electrode side nickel plating layer 7b, the 1st electrode side palladium plating layer 8a, the 2nd electrode side palladium plating layer 8b, the 1st electrode side gold plating layer 9a, the 2nd electrode The side gold plating layer 9b is not necessarily formed. Alternatively, the first electrode side gold plating layer 9a and the second electrode side gold plating layer 9b may be directly formed on the first electrode side nickel plating layer 7a and the second electrode side nickel plating layer 7b, respectively. However, in order to further improve the reliability in wire bonding, the first electrode side palladium plating layer 8a is provided between the first electrode side nickel plating layer 7a and the first electrode side gold plating layer 9a. The second electrode side palladium plating layer 8b is preferably formed between the second electrode side nickel plating layer 7b and the second electrode side gold plating layer 9b.

  The LED side nickel plating layer 7c, the LED side palladium plating layer 8c, and the LED side gold plating layer 9c are sequentially formed on the pad 6c by the same process as the plating process on the first peripheral pattern part 6a and the second peripheral pattern part 6b. These are formed with the same thickness. Note that the LED-side nickel plating layer 7c, the LED-side palladium plating layer 8c, and the LED-side gold plating layer 9c are not necessarily formed.

  In place of such a multilayer plating process, the first electrode side nickel is formed on the first peripheral pattern portion 6a, the second peripheral pattern portion 6b, and the pad 6c by electrolytic plating in order to simplify the processing process. A plating layer 7a, a second electrode-side nickel plating layer 7b, and an LED-side nickel plating layer 7c are respectively formed on the first electrode-side nickel plating layer 7a, the second electrode-side nickel plating layer 7b, and the LED-side nickel plating layer 7c. The first electrode side silver plating layer 10a, the second electrode side silver plating layer 10b, and the LED side silver plating layer 10 may be formed by electrolytic plating.

(1-11. Zinc oxide treatment step)
Next, the circuit board (FIG. 1 (j)) that has been subjected to the multilayer metal plating process is immersed in a heated nitric acid solution in which zinc is dissolved, and a cathode electrode is taken from the base metal board 2 to perform an electrolytic process.
Thereby, as shown in FIG.1 (k), the surface zinc oxide film | membrane 11 is formed on the LED side silver plating layer 10 above the metal bump 3. As shown in FIG. By forming this surface zinc oxide film 11, it is possible to suppress the LED side silver plating layer 10 from being corroded by sulfur in the atmosphere on the side of the circuit board on which the LED chip is mounted.

  As shown in FIG. 1 (l), by performing electrolytic treatment using both the back side of the base metal substrate 2 and the upper side of the metal bump 3 as a cathode, a surface zinc oxide film 11 is formed above the metal bump 3, Further, the back surface zinc oxide film 12 may be formed on the back surface of the base metal substrate 2. As a result, the metal (for example, copper) constituting the base metal substrate 2 is corroded by impurities (sulfur, oxygen, etc.) in the atmosphere on the back side of the base metal substrate 2 as well as the side on which the LED chip is mounted on the circuit board Can be suppressed.

The heated nitric acid solution is preferably a nitric acid solution having a zinc concentration of 1 g / L to 10 g / L and a pH of about 4 to pH 6, and the solution temperature is preferably room temperature (about 10 to 28 ° C.) to about 80 ° C. About 40 to 60 ° C. is more preferable.
In addition, you may make it perform the process which wash | cleans the surface of the silver plating layer of a circuit board with nitric acid before performing the electrolytic process (zinc oxide process) which forms such a zinc oxide film | membrane.
A zinc plate is used for the anode. The current density was 0.01 A / dm ² to 0.1 A / dm ² about desirably, electrolysis time is zinc oxide film within one minute is sufficiently formed. The actual electrolysis time may be about 5 seconds, and may be a thin zinc oxide film having a thickness of several nanometers to several hundred nanometers. Even with such a thin zinc oxide film, corrosion due to sulfur in the atmosphere can be sufficiently suppressed.

  Thus, on the pad 6c, the LED side nickel plating layer 7c, the LED side palladium plating layer 8c, the LED side gold plating layer 9c, and the LED side silver plating layer 10 are formed in this order, and the surface is formed on the surface of the LED side silver plating layer 10 The LED mounting portion 15 is configured by forming the zinc oxide film 11.

<Second Embodiment>
Next, an example of a manufacturing process for manufacturing the circuit board according to the second embodiment will be described. Note that description of the same processing as in the first embodiment is omitted.
The manufacturing process of the circuit board according to the second embodiment includes the following processes.
2-1. Preparation step 2-2. Resist placement process (1)
2-3. Bump formation process 2-4. Layer arrangement step 2-5. Pressing step 2-6. Convex part removal process 2-7. Metal plating step 2-8. Resist placement process (2)
2-9. Pattern forming step 2-10. Multi-layer metal plating (nickel, palladium, gold, silver plating) step 2-11. Zinc oxide treatment process

(2-1. Preparation process)
First, as shown in FIG. 3A, a metal plate 1 for forming a base metal substrate 2 and metal bumps 3 in a later bump formation step is prepared.

(2-2. Resist placement step (1))
Next, as shown in FIG. 3B, the etching resist M is disposed at a position where the metal bump 3 is formed on the metal plate 1.
(2-3. Bump formation process)
Next, as shown in FIG. 3C, by selectively etching the metal plate 1 using the etching resist M, metal bumps (columnar metal portions) are formed on the LED chip mounting position on the circuit board. 3 is formed.

(2-4. Layer arrangement process)
Next, as illustrated in FIG. 3D, the insulating resin layer 400 is disposed on the base metal substrate 2, and the metal layer 5 is disposed on the insulating resin layer 400.
Unlike the insulating resin layer 4 used in the first embodiment, the insulating resin layer 400 has a single-layer structure in which the hole portion 4a is not formed. However, other points (material, size, etc.) are insulated. The configuration is the same as that of the resin layer 4. The insulating material constituting the insulating resin layer 400 is not particularly limited, and any of the materials mentioned as the material constituting the insulating resin layer 4 described above may be used. As the insulating resin layer 400, a composite body (prepreg) can be preferably applied as in the case of the insulating resin layer 4 described above.

(2-5. Pressing process)
Next, as shown in FIG.3 (e), the upper surface of the metal layer 5 is heated and pressurized (hot press). Accordingly, the base metal substrate 2, the insulating resin layer 400, and the metal layer 5 are bonded together by pressure bonding. As a result, a laminated body having a convex portion A ′ made of the insulating resin layer 400 and the metal layer 5 is formed on the metal bump 3.

(2-6. Projection removal step)
Next, as shown in FIG. 3F, a process of removing the protrusion A ′ on the metal bump 3 is performed, and the upper surface of the metal bump 3 is exposed to form a flat surface B.

(2-7. Plating process)
Next, as shown in FIG. 3G, a metal plating layer is formed by, for example, electroless plating and electrolytic plating so as to cover the exposed metal bump 3 upper surface, insulating resin layer 4 upper surface, and metal layer 5 upper surface. 6 is formed. Alternatively, although not shown, the metal plating layer 6 may be formed only on the upper surface of the exposed metal bump 3.

(2-8. Resist placement step (2))
Next, as shown in FIG. 3H, etching resists N ₁ , N ₂ , and N ₃ are formed on the metal plating layer 6 to form the first peripheral pattern portion 6a, the second peripheral pattern portion 6b, and the pad 6c, respectively. Place on the top surface.

(2-9. Pattern formation step)
Next, as shown in FIG. 3I, the metal plating layer 6 is partially etched with a predetermined pattern using etching resists N ₁ , N ₂ , and N ₃ . Thus, the pad 6c, the first peripheral pattern portion 6a, and the second peripheral pattern portion 6b are formed, and further, the insulating resin layer 4 is exposed from the non-pattern portion 4b.

(2-10. Multi-layer metal plating (nickel, palladium, gold, silver plating) process)
As shown in FIG. 3 (j), the first electrode side nickel plating layer 7a, the first electrode side palladium plating layer 8a, and the first electrode side gold plating layer 9a are sequentially formed on the first peripheral pattern portion 6a. Thus, the first electrode portion 13 is configured.
Further, the second electrode portion 14 is formed by sequentially forming the second electrode side nickel plating layer 7b, the second electrode side palladium plating layer 8b, and the second electrode side gold plating layer 9b on the second peripheral pattern portion 6b. Configure.
On the pad 6c, an LED side nickel plating layer 7c, an LED side palladium plating layer 8c, an LED side gold plating layer 9c, and an LED side silver plating layer 10 are formed in this order.

(2-11. Zinc oxide treatment step)
Next, the circuit board (FIG. 3 (j)) that has been subjected to the multilayer metal plating process is immersed in a heated nitric acid solution in which zinc is dissolved, and a cathode electrode is taken from the base metal board 2 to perform electrolytic treatment. As a result, a surface zinc oxide film 11 is formed on the LED-side silver plating layer 10 above the metal bump 3 as shown in FIG.

  Thus, on the pad 6c, the LED side nickel plating layer 7c, the LED side palladium plating layer 8c, the LED side gold plating layer 9c, and the LED side silver plating layer 10 are formed in this order, and the surface is formed on the surface of the LED side silver plating layer 10 The LED mounting portion 15 is configured by forming the zinc oxide film 11.

  As shown in FIG. 3 (l), the surface zinc oxide film 11 is formed above the metal bump 3 by electrolytically treating both the back side of the base metal substrate 2 and the upper side of the metal bump 3 as a cathode, Further, the back surface zinc oxide film 12 may be formed on the back surface of the base metal substrate 2.

<LED module>
An example of a method for manufacturing an LED module by mounting an LED chip on the circuit board manufactured in the first embodiment or the second embodiment will be described. This method is not particularly limited.
For example, as shown in FIG. 4, the LED chip 41 is mounted on the LED mounting portion 15 (on the surface zinc oxide film 11). For simplicity, FIG. 4 shows an LED chip as one LED chip 41, but in practice, a large number of LED chips are usually mounted.
The LED chip 41 is firmly connected to the first electrode portion 13 and the second electrode portion 14 by wire bonding using the first metal wire 42a and the second metal wire 42b, respectively.
Instead of this, the pads 6c and both the first peripheral pattern portion 6a and the second peripheral pattern portion 6b may be connected by solder. Alternatively, the LED chip 41 and the pad 6c can be electrically connected by a conductive paste, an anisotropic conductive film, or the like.
Then, the mounting surface of the LED chip 41 on the circuit board is sealed with a lens-shaped sealing resin (lens resin 43). Thereby, the LED module 50 shown in FIG. 4 is manufactured.

  The lens resin 43 that seals the mounting surface of the LED chip 41 on the circuit board is preferably a transparent synthetic resin that transmits light emitted from the LED chip 41 and has heat resistance against the heat generated by the LED chip 41. Examples of the lens resin 43 include a thermoplastic resin, a thermosetting resin, and a photocurable resin.

More specifically, examples of the lens resin 43 include methacrylic resin, styrene resin, polycarbonate resin, polyester resin, phenoxy resin, butyral resin, cellulose resin, epoxy resin, phenol resin, and silicone resin. be able to.
Examples of the cellulose resin include ethyl cellulose, cellulose acetate, and cellulose acetate butyrate.

The lens resin 43 preferably contains a phosphor in order to improve the emission intensity and to establish a practical emission color. Examples of the phosphor include a yellow light-emitting phosphor, a red light-emitting phosphor, a green light-emitting phosphor, and a phosphor that emits a color between them.
Such phosphors may be inorganic or organic phosphors. Examples of inorganic phosphors include oxide phosphors, nitride phosphors, oxynitride phosphors, and silicate phosphors.

Examples of the yellow light-emitting phosphor include Y and an yttrium aluminum garnet oxide phosphor activated with Ce or Pr, a europium-activated alkaline earth metal represented by (Ba, Ca, Sr) ₂ SiO ₄ : Eu silicate phosphor _can be cited _{Si 12- (m + n) Al} (m + n) n 16-n O n represented by α-sialon phosphor and the like.

Examples of the red light-emitting phosphor include, for example, a europium-activated alkaline earth metal silicate phosphor represented by (Ba, Ca, Sr) ₂ SiO ₄ : Eu, (Mg, Ca, Sr, Ba) ₂ Si ₅ N ₈ : Examples include a europium activated alkaline earth silicon nitride phosphor represented by Eu, a europium activated rare earth oxychalcogenite phosphor represented by (Y, La, Gd, Lu) ₂ O ₂ S: Eu, and the like. .

Examples of the green light emitting phosphor include, for example, a europium activated alkaline earth silicon oxynitride phosphor represented by (Mg, Ca, Sr, Ba) Si ₂ O ₂ N ₂ : Eu, (Ba, Ca, Sr) _2. Examples include a europium activated alkaline earth magnesium silicate phosphor represented by SiO ₄ : Eu, a β sialon phosphor represented by Si _6-Z Al _Z N _8—Z O _Z , and the like.

  The LED module 50 configured as described above is used as an LED light emitting device by arranging a single unit or a plurality of LED modules.

<Third Embodiment>
An example of a manufacturing process for manufacturing the circuit board (LED package circuit board) of the third embodiment will be described. In addition, description is abbreviate | omitted about the process same as 1st Embodiment (or 2nd Embodiment).
The circuit board manufacturing process of the third embodiment includes the following processes in the following order.
3-1. Preparation step 3-2. Resist placement process (1)
3-3. Circuit formation step 3-4. Layer arrangement step 3-5. Pressing step 3-6. Convex part removal process 3-7. Metal plating step 3-8. Resist placement process (2)
3-9. Surface pattern formation step 3-10. Resist placement process (3)
3-11. Back surface pattern forming step 3-12. Multi-layer metal plating (nickel, palladium, gold, silver plating) step 3-13. Zinc oxide treatment process

(3-1. Preparation process)
First, as shown in FIG. 5A, a metal plate 61 for forming the base metal substrate 62, the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c is prepared in a later bump formation step. .

(3-2. Resist placement step (1))
Next, as shown in FIG. 5B, etching resists P ₁ , P ₂ , and P ₃ are formed, and later-described first circuit portion 63a, second circuit portion 63b, and metal bump 63c are formed on the metal plate 61, respectively. Place it at the position you want.

(3-3. Circuit formation process)
Next, as shown in FIG. 5C, the metal plate 61 is selectively etched using the etching resists P ₁ , P ₂ , and P ₃ . Thereby, the metal bump (columnar metal part) 63c is formed at the mounting position of the LED chip on the circuit board, and the first circuit part 63a and the second circuit part 63b are formed.

By using the circuit board on which the metal bumps 63c are formed, an LED package with high heat dissipation can be obtained later. Further, by making the area (bump area) of the upper surface of the metal bump 63c larger (eg, an area of 9 mm ² or more) than before, higher heat dissipation can be ensured in the LED package.

(3-4. Layer arrangement process)
Next, as illustrated in FIG. 5D, the insulating resin layer 64 is disposed on the base metal substrate 62, and the metal layer 65 is disposed on the insulating resin layer 64.
As the insulating resin layer 64, columnar first hole portions 64a, second hole portions 64b, and third hole portions 64c corresponding to the shapes of the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c are formed. Use the same thing. In this layer arrangement step, the first circuit portion 63a is inserted into the first hole portion 64a of the insulating resin layer 64, the second circuit portion 63b is inserted into the second hole portion 64b, and the metal bump 63c is inserted into the third hole portion 64c. It has a metal part insertion process.

In the metal part insertion step, the center of the upper surface of the metal bump 63 c formed on the base metal substrate 62 and the center of the third hole portion 64 c on the upper surface side of the insulating resin layer 64 overlap so that the insulating resin layer 64. The metal bump 63c is inserted into the third hole portion 64c. Similarly, the first circuit portion 63a is inserted into the first hole portion 64a, and the second circuit portion 63b is inserted into the second hole portion 64b. In this way, the insulating resin layer 64 is disposed on the base metal substrate 62, and an insulating resin layer is formed at least around the side surfaces of the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c.
In addition, it is not the insulating resin layer 64 in which the 1st hole part 64a, the 2nd hole part 64b, and the 3rd hole part 64c which were shown in this FIG.5 (d) were formed, but FIG.3 (d) demonstrated in 2nd Embodiment. The insulating resin layer 400 in which no hole is formed as shown in FIG. In this case, processing similar to that described with reference to FIGS. 3D and 3E in the second embodiment is performed.

(3-5. Pressing process)
Next, as shown in FIG.5 (e), the upper surface of the metal layer 65 is heated and pressurized (hot press). Thereby, the base metal substrate 62, the insulating resin layer 64, and the metal layer 65 are pressure-bonded. As a result, the first convex portion A ₁ , the second convex portion A ₂ , and the third convex portion A ₃ are formed by the metal layer 5 on the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c, respectively. The body is formed.

(3-6. Projection removal step)
Next, as shown in FIG. 5F, the first convex portion A ₁ on the first circuit portion 63a, the second convex portion A ₂ on the second circuit portion 63b, and the third convex portion on the metal bump 63c. A ₃ is removed, and the upper surfaces of the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c are exposed, and the first flat surface B ₁ , the second flat surface B ₂ , and the third flat surface are exposed. B ₃ is formed respectively.

(3-7. Metal plating process)
Next, as shown in FIG. 5G, the exposed upper surface of the first circuit portion 63a, the upper surface of the second circuit portion 63b, the upper surface of the metal bump 63c, the upper surface of the insulating resin layer 64, and the upper surface of the metal layer 65 are covered. Further, the metal plating layer 66 is formed by, for example, electroless plating and electrolytic plating. Alternatively, although not shown, only the exposed upper surface of the first circuit portion 63a, the upper surface of the second circuit portion 63b, and the upper surface of the metal bump 63c may be metal-plated.

(3-8. Resist placement step (2))
Next, as shown in FIG. 5H, etching resists Q ₁ , Q ₂ , and Q ₃ are formed on the metal plating layer 66 to form the first peripheral pattern portion 66a, the second peripheral pattern portion 66b, and the pad 66c, respectively. Place on the top surface.

(3-9. Surface pattern formation step)
Next, as shown in FIG. 5I, the metal plating layer 66 is partially etched with a predetermined pattern by the etching resists Q ₁ , Q ₂ , and Q ₃ . As a result, the pad 66c, the first peripheral pattern portion 66a, and the second peripheral pattern portion 66b are formed, and further, the insulating resin layer 64 is formed on the surface side (upper surface side) of the circuit board. The portion not exposed (non-pattern portion 64b) is exposed.

(3-10. Resist placement step (3))
Next, as shown in FIG. 5J, the etching resists R ₁ , R ₂ , and R ₃ are formed on the portions where the first electrode portion 73, the second electrode portion 74, and the pad 75 on the back surface of the base metal substrate 62 are formed. To place.

(3-11. Back surface pattern forming step)
Next, as shown in FIG. 5 (k), the base metal substrate 62 is partially etched with a predetermined pattern by the etching resists R ₁ , R ₂ , R ₃ . Thereby, the first electrode side base portion 62a, the second electrode side base portion 62b, and the LED side base portion 62c are formed. Further, the insulating resin layer 64 is formed on the back surface side of the circuit board. The portion not formed (non-pattern portion 64c) is exposed.

(3-12. Multi-layer metal plating (nickel, palladium, gold, silver plating) process)
As shown in FIG. 5L, a first electrode-side surface nickel plating layer 67a and a first electrode-side surface silver plating layer 68a are sequentially formed on the first peripheral pattern portion 66a by electrolytic plating.
Further, the second electrode side surface nickel plating layer 67b and the second electrode side surface silver plating layer 68b are sequentially formed on the second peripheral pattern portion 66b by electrolytic plating.
On the pad 66c, the LED side surface nickel plating layer 67c and the LED side surface silver plating layer 68c are both formed in order by electrolytic plating.

Moreover, after forming the 1st electrode side back surface nickel plating layer 77a by electrolytic plating on the exposed surface of the 1st electrode side base part 62a of the back surface side of a circuit board, the 1st electrode side back surface silver plating layer 78a is formed by electrolytic plating. Form.
Further, after the second electrode side back surface nickel plating layer 77b is formed by electrolytic plating on the exposed surface of the second electrode side base portion 62b on the back side of the circuit board, the second electrode side back surface silver plating layer 78b is formed by electrolytic plating. Form.
Further, after the LED side back surface nickel plating layer 77c is formed by electrolytic plating on the exposed surface of the LED side base portion 62c on the back side of the circuit board, the LED side back surface silver plating layer 78c is formed by electrolytic plating.

(3-13. Zinc oxide treatment step)
Next, the circuit board (FIG. 5 (l)) subjected to the multilayer metal plating process is immersed in a heated nitric acid solution in which zinc is dissolved, and the entire front and back surfaces of the circuit board (first electrode side base portion 62a, second electrode). A cathode electrode is taken out from the electrode side base portion 62b, the LED side base portion 62c, the first circuit portion 63a, the second circuit portion 63b, and the metal bump 63c), and electrolytic treatment is performed. Thereby, as shown in FIG. 5 (m), the first electrode side surface oxidation is formed on the first electrode side surface silver plating layer 68a, the second electrode side surface silver plating layer 68b, and the LED side silver plating layer 68c. A zinc coating 69a, a second electrode side surface zinc oxide coating 69b, and an LED side surface zinc oxide coating 69c are formed. Along with this, on the exposed surface of the first electrode side back surface silver plating layer 78a on the back surface side of the circuit board, on the exposed surface of the second electrode side back surface silver plating layer 78b, on the exposed surface of the LED side back surface silver plating layer 78c, A first electrode-side back surface zinc oxide film 79a, a second electrode-side back surface zinc oxide film 79b, and an LED-side back surface zinc oxide film 79c are formed.

  As described above, the first electrode side surface nickel plating layer 67a and the first electrode side surface silver plating layer 68a are sequentially formed on the first peripheral pattern portion 66a on the first circuit portion 63a, and the first electrode side surface oxidation is performed. A zinc film 69a is formed. At the same time, after the first electrode side back surface nickel plating layer 77a is formed on the exposed surface of the first electrode side base portion 62a, the first electrode side back surface silver plating layer 78a is formed, and the first electrode side back surface zinc oxide film is formed. 79a is formed. Thereby, the 1st electrode part 83 is comprised.

  Further, in this way, the second electrode side surface nickel plating layer 67b and the second electrode side surface silver plating layer 68b are sequentially formed on the second peripheral pattern portion 66b on the second circuit portion 63b, and the second electrode side A surface zinc oxide film 69b is formed. At the same time, the second electrode side back surface nickel plating layer 77b is formed on the exposed surface of the second electrode side base portion 62b, and then the second electrode side back surface silver plating layer 78b is formed. A film 79b is formed. Thereby, the 2nd electrode part 84 is comprised.

  Further, in this way, the LED side surface nickel plating layer 67c and the LED side surface silver plating layer 68c are sequentially formed on the pad 66c on the metal bump 63c to form the LED side surface zinc oxide film 69c. At the same time, the LED side back surface nickel plating layer 77c is formed on the exposed surface of the LED side base portion 62c, and then the LED side back surface silver plating layer 78c is formed, thereby forming the LED side back surface zinc oxide film 79c. Thereby, the LED mounting part 85 is comprised.

<LED package>
An example of a method for manufacturing an LED package by mounting an LED chip on a circuit board manufactured in the third embodiment will be described. This method is not particularly limited.
For example, as shown in FIG. 6, the LED chip 91 is mounted on the LED mounting portion 85 (LED-side surface zinc oxide film 69c). For simplicity, FIG. 6 shows an LED chip as one LED chip 91, but in practice, a plurality of LED chips are usually mounted. In the LED package, it is usual to mount a smaller number of LED chips than the LED chip mounted on the LED module, which is smaller than the number mounted on the LED module.

The LED chip 91 is firmly connected to the first electrode portion 83 and the second electrode portion 84 by wire bonding using the first metal wire 92a and the second metal wire 92b, respectively.
Instead of this, the pads 66c and both the first peripheral pattern portion 66a and the second peripheral pattern portion 66b may be connected by solder. Alternatively, the LED chip 91 and the pad 66c can be electrically connected by a conductive paste, an anisotropic conductive film, or the like.
Then, the mounting surface of the LED chip 91 on the circuit board is sealed with a lens-shaped sealing resin (lens resin 93). Thereby, the LED package 100 shown in FIG. 6 is manufactured. In this LED package, the back surface side of the first electrode portion 83 and the back surface side of the second electrode portion 84 are used as the first external terminal 83a and the second external terminal 84b, respectively.

  When the LED module 50 has the above-described configuration, and the LED package 100 also has the above-described configuration, and is mounted on a mother board such as a metal substrate or a resin substrate with solder or the like, an appropriate light emission amount can be obtained. The LED light-emitting device which has can be provided.

  Further, the LED module 50 and the LED package 100 configured as described above are widely used for lighting fixtures, light emitting fixtures including liquid crystal TV backlights, and the like. Luminous fixtures include indoor or outdoor lighting, neon lights for advertising, lights installed in tunnels, lighting fixtures such as flashlights, backlights for liquid crystal panels used in personal computers and televisions, automobiles, Examples include headlights and turn signals installed on motorcycles, and light sources of projectors that project images.

  The above embodiment is merely an example, and the manufacturing method, material, and the like can be changed as appropriate.

Hereinafter, specific examples of the present invention will be described.
<Example 1>
First, the etching resist was arrange | positioned in the position which forms the copper bump on a 1 mm-thick copper plate. And the process which selectively etches except the arrangement | positioning part of the etching resist in this copper plate was performed, and the circular copper bump was formed. In addition, parts other than the formation part of the copper bump in the copper plate are a base copper plate (corresponding to the base metal substrate 2).

Next, a 0.06 mm thick insulating resin layer (Hitachi Chemical Co., Ltd. prepreg “GEA-679N”) containing glass cloth in an epoxy insulating resin, and a cylindrical hole portion corresponding to the shape of the copper bump is formed. The layer arrangement process was performed using what was made.
In this layer arrangement process, copper bumps of a copper plate were inserted into the hole portions of the insulating resin layer. Thereby, the insulating resin layer was arrange | positioned on the position (base copper plate) in which the copper bump on a copper plate is not formed.
Next, a copper foil was disposed as a metal layer on the insulating resin layer and the copper bump.

Next, the insulating resin layer was cured by heating and pressurizing for 3 hours at a pressing pressure of 30 kgf / cm ² and a heating temperature of 170 ° C.

  Next, the convex part which arose on the copper bump by this heating and pressurization was removed by grinding | polishing using the grinding | polishing apparatus (Belt Sander, Marugen Iron Works Co., Ltd.).

  Next, after performing electroless and electrolytic copper plating, etching is performed to form a copper plating layer (corresponding to the pad 6c) having a thickness of 0.030 mm on the copper bump, and an electronic component or the like is mounted. Two copper circuits (a circuit having a copper plating layer, corresponding to the first peripheral pattern portion 6a and the second peripheral pattern portion 6b) were formed.

  Next, an electroless nickel plating layer having a thickness of 0.004 mm was formed on all of the copper plating layer and the two copper circuits. Thereafter, an electroless gold plating layer having a thickness of 0.0001 mm was formed on all the electroless nickel plating layers.

  Next, an electrolytic silver plating layer having a thickness of 0.003 mm was formed on the electroless gold plating layer formed in the copper circuit on the copper bump.

Next, using a zinc nitrate solution (pH 5) containing zinc with a zinc concentration of 5 g / L, using a base copper plate as the cathode and a zinc plate as the anode at a solution temperature of 50 ° C., a current density of 0.5 A / Reduction treatment was performed at dm ² for 10 seconds. Thereby, the zinc oxide film was formed on the electrolytic silver plating layer of the copper bump. Thereafter, the circuit board was inspected by a photoelectron spectrometer (XPS: JPS-9010MC manufactured by JEOL Ltd.) to confirm the presence of the zinc oxide film.

  Next, cutting was performed on a circuit board having an outer shape of 3.5 mm × 3.5 mm so that one copper bump was included in one circuit board.

  Next, 60 LED chips were mounted with a silicone die bonding material on a copper land having a copper bump on which an electrolytic silver plating layer of the circuit board was formed and a zinc oxide film was formed. Thereafter, the LED chip and another copper circuit are connected with a gold wire, and the surface of the circuit board on which the LED chip is mounted is silicone-sealing material (product name “OE6636”, manufactured by Toray Dow Corning) Sealed (coated) with. Thus, the LED module of Example 1 was manufactured.

  The LED module of Example 1 was screwed to an aluminum fin and left in a hydrogen sulfide gas of 10 ppm, 40 ° C., 80% RH for 100 hours. This was measured with a total luminous flux meter (HM-9100, manufactured by Otsuka Electronics Co., Ltd.). As a result, the amount of light emitted from the LED chip (light emission amount) in the LED module of Example 1 was reduced to 140 lm / w from the initial value of 150 lm / w.

<Comparative Example 1>
In the following comparative example 1, the description of the members, materials, devices, and the like is omitted for the sake of brevity regarding the same processing as in the first embodiment.

In Comparative Example 1, an LED module was manufactured by performing the same treatment as in Example 1 except that the zinc oxide film was not formed by electrolytic treatment in Example 1.
As a result, the light emission amount of the LED module of Comparative Example 1 was reduced to 98 lm / w with respect to the initial value of 150 lm / w.

  The results of Example 1 and Comparative Example 1 will be described. It can be seen that the LED module of Example 1 has less reduction in the total luminous flux due to hydrogen sulfide than the LED module of Comparative Example 1. That is, the LED module of Example 1 can reduce corrosion of silver by silver sulfide (production of silver sulfide) by forming a zinc oxide film on the surface of the silver plating layer, and the amount of luminous flux emitted from the LED chip. It can be seen that a significant reduction in (light emission amount) could be prevented.

<Example 2>
An etching resist was disposed at a position where a copper bump of a copper plate having a thickness of 0.2 mm was formed and a position where two copper circuits were formed. And the process which selectively etches except the arrangement | positioning part of the etching resist in this copper plate was performed, and the two copper circuits which mount an electronic component etc. were formed with the circular copper bump. In addition, parts other than the formation part of the copper bump and two copper circuits in the copper plate are a base copper plate (corresponding to the base metal substrate 62).

Next, an insulating resin layer (Hitachi Chemical Co., Ltd. prepreg “GEA-679N”) in which glass cloth is contained in epoxy insulating resin is placed on the base copper plate, the copper bump, and the two circuit portions. did.
Next, a copper foil was disposed as a metal layer on the insulating resin layer.

Next, the insulating resin layer was cured by heating and pressurizing for 3 hours at a pressing pressure of 30 kgf / cm ² and a heating temperature of 170 ° C.

  Next, the convex part which arose on the copper bump and two copper circuits by this heating and pressurization was removed by grinding | polishing using the grinding | polishing apparatus (Belt Sander, Marugen Iron Works Co., Ltd.).

  Next, after performing electroless and electrolytic copper plating so as to cover at least the copper bump and the two copper circuits, the thickness of the copper bump is reduced to 0 by performing selective etching using an etching resist. A first copper circuit having a copper plating layer (corresponding to the first peripheral pattern portion 66a in FIG. 5 (k)) and a copper plating layer (corresponding to the second peripheral pattern portion 66b) while forming a .030 mm copper plating layer Formed a second copper circuit having

  Further, selective etching using an etching resist was also performed on the back side of the base copper plate. Thus, three base portions (corresponding to the first electrode side base portion 62a, the second electrode side base portion 62b, and the LED side base portion 62c in FIG. 5K) were formed from the base copper plate.

  Next, all the copper plating layers (corresponding to the first peripheral pattern portion 66a and the second peripheral pattern portion 66b) and all the base portions (the first electrode side base portion 62a, the second electrode side base portion 62b, And an electrolytic nickel plating layer having a thickness of 0.004 mm was formed on the exposed surface of the LED side base portion 62c), and an electrolytic silver plating layer having a thickness of 0.003 mm was further formed on the electrolytic nickel plating layer. .

Next, at a zinc concentration of about 5 g / L, a nitric acid solution pH 5, and a solution temperature of 50 ° C., the entire front and back surfaces of the circuit board (first electrode side base portion 62a, second electrode side base portion 62b, LED side base portion 62c, first side The circuit portion 63a, the second circuit portion 63b, and the entire surface of the circuit board including the metal bumps 63c are equivalent to the entire front and back surfaces of the circuit board, and the anode is made of zinc plate, and the current density is 0.5 A / dm ² for 10 seconds. Processed. Thereby, the zinc oxide film was formed on all the silver plating layers. Thereafter, the circuit board was inspected by a photoelectron spectrometer (XPS: JPS-9010MC manufactured by JEOL Ltd.) to confirm the presence of the zinc oxide film.

  Next, cutting was performed on a circuit board having an outer shape of 3.5 mm × 3.5 mm so that one copper bump was included in one circuit board.

  Next, one LED chip was mounted with a silicone die bonding material on a copper land having a copper bump on which an electrolytic silver plating layer of the circuit board was formed and a zinc oxide film was formed. Thereafter, the LED chip and another copper circuit are connected with a gold wire, and the surface on which the LED chip is mounted on the circuit board is further sealed with a silicone sealing material (product name “OE6636”, manufactured by Toray Dow Corning). Sealed (coated). Thus, the LED package of Example 2 was manufactured.

As a result, the amount of luminous flux (light emission amount) emitted by the LED chip in the LED package of Example 2 was reduced to 75 lm / w with respect to the initial value of 80 lm / w.
<Comparative example 2>
In Comparative Example 2 below, the description of the members, materials, devices, and the like is omitted for the sake of brevity regarding the same processing as in Example 2.

In Comparative Example 2, an LED package was manufactured by performing the same treatment as in Example 2 except that the zinc oxide film was not formed by electrolytic treatment in Example 2.
As a result, the light emission amount in the LED package of Comparative Example 2 was reduced to 56 lm / w with respect to the initial value of 80 lm / w.

  The results of Example 2 and Comparative Example 2 will be described. It can be seen that the LED package of Example 2 has less reduction in the total luminous flux due to hydrogen sulfide than the LED package of Comparative Example 2. That is, the LED package of Example 2 can reduce the corrosion of silver due to hydrogen sulfide by forming a zinc oxide film on the surface of the silver plating layer, and the amount of luminous flux (light emission amount) emitted by the LED chip is remarkable. It can be seen that the reduction could be prevented.

1, 61 Metal plate 2, 62 Base metal substrate 3, 63c Metal bump 4, 64, 400 Insulating resin layer 4a Hole part 4b Non-pattern part 5, 65 Metal layer 6, 66 Metal plating layer 6a, 66a First peripheral pattern part 6b, 66b Second peripheral pattern portion 6c, 66c Pad 30 Processing tool 30a Tip processing portion 7a First electrode side nickel plating layer 7b Second electrode side nickel plating layer 7c LED side nickel plating layer 8a First electrode side palladium plating layer 8b Second electrode side palladium plating layer 8c LED side palladium plating layer 9a First electrode side gold plating layer 9b Second electrode side gold plating layer 9c LED side gold plating layer 10 LED side silver plating layer 10a First electrode side silver plating layer 10b Second electrode side silver plating layer 11 Surface zinc oxide film 12 Back surface zinc oxide film 13, 73, 83 First electrode parts 14, 7 4,84 Second electrode part 15, 85 LED mounting part 41, 91 LED chip 42a, 92a First metal wire 42b, 92b First metal wire 43, 93 Lens resin 50 LED module 62a First electrode side base part 62b Second Electrode side base portion 62c LED side base portion 63a First circuit portion 63b Second circuit portion 64a First hole portion 64b Second hole portion 64c Third hole portion 67a First electrode side surface nickel plating layer 67b Second electrode side surface nickel Plating layer 67c LED side surface nickel plating layer 68a First electrode side surface silver plating layer 68b Second electrode side surface silver plating layer 68c LED side surface silver plating layer 69a First electrode side surface zinc oxide film 69b Second electrode side surface oxidation Zinc coating 69c LED side surface zinc oxide coating 77a First electrode side back surface nickel plating layer 77b Second Polar side back surface nickel plating layer 77c LED side back surface nickel plating layer 78a First electrode side back surface silver plating layer 78b Second electrode side back surface silver plating layer 78c LED side back surface silver plating layer 79a First electrode side back surface silver plating layer 79b Second Electrode side back surface zinc oxide coating 79c LED side back surface zinc oxide coating 100 LED package A, A ′ Convex portion A ₁ First convex portion A ₂ 2nd convex portion A ₃ 3rd convex portion B Flat surface B ₁ 1st flat surface B ₂ Second flat surface B ₃ Third flat surface M, N ₁ , N ₂ , N ₃ , P ₁ , P ₂ , P ₃ etching resist

Claims (6)

A metal substrate made of one selected from copper, copper alloy, and aluminum;
A columnar metal part formed on the metal substrate and made of one kind selected from copper, copper alloy, aluminum and nickel;
An insulating resin layer formed around the side surface of the columnar metal part;
A metal layer formed on the insulating resin layer and the columnar metal part,
A circuit board, wherein at least a silver plating layer is formed above the metal layer on the columnar metal portion, and a zinc oxide film is formed on the surface of the silver plating layer.   An LED module in which an LED (light emitting diode) chip is mounted on the circuit board according to claim 1.   The LED module according to claim 2, wherein a zinc oxide film is formed on the back surface of the metal substrate.   An LED package in which an LED (light emitting diode) chip is mounted on the circuit board according to claim 1. Forming a columnar metal portion on a metal substrate;
Inserting the columnar metal part into the hole part of the insulating resin layer in which a columnar hole part corresponding to the shape of the columnar metal part is formed;
A step of pressure-bonding the metal substrate and the insulating resin layer by heating and pressurizing the insulating resin layer;
Forming a metal layer on the columnar metal part;
Forming at least a silver plating layer above the metal layer on the columnar metal part;
And a step of forming a zinc oxide film on the surface of the silver plating layer. Forming a columnar metal portion on a metal substrate;
Disposing an insulating resin layer on the metal substrate and the columnar metal part;
A step of pressure-bonding the insulating metal layer and the metal substrate by heating and pressurizing the insulating resin layer; and
Removing the insulating resin layer on the columnar metal part;
Forming a metal layer on the columnar metal part;
Forming at least a silver plating layer above the metal layer on the columnar metal part;
And a step of forming a zinc oxide film on the surface of the silver plating layer.

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