JP2014007315A - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】耐熱支持層2に自己粘着エラストマ層3が積層され、この自己粘着エラストマ層3の表面4にセパレータ層が剥離可能に粘着された耐熱フィルム1を使用して半導体パッケージ14を製造する製造方法であり、耐熱フィルム1の自己粘着エラストマ層3からセパレータ層5を剥離し、耐熱フィルム1の自己粘着エラストマ層表面4に厚さ1mm以下の薄いプリント回路基板10を粘着し、このプリント回路基板10上に複数の半導体チップ11をマウントするとともに、プリント回路基板10と複数の半導体チップ11とをハンダ接合し、複数の半導体チップ11をモールド樹脂12により封止してモールド品13を構成し、その後、モールド品13にキュア処理を施す。
【選択図】図5
Description
耐熱フィルムの自己粘着エラストマ層からセパレータ層を剥離し、耐熱フィルムの自己粘着エラストマ層に厚さ1mm以下の薄い回路基板を粘着し、この回路基板上に複数の電子部品をマウントするとともに、回路基板と複数の電子部品とをハンダ接合し、複数の電子部品をモールド樹脂により封止してモールド品を構成し、その後、モールド品にキュア処理を施すことを特徴としている。
また、モールド品を電子部品毎にダイシングすることもできる。具体的には、モールド品から耐熱フィルムを剥離し、この耐熱フィルムの剥離されたモールド品を電子部品毎にダイシングしても良い。
また、請求項3記載の発明によれば、モールド品を電子部品毎にダイシングする前に耐熱フィルムを剥離するので、ダイシングに伴う耐熱フィルムの損傷を抑制したり、使用した耐熱フィルムを再び使用することが可能となる。
2 耐熱支持層
3 自己粘着エラストマ層
4 表面
5 セパレータ層
6 隙間
10 プリント回路基板(回路基板)
11 半導体チップ(電子部品)
12 モールド樹脂
13 モールド品
14 半導体パッケージ
Claims (4)
- 耐熱支持層に自己粘着エラストマ層が積層され、この自己粘着エラストマ層にセパレータ層が剥離可能に粘着された耐熱フィルムを使用して半導体パッケージを製造する半導体パッケージの製造方法であって、
耐熱フィルムの自己粘着エラストマ層からセパレータ層を剥離し、耐熱フィルムの自己粘着エラストマ層に厚さ1mm以下の薄い回路基板を粘着し、この回路基板上に複数の電子部品をマウントするとともに、回路基板と複数の電子部品とをハンダ接合し、複数の電子部品をモールド樹脂により封止してモールド品を構成し、その後、モールド品にキュア処理を施すことを特徴とする半導体パッケージの製造方法。 - 耐熱フィルムの耐熱支持層に略ドット形又は略ストライプ形の自己粘着エラストマ層を積層し、回路基板上に複数の電子部品をマウント後、回路基板と複数の電子部品とにリフロー処理を施してハンダ接合する請求項1記載の半導体パッケージの製造方法。
- モールド品から耐熱フィルムを剥離し、この耐熱フィルムの剥離されたモールド品を電子部品毎にダイシングする請求項1又は2記載の半導体パッケージの製造方法。
- モールド品を電子部品毎にダイシングする請求項1又は2記載の半導体パッケージの製造方法。
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JP2012142677A JP5843709B2 (ja) | 2012-06-26 | 2012-06-26 | 半導体パッケージの製造方法 |
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JP2012142677A JP5843709B2 (ja) | 2012-06-26 | 2012-06-26 | 半導体パッケージの製造方法 |
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JP2014007315A true JP2014007315A (ja) | 2014-01-16 |
JP5843709B2 JP5843709B2 (ja) | 2016-01-13 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170018449A (ko) | 2014-06-26 | 2017-02-17 | 도판 인사츠 가부시키가이샤 | 배선 기판, 반도체 장치 및 반도체 장치의 제조 방법 |
KR20190024444A (ko) * | 2017-08-31 | 2019-03-08 | 주식회사 두산 | 반도체 패키지의 제조방법 |
KR20190087422A (ko) | 2016-11-28 | 2019-07-24 | 미쓰이금속광업주식회사 | 점착 시트 및 그 박리 방법 |
US20220124930A1 (en) * | 2020-10-19 | 2022-04-21 | Quanta Computer Inc. | System and method for determining cable routing between electronic components within a computer chassis |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002076034A (ja) * | 2000-09-01 | 2002-03-15 | Sanyu Rec Co Ltd | 電子部品の製造方法 |
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2012
- 2012-06-26 JP JP2012142677A patent/JP5843709B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002076034A (ja) * | 2000-09-01 | 2002-03-15 | Sanyu Rec Co Ltd | 電子部品の製造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170018449A (ko) | 2014-06-26 | 2017-02-17 | 도판 인사츠 가부시키가이샤 | 배선 기판, 반도체 장치 및 반도체 장치의 제조 방법 |
US9735099B2 (en) | 2014-06-26 | 2017-08-15 | Toppan Printing Co., Ltd. | Wiring substrate, semiconductor device and method for manufacturing semiconductor device |
KR20190087422A (ko) | 2016-11-28 | 2019-07-24 | 미쓰이금속광업주식회사 | 점착 시트 및 그 박리 방법 |
KR20190024444A (ko) * | 2017-08-31 | 2019-03-08 | 주식회사 두산 | 반도체 패키지의 제조방법 |
KR102041676B1 (ko) * | 2017-08-31 | 2019-11-06 | 주식회사 두산 | 반도체 패키지의 제조방법 |
US20220124930A1 (en) * | 2020-10-19 | 2022-04-21 | Quanta Computer Inc. | System and method for determining cable routing between electronic components within a computer chassis |
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JP5843709B2 (ja) | 2016-01-13 |
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