JP2013508970A - マイクロエレクトロニクス・パッケージ及びその製造方法 - Google Patents
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
routing)を可能とし、そして、システムボードレベルピッチでインターフェースするために、非常に大きな基板本体サイズをもたらす。
一実施形態では、マイクロエレクトロニクス・パッケージは、第1表面領域を有する第1基板と、第2表面領域を有する第2基板とを含む。前記第1基板は、その第1表面で第1ピッチを有する第1セットの相互接続と、その第2表面で第2ピッチを有する第2セットの相互接続とを含む。前記第2基板は、前記第2セットの相互接続を使用して、前記第1基板に接続され、前記第2基板は、第3ピッチを有する第3セットの相互接続と、マイクロビアによって相互に結合される第1及び第2の内部導電層とを含む。前記第1ピッチは前記第2ピッチより小さく、前記第2ピッチは前記第3ピッチより小さく、そして、前記第1表面領域は前記第2表面領域よりも小さい。
Claims (13)
- 第1表面領域を有し、第1表面で第1ピッチを有する相互接続の第1セットと、第2表面で第2ピッチを有する相互接続の第2セットとを有する、第1基板と、
第2表面領域を有し、前記相互接続の第2セットを使用して前記第1基板に接続される、第2基板と、
を含む、マイクロエレクトロニクス・パッケージであって、
前記第2基板は、
第3ピッチを有する相互接続の第3セットと、
マイクロビアによって互いに接合される第1及び第2内部導電層と、を有し、
前記第1ピッチは前記第2ピッチより小さく、
前記第2ピッチは前記第3ピッチより小さく、更に、
前記第1表面領域は前記第2表面領域より小さい、
マイクロエレクトロニクス・パッケージ。 - 前記第1基板は、複数のスルーホールを含み、該スルーホールは、200マイクロメーター以下の直径を有し;及び、
前記第1基板は、第1及び第2の導電性トレースを含み、該導電性トレースは、15マイクロメーター以下の厚さをそれぞれ有し、15マイクロメーター以下のスペースによって互いに分離される、請求項1記載のマイクロエレクトロニクス・パッケージ。 - 前記第2基板は、第1及び第2の導電性トレースを含み、該導電性トレースは、75マイクロメーター以下の厚さをそれぞれ有し、75マイクロメーター以下のスペースによって互いに分離される、請求項1記載のマイクロエレクトロニクス・パッケージ。
- 前記第1基板及び前記第2基板の少なくとも1つに配置される統合受動素子を更に含む、請求項1記載のマイクロエレクトロニクス・パッケージ。
- 前記第1基板はコアレス基板である、請求項1記載のマイクロエレクトロニクス・パッケージ。
- 前記第1基板は、400マイクロメーター以下の厚さのコアを有する、請求項1記載のマイクロエレクトロニクス・パッケージ。
- マイクロエレクトロニクス・ダイと、
第1表面領域を有し、第1表面で第1ピッチを有する相互接続の第1セットと、第2表面で第2ピッチを有する相互接続の第2セットとを有する、第1基板と、
第2表面領域を有し、前記相互接続の第2セットを使用して前記第1基板に接続される、第2基板と、
を含む、マイクロエレクトロニクス・パッケージであって、
前記第2基板は、
第3ピッチを有する相互接続の第3セットと、
マイクロビアによって互いに接合される第1及び第2の内部導電層と、を有し、
前記第1ピッチは前記第2ピッチより小さく、
前記第2ピッチは前記第3ピッチより小さく、
前記第1基板は前記相互接続の第1セットを使用して前記マイクロエレクトロニクス・ダイと接続され、及び、
前記第1表面領域は前記第2表面領域より小さい、
マイクロエレクトロニクス・パッケージ。 - 前記第1基板は、400マイクロメーター以下の厚さを有し、
前記第1基板は、200マイクロメーター以下の直径を有する複数のスルーホールを含み、及び、
前記第1基板は、第1及び第2の導電性トレースを含み、該導電性トレースは、15マイクロメーター以下の厚さをそれぞれ有し、15マイクロメーター以下のスペースによって互いに分離される、
請求項7記載のマイクロエレクトロニクス・パッケージ。 - 前記第2基板は、第3及び第4の導電性トレースを含み、該導電性トレースは、75マイクロメーター以下の厚さをそれぞれ有し、75マイクロメーター以下のスペースによって互いに分離される、請求項8記載のマイクロエレクトロニクス・パッケージ。
- マイクロエレクトロニクス・パッケージの製造方法であって、
第1基板を供給するステップと、
基板アセンブリを形成するため、前記第1基板を第2基板に付着するステップであって、該第2基板は、マイクロビアによって互いに接合される第1及び第2の内部導電層を有する、ステップと、
前記基板アセンブリ上で検査を実行し、検査結果を得るステップと、
前記検査結果が所定の条件を満たすなら、その場合だけ、ダイを前記基板アセンブリに付着するステップと、を含む、方法。 - 前記基板アセンブリを補強するステップを更に含む、請求項10記載の方法。
- 前記第1基板は第1表面領域を有し、
前記第1基板は、その第1表面で第1ピッチを有する相互接続の第1セットと、その第2表面で第2ピッチを有する相互接続の第2セットとを含み、及び、
前記第1ピッチは前記第2ピッチよりも小さい、
請求項10記載の方法。 - 前記第2基板は第2表面領域を有し、
前記第2基板は、前記相互接続の第2セットを使用して前記第1基板に接続され、
前記第2基板は、第3ピッチを有する相互接続の第3セットを含み、
前記第2ピッチは前記第3ピッチより小さく、及び、
前記第1表面領域は前記第2表面領域よりも小さい、
請求項12記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US12/590,138 US8035218B2 (en) | 2009-11-03 | 2009-11-03 | Microelectronic package and method of manufacturing same |
US12/590,138 | 2009-11-03 | ||
PCT/US2010/049457 WO2011056306A2 (en) | 2009-11-03 | 2010-09-20 | Microelectronic package and method of manufacturing same |
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JP2013508970A true JP2013508970A (ja) | 2013-03-07 |
JP5536223B2 JP5536223B2 (ja) | 2014-07-02 |
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JP (1) | JP5536223B2 (ja) |
KR (1) | KR101367671B1 (ja) |
CN (1) | CN102598251B (ja) |
DE (1) | DE112010004254B4 (ja) |
GB (1) | GB2487172B (ja) |
TW (1) | TWI420638B (ja) |
WO (1) | WO2011056306A2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8169076B2 (en) * | 2009-06-16 | 2012-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structures having lead-free solder bumps |
US8035218B2 (en) | 2009-11-03 | 2011-10-11 | Intel Corporation | Microelectronic package and method of manufacturing same |
US8866301B2 (en) * | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8643154B2 (en) * | 2011-01-31 | 2014-02-04 | Ibiden Co., Ltd. | Semiconductor mounting device having multiple substrates connected via bumps |
KR101632249B1 (ko) | 2011-10-31 | 2016-07-01 | 인텔 코포레이션 | 멀티 다이 패키지 구조들 |
WO2017111767A1 (en) * | 2015-12-22 | 2017-06-29 | Intel Corporation | Microelectronic devices designed with integrated antennas on a substrate |
US10064277B2 (en) * | 2016-03-29 | 2018-08-28 | Ferric, Inc. | Integrated passive devices and assemblies including same |
WO2018063400A1 (en) | 2016-09-30 | 2018-04-05 | Intel Corporation | Multi-chip package with high density interconnects |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003298232A (ja) * | 2002-04-02 | 2003-10-17 | Sony Corp | 多層配線基板の製造方法および多層配線基板 |
JP2005011908A (ja) * | 2003-06-17 | 2005-01-13 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2006344646A (ja) * | 2005-06-07 | 2006-12-21 | Sumitomo Electric Ind Ltd | 多層基板及び半導体パッケージ |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2966972B2 (ja) * | 1991-07-05 | 1999-10-25 | 株式会社日立製作所 | 半導体チップキャリアとそれを実装したモジュール及びそれを組み込んだ電子機器 |
KR101384035B1 (ko) * | 1999-09-02 | 2014-04-09 | 이비덴 가부시키가이샤 | 프린트배선판 및 그 제조방법 |
US6323735B1 (en) | 2000-05-25 | 2001-11-27 | Silicon Laboratories, Inc. | Method and apparatus for synthesizing high-frequency signals utilizing on-package oscillator circuit inductors |
US6775150B1 (en) * | 2000-08-30 | 2004-08-10 | Intel Corporation | Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture |
JP2003188338A (ja) * | 2001-12-13 | 2003-07-04 | Sony Corp | 回路基板装置及びその製造方法 |
US6713871B2 (en) | 2002-05-21 | 2004-03-30 | Intel Corporation | Surface mount solder method and apparatus for decoupling capacitance and process of making |
US6642158B1 (en) * | 2002-09-23 | 2003-11-04 | Intel Corporation | Photo-thermal induced diffusion |
US7141883B2 (en) | 2002-10-15 | 2006-11-28 | Silicon Laboratories Inc. | Integrated circuit package configuration incorporating shielded circuit element structure |
US6753600B1 (en) * | 2003-01-28 | 2004-06-22 | Thin Film Module, Inc. | Structure of a substrate for a high density semiconductor package |
TW200520121A (en) | 2003-08-28 | 2005-06-16 | Gct Semiconductor Inc | Integrated circuit package having an inductance loop formed from a multi-loop configuration |
KR100745359B1 (ko) * | 2003-12-26 | 2007-08-02 | 가부시키가이샤 무라타 세이사쿠쇼 | 세라믹 다층기판 |
US7589417B2 (en) * | 2004-02-12 | 2009-09-15 | Intel Corporation | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same |
US7230334B2 (en) | 2004-11-12 | 2007-06-12 | International Business Machines Corporation | Semiconductor integrated circuit chip packages having integrated microchannel cooling modules |
KR100714310B1 (ko) | 2006-02-23 | 2007-05-02 | 삼성전자주식회사 | 변압기 또는 안테나를 구비하는 반도체 패키지들 |
US7859098B2 (en) * | 2006-04-19 | 2010-12-28 | Stats Chippac Ltd. | Embedded integrated circuit package system |
US20080237828A1 (en) | 2007-03-30 | 2008-10-02 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same |
US8877565B2 (en) | 2007-06-28 | 2014-11-04 | Intel Corporation | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
JP5079475B2 (ja) * | 2007-12-05 | 2012-11-21 | 新光電気工業株式会社 | 電子部品実装用パッケージ |
US8035218B2 (en) | 2009-11-03 | 2011-10-11 | Intel Corporation | Microelectronic package and method of manufacturing same |
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2009
- 2009-11-03 US US12/590,138 patent/US8035218B2/en active Active
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- 2010-09-20 CN CN201080049669.XA patent/CN102598251B/zh active Active
- 2010-09-20 WO PCT/US2010/049457 patent/WO2011056306A2/en active Application Filing
- 2010-09-20 DE DE112010004254.3T patent/DE112010004254B4/de active Active
- 2010-09-20 JP JP2012535211A patent/JP5536223B2/ja active Active
- 2010-09-20 GB GB1208342.4A patent/GB2487172B/en active Active
- 2010-09-20 KR KR1020127014347A patent/KR101367671B1/ko active IP Right Grant
- 2010-09-21 TW TW099132012A patent/TWI420638B/zh active
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003298232A (ja) * | 2002-04-02 | 2003-10-17 | Sony Corp | 多層配線基板の製造方法および多層配線基板 |
JP2005011908A (ja) * | 2003-06-17 | 2005-01-13 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2006344646A (ja) * | 2005-06-07 | 2006-12-21 | Sumitomo Electric Ind Ltd | 多層基板及び半導体パッケージ |
Also Published As
Publication number | Publication date |
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CN102598251B (zh) | 2015-08-12 |
TW201133754A (en) | 2011-10-01 |
WO2011056306A2 (en) | 2011-05-12 |
DE112010004254B4 (de) | 2021-04-29 |
CN102598251A (zh) | 2012-07-18 |
KR101367671B1 (ko) | 2014-02-27 |
JP5536223B2 (ja) | 2014-07-02 |
GB201208342D0 (en) | 2012-06-27 |
US20110318850A1 (en) | 2011-12-29 |
US20110101516A1 (en) | 2011-05-05 |
KR20120085885A (ko) | 2012-08-01 |
US8035218B2 (en) | 2011-10-11 |
GB2487172A (en) | 2012-07-11 |
GB2487172B (en) | 2014-06-04 |
DE112010004254T5 (de) | 2013-05-02 |
TWI420638B (zh) | 2013-12-21 |
WO2011056306A3 (en) | 2011-08-04 |
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