JP2013175795A - リードフレームの製造方法 - Google Patents

リードフレームの製造方法 Download PDF

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Publication number
JP2013175795A
JP2013175795A JP2013123951A JP2013123951A JP2013175795A JP 2013175795 A JP2013175795 A JP 2013175795A JP 2013123951 A JP2013123951 A JP 2013123951A JP 2013123951 A JP2013123951 A JP 2013123951A JP 2013175795 A JP2013175795 A JP 2013175795A
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JP
Japan
Prior art keywords
element mounting
mounting portion
lead frame
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013123951A
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English (en)
Japanese (ja)
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JP2013175795A5 (enExample
Inventor
Tetsutsugu Hiratsuka
哲嗣 平塚
Yoshitoki Kajiwara
義節 梶原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2013123951A priority Critical patent/JP2013175795A/ja
Publication of JP2013175795A publication Critical patent/JP2013175795A/ja
Publication of JP2013175795A5 publication Critical patent/JP2013175795A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)
JP2013123951A 2013-06-12 2013-06-12 リードフレームの製造方法 Pending JP2013175795A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013123951A JP2013175795A (ja) 2013-06-12 2013-06-12 リードフレームの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013123951A JP2013175795A (ja) 2013-06-12 2013-06-12 リードフレームの製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2011221123A Division JP2012004605A (ja) 2011-10-05 2011-10-05 リードフレームおよびリードフレームの製造方法ならびに半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2013175795A true JP2013175795A (ja) 2013-09-05
JP2013175795A5 JP2013175795A5 (enExample) 2013-10-17

Family

ID=49268363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013123951A Pending JP2013175795A (ja) 2013-06-12 2013-06-12 リードフレームの製造方法

Country Status (1)

Country Link
JP (1) JP2013175795A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170016283A (ko) 2015-08-03 2017-02-13 에스아이아이 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06302736A (ja) * 1993-04-14 1994-10-28 Nec Corp 半導体装置用リードフレームの製造方法および半導体装置
JPH11150216A (ja) * 1997-11-19 1999-06-02 Denso Corp 樹脂封止型半導体部品及びその製造方法
JP2001177035A (ja) * 1999-12-15 2001-06-29 Matsushita Electronics Industry Corp 半導体装置及び半導体装置の製造方法
JP2001185671A (ja) * 1999-12-22 2001-07-06 Mitsubishi Electric Corp 半導体装置の製造方法及び該半導体装置の製造に用いられるリードフレームの製造方法
JP2004351485A (ja) * 2003-05-29 2004-12-16 Matsushita Electric Ind Co Ltd 金属の加工法および加工成形品
JP2005153014A (ja) * 2003-11-05 2005-06-16 Amada Co Ltd 突起部形成方法およびその方法に用いる金型

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06302736A (ja) * 1993-04-14 1994-10-28 Nec Corp 半導体装置用リードフレームの製造方法および半導体装置
JPH11150216A (ja) * 1997-11-19 1999-06-02 Denso Corp 樹脂封止型半導体部品及びその製造方法
JP2001177035A (ja) * 1999-12-15 2001-06-29 Matsushita Electronics Industry Corp 半導体装置及び半導体装置の製造方法
JP2001185671A (ja) * 1999-12-22 2001-07-06 Mitsubishi Electric Corp 半導体装置の製造方法及び該半導体装置の製造に用いられるリードフレームの製造方法
JP2004351485A (ja) * 2003-05-29 2004-12-16 Matsushita Electric Ind Co Ltd 金属の加工法および加工成形品
JP2005153014A (ja) * 2003-11-05 2005-06-16 Amada Co Ltd 突起部形成方法およびその方法に用いる金型

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170016283A (ko) 2015-08-03 2017-02-13 에스아이아이 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
CN106409694A (zh) * 2015-08-03 2017-02-15 精工半导体有限公司 半导体装置及其制造方法
TWI689063B (zh) * 2015-08-03 2020-03-21 日商艾普凌科有限公司 半導體裝置及其製造方法
CN106409694B (zh) * 2015-08-03 2020-08-25 艾普凌科有限公司 半导体装置及其制造方法

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