JP2013115345A - 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体 - Google Patents

部品内蔵基板及びその製造方法並びに部品内蔵基板実装体 Download PDF

Info

Publication number
JP2013115345A
JP2013115345A JP2011262217A JP2011262217A JP2013115345A JP 2013115345 A JP2013115345 A JP 2013115345A JP 2011262217 A JP2011262217 A JP 2011262217A JP 2011262217 A JP2011262217 A JP 2011262217A JP 2013115345 A JP2013115345 A JP 2013115345A
Authority
JP
Japan
Prior art keywords
substrate
component
electronic component
printed wiring
thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011262217A
Other languages
English (en)
Other versions
JP5167516B1 (ja
Inventor
Kazuhisa Itoi
和久 糸井
Masahiro Okamoto
誠裕 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2011262217A priority Critical patent/JP5167516B1/ja
Priority to EP12854222.2A priority patent/EP2787799B1/en
Priority to DK12854222.2T priority patent/DK2787799T3/da
Priority to PCT/JP2012/079463 priority patent/WO2013080790A1/ja
Application granted granted Critical
Publication of JP5167516B1 publication Critical patent/JP5167516B1/ja
Publication of JP2013115345A publication Critical patent/JP2013115345A/ja
Priority to US14/290,173 priority patent/US9591767B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0207Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02311Additive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08237Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11312Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11416Spin coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11418Spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13009Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/1329Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/13294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13309Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13311Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13313Bismuth [Bi] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13316Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13317Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13324Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13344Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13355Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/1336Iron [Fe] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/1339Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16501Material at the bonding interface
    • H01L2224/16503Material at the bonding interface comprising an intermetallic compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802Applying energy for connecting
    • H01L2224/80201Compression bonding
    • H01L2224/80203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399Material
    • H01L2224/804Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/809Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding with the bonding area not providing any mechanical bonding
    • H01L2224/80901Pressing a bonding area against another bonding area by means of a further bonding area or connector
    • H01L2224/80903Pressing a bonding area against another bonding area by means of a further bonding area or connector by means of a bump or layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8185Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8185Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/8349Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9221Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

【課題】電子部品と導熱層との密着性を確保し、放熱特性を向上させる。
【解決手段】部品内蔵基板実装体100は、部品内蔵基板1と、これが実装された実装基板2とからなる。部品内蔵基板1は、第2〜第4プリント配線基材20〜40及びカバーレイフィルム3を熱圧着により一括積層した構造を備える。第2プリント配線基材20の第2樹脂基材21に形成された開口部29内には、電子部品90の裏面91aと導熱層23Aとが密着し、且つ孔部23Bを介して接着層9により固定された状態で内蔵されている。第4プリント配線基材40の実装面2a側にはバンプ49が形成されている。電子部品90の裏面91aに接する導熱層23Aやサーマルビア24を介して、各層のサーマルビア及びサーマル配線を通り、バンプ49から実装基板2に電子部品90の熱が伝わって、実装基板2にて放熱される。
【選択図】図1

Description

この発明は、電子部品が内蔵された部品内蔵基板及びその製造方法並びに部品内蔵基板実装体に関する。
電子部品の高密度実装を実現するため、電子部品を基板に内蔵した部品内蔵基板が知られている。このような部品内蔵基板は、電子部品が配線基板に形成された絶縁層に埋設されるため、電子部品で発生する熱を、如何に効率よく外部へ放出するかが課題となる。従来の部品内蔵基板は、熱伝導性に優れた絶縁層と、電子部品の裏面(実装面とは反対側の面)に接するサーマルビアとを介して、電子部品で発生する熱を配線基板の上層に配置したヒートシンク(放熱器)に伝達して放熱させるようにしている(特許文献1)。
特開2008−305937号公報
しかしながら、上記特許文献1に開示された従来技術の部品内蔵基板では、電子部品の裏面と放熱器との間が、導熱性樹脂組成物により形成されたサーマルビアを介して接続されているが、一般に導電ペーストの熱伝導率は銅の熱伝導率よりも低いので、銅を接続したものよりも放熱特性が良好ではないという問題がある。
一方で、熱を伝え易くするために、電子部品の裏面を放熱器などの導熱部材に直接接触させると、外部から浸入した水分が密着力の弱い電子部品の裏面と放熱器との間に浸入することでこれらの間に隙間が生じ、部品内蔵基板の信頼性を低下させてしまうという問題もある。
この発明は、上述した従来技術による問題点を解消し、電子部品と導熱層との密着性を確保し、放熱特性を向上させることができる部品内蔵基板及びその製造方法並びに部品内蔵基板実装体を提供することを目的とする。
本発明に係る部品内蔵基板は、樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板であって、前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、前記複数のプリント配線基材のうちの少なくとも一つには、前記電子部品が内蔵される開口部が形成されると共に、この開口部に内蔵される前記電子部品の電極形成面と反対側の面と密着する金属部材からなる導熱層が形成され、前記電子部品は、前記導熱層の前記開口部に臨む領域に形成された孔部を介して、前記導熱層上に積層された接着層により前記開口部内に固定されていることを特徴とする。
本発明に係る部品内蔵基板によれば、部品内蔵基板に内蔵された電子部品の電極形成面と反対側の面が、開口部内において導電ペーストよりも熱伝導率の高い金属部材からなる導熱層に密着すると共に、導熱層の開口部に臨む領域に形成された孔部を介して、導熱層上に積層された接着層により開口部内に固定されるので、電子部品と導熱層との密着性を確実なものとし、放熱特性を向上させることができる。
本発明の一つの実施形態においては、前記孔部が、前記領域内で離散的に形成されている。
また、本発明の他の実施形態においては、前記導熱層が、前記サーマルビア及び前記サーマル配線を介して表層に形成されたバンプに接続されている。
本発明に係る部品内蔵基板実装体は、前記導熱層が、前記サーマルビア及び前記サーマル配線を介して表層に形成されたバンプに接続された前記部品内蔵基板を、前記バンプを介して実装基板に実装してなることを特徴とする。
本発明に係る部品内蔵基板実装体によれば、部品内蔵基板に内蔵された電子部品の電極形成面とは反対側の面が、導熱層、サーマルビア、サーマル配線及び部品内蔵基板の表層に形成されたバンプを介して実装基板に接続されている。このため、電子部品の熱が導熱層、サーマルビア、サーマル配線及びバンプを放熱経路として伝わって、効率よく確実に実装基板に放熱される。実装基板は電子部品や部品内蔵基板と比べると十分に面積が広いので、放熱媒体としては従来のような放熱器よりも良好であり、放熱器を設ける必要がない。これにより、小型化が可能であると共に電子部品のレイアウトの自由度を高めることができ、更に内蔵された電子部品の放熱特性の向上を図ることができる。
本発明に係る部品内蔵基板の製造方法は、樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板の製造方法であって、複数の樹脂基材にサーマル配線を含む前記配線パターン及びサーマルビアを含む前記ビアを形成すると共に、前記複数の樹脂基材のうちの少なくとも一つに前記電子部品を内蔵する開口部及びこの開口部に内蔵される前記電子部品の電極形成面と反対側の面と密着し前記開口部に臨む領域に孔部を有する金属部材からなる導熱層を形成して複数のプリント配線基材を形成する工程と、前記電子部品の電極形成面と反対側の面が、前記孔部を介して前記導熱層上に積層される接着層により前記開口部内に固定されて前記導熱層と密着するように前記複数のプリント配線基材を熱圧着して一括積層する工程とを備えたことを特徴とする。
本発明に係る部品内蔵基板の製造方法によれば、部品内蔵基板に内蔵された電子部品の電極形成面とは反対側の面が、開口部内において導電ペーストよりも熱伝導率の高い金属部材からなる導熱層に密着すると共に、導熱層の開口部に臨む領域に形成された孔部を介して、導熱層上に積層された接着層により開口部内に固定されるので、上記と同様の作用効果を奏することができる。
本発明によれば、電子部品と導熱層との密着性を確保し、放熱特性を向上させることができる。
本発明の第1の実施形態に係る部品内蔵基板実装体の構造を示す断面図である。 同部品内蔵基板実装体の製造工程を示すフローチャートである。 同部品内蔵基板実装体の製造工程を示すフローチャートである。 同部品内蔵基板実装体の製造工程を示すフローチャートである。 同部品内蔵基板実装体の製造工程を示すフローチャートである。 同部品内蔵基板実装体を製造工程毎に示す断面図である。 同部品内蔵基板実装体を製造工程毎に示す断面図である。 同部品内蔵基板実装体を製造工程毎に示す断面図である。 同部品内蔵基板実装体を製造工程毎に示す断面図である。 同部品内蔵基板実装体の導熱層の平面図である。 同部品内蔵基板実装体の他の導熱層の平面図である。 同部品内蔵基板実装体の更に他の導熱層の平面図である。 本発明の第2の実施形態に係る部品内蔵基板実装体の構造を示す断面図である。
以下、添付の図面を参照して、この発明の実施の形態に係る部品内蔵基板及びその実装体並びに部品内蔵基板の製造方法を詳細に説明する。
[第1の実施形態]
図1は、本発明の第1の実施形態に係る部品内蔵基板実装体の構造を示す断面図である。図1に示すように、第1の実施形態に係る部品内蔵基板実装体100は、部品内蔵基板1と、この部品内蔵基板1が実装面2aに実装された実装基板2とからなる。
部品内蔵基板1は、第2プリント配線基材20と、第3プリント配線基材30と、第4プリント配線基材40と、第1プリント配線基材に代わるカバーレイフィルム3とを熱圧着により一括積層した構造を備えている。また、部品内蔵基板1は、第2プリント配線基材20の第2樹脂基材21に形成された開口部29内に、第3プリント配線基材30及びカバーレイフィルム3に挟まれた状態で内蔵された電子部品90を備えている。更に、部品内蔵基板1は、第4プリント配線基材40の実装面2a側に形成されたバンプ49を備えている。
第3及び第4プリント配線基材30,40は、それぞれ第3及び第4樹脂基材31,41と、これら第3及び第4樹脂基材31,41の少なくとも片面に形成された信号用配線32,42及びサーマル配線33,43とを備える。また、第3及び第4プリント配線基材30,40は、それぞれ第3及び第4樹脂基材31,41に形成されたビアホール内に充填形成されたサーマルビア34,44及び信号用ビア35,45を備える。
一方、第2プリント配線基材20は、第2樹脂基材21の一方の面に形成されたサーマル配線23と、他方の面に形成された孔部を有する導体層8と、第2樹脂基材21に形成されたビアホール内に第2樹脂基材21の両面を導通するように形成されたサーマルビア24とを備える。これら第2〜第4プリント配線基材20〜40は、例えば片面銅張積層板(片面CCL)や両面銅張積層板(両面CCL)などを用いてもよい。
本例では、第2プリント配線基材20が両面CCLに基づき形成され、第3及び第4プリント配線基材30,40が片面CCLに基づき形成されている。従って、第2プリント配線基材20の導体層8及びサーマル配線23は第2樹脂基材21の両面に形成され、サーマルビア24はこれら両面の導体層8及びサーマル配線23を層間接続している。
この場合、サーマルビア24は、例えば導体層8を貫通させることなくサーマル配線23側から形成した貫通孔内にめっきを施した構造からなり、例えば銅めっきにより形成される。このとき、貫通孔内をめっきする代わりに導電ペーストを充填させた構造としてもよい。なお、導体層8は、その上に形成されためっき層23aと共に電子部品90からの熱を伝導する導熱層23Aを構成する。
第2〜第4樹脂基材21〜41及びカバーレイフィルム3は、それぞれ例えば厚さ25μm程度の樹脂フィルムにより構成されている。ここで、樹脂フィルムとしては、例えば熱可塑性のポリイミド、ポリオレフィン、液晶ポリマーなどからなる樹脂フィルムや、熱硬化性のエポキシ樹脂からなる樹脂フィルムなどを用いることができる。
電子部品90は、例えばICチップなどの半導体部品や受動部品等であり、図1に示す電子部品90は、再配線を施したWLP(Wafer Level Package)を示している。電子部品90の電極形成面91bには、パッド91c上に形成された複数の再配線電極91が設けられ、その周囲には絶縁層91dが形成されている。
なお、信号用配線32,42及びサーマル配線23,33,43は、例えば厚さ12μm程度の銅箔などの導電材をパターン形成してなる。信号用ビア35,45及びサーマルビア34,44は、ビアホール内にそれぞれ充填された導電ペーストからなり、サーマルビア24は、上記のようにめっきにより形成される。サーマル配線及びサーマルビアは、一部を除いて電子部品90の外周側に配置されるように形成されている。
導電ペーストは、例えばニッケル、金、銀、銅、アルミニウム、鉄などから選択される少なくとも1種類の低電気抵抗の金属粒子と、錫、ビスマス、インジウム、鉛などから選択される少なくとも1種類の低融点の金属粒子とを含み、エポキシ、アクリル、ウレタンなどを主成分とするバインダ成分を混合したペーストからなる。
このように構成された導電ペーストは、熱伝導率が例えば5〜13.5W/(m・K)と低く、含有された低融点の金属が200℃以下で溶融し合金を形成することができ、特に銅や銀などとは金属間化合物を形成することができる特性を備える。なお、導電ペーストは、例えば粒子径がナノレベルの金、銀、銅、ニッケル等のフィラーが、上記のようなバインダ成分に混合されたナノペーストで構成することもできる。
その他、導電ペーストは、上記ニッケル等の金属粒子が、上記のようなバインダ成分に混合されたペーストで構成することもできる。この場合、導電ペーストは、金属粒子同士が接触することで電気的接続が行われる特性となる。導電ペーストのビアホールへの充填方法としては、例えば印刷工法、スピン塗布工法、スプレー塗布工法、ディスペンス工法、ラミネート工法、及びこれらを併用した工法などを用いることができる。
バンプ49は、半田などからなり、第4プリント配線基材40の第4樹脂基材41の実装面2a側に形成された信号用配線42及びサーマル配線43上のソルダーレジスト48が被覆していない部分に形成されている。部品内蔵基板1は、これらバンプ49を介して実装基板2の実装面2a上に実装されている。なお、第2〜第4プリント配線基材20〜40及びカバーレイフィルム3は、接着層9を介して積層されている。接着層9は、例えばエポキシ系やアクリル系接着材など、揮発成分が含まれた有機系接着材などからなる。
第2プリント配線基材20の開口部29内に配置された電子部品90は、電極形成面91bとは反対側の裏面91aが、導熱層23Aの導体層8と密着する。これと共に、裏面91aは、導熱層23Aの開口部29に臨む領域に形成された孔部23Bを介して、カバーレイフィルム3の接着層9により接着される。これにより、電子部品90は、裏面91aと導体層8とが密着した状態で開口部29内に固定される。
導体層8が純銅の銅箔からなる場合、純銅の熱伝導率は0℃にて403W/(m・K)、100℃にて395W/(m・K)と非常に高いので、裏面91aと密着させることは放熱特性を向上させるのに非常に有効である。なお、孔部23Bを設けずに開口部29内に電子部品90を固定させる場合、導体層8と電子部品90の裏面とは直接接着できないので、これらの間には何らかの接着媒体が必要となり、孔部を有する導体層8に電子部品90を密着させる場合に比べて、熱伝導特性が劣る。
このように構成された部品内蔵基板実装体100では、電子部品90が、導熱層23Aと実装基板2との間に配置される構造となる。そして、部品内蔵基板1に内蔵された電子部品90の熱は、次のような放熱経路を辿って実装基板2に伝えられる。すなわち、電子部品90の熱は、電子部品90の裏面91aから、第2プリント配線基材20の導熱層23Aに伝わる。
導熱層23Aに伝わった熱は、電子部品90の外周側に形成されたサーマルビア24を通って、第3プリント配線基材30のサーマルビア34及びサーマル配線33に伝わり、更に第4プリント配線基材40のサーマルビア44及びサーマル配線43に伝わって、バンプ49に伝わる。こうしてバンプ49に伝わった熱は、このバンプ49を介して部品内蔵基板1よりも面積の大きな実装基板2に伝わり、実装基板2から放熱される。
このような構造により、部品内蔵基板1に内蔵された電子部品90で発生した熱の殆どが、従来のような放熱器が不要な構造の部品内蔵基板1から実装基板2に伝わって放熱されることとなる。
次に、第1の実施形態に係る部品内蔵基板の製造方法について説明する。
図2〜図5は、部品内蔵基板実装体の製造工程を示すフローチャートである。図6〜図9は、部品内蔵基板実装体を製造工程毎に示す断面図である。なお、図2及び図6は第3及び第4プリント配線基材30,40について、図3及び図7は第2プリント配線基材20について、図4及び図8は電子部品について、図5及び図9は部品内蔵基板実装体についてそれぞれの製造工程の詳細を示している。
まず、第3及び第4プリント配線基材30,40の製造工程について説明する。なお、これらは同様の工程で製造することができるので、ここでは図2を参照しながら代表して第4プリント配線基材40の製造工程について説明するが、第3プリント配線基材30についても同様である。
図6(a)に示すように、第4樹脂基材41の一方の面に導体層8が形成された片面銅張積層板(片面CCL)を準備する(ステップS100)。次に、導体層8上にフォトリソグラフィによりエッチングレジストを形成した後にエッチングを行って、図6(b)に示すように、信号用配線42やサーマル配線43等の配線パターンを形成する(ステップS102)。
ステップS100にて使用する片面CCLは、例えば厚さ12μm程度の銅箔からなる導体層8に、厚さ25μm程度の第4樹脂基材41を貼り合わせた構造からなる。なお、この片面CCLとしては、例えばキャスティング法により、銅箔にポリイミドのワニスを塗布してそのワニスを硬化させて作製されたものを使用することができる。
キャスティング法は、押出機によって溶融された樹脂を、平坦なダイに設けられた直線状のスリットから押し出して、その溶融膜を冷却されたロールで急速に冷やして圧延しながら巻き取ることで、平坦なフィルムやシートを成形する公知の方法である。この方法は、信頼性が高く多用されている。
その他、片面CCLとしては、ポリイミドフィルム上にシード層をスパッタリングにより形成し、めっきにより銅を成長させて導体層8を形成したものや、圧延或いは電解銅箔とポリイミドフィルムとを接着材により貼り合わせて作製されたものなどを使用することもできる。なお、第4樹脂基材41は必ずしもポリイミドからなるものである必要はなく、液晶ポリマー等のプラスチックフィルムからなるものであってもよい。また、ステップS102でのエッチングには塩化第二鉄を主成分とするエッチャントや、塩化第二銅を主成分とするエッチャントなどを用いることができる。
配線パターンを形成したら、図6(c)に示すように、第4樹脂基材41の信号用配線42及びサーマル配線43形成面側と反対側の面に、接着材9a及びマスク材7を加熱圧着により貼り付ける(ステップS104)。ステップS104にて貼り付けられる接着材9aとしては、例えば厚さ25μm程度のエポキシ系熱硬化性フィルムを使用することができる。加熱圧着には真空ラミネータを用い、減圧下の雰囲気中にて、接着材9aの硬化温度以下の温度で0.3MPaの圧力によりプレスしてこれらを貼り合わせることが挙げられる。
なお、接着層9や接着材9aに用いられる層間接着材は、エポキシ系の熱硬化性フィルムのみならず、アクリル系の接着材や、熱可塑性ポリイミドなどに代表される熱可塑性接着材などが挙げられる。また、層間接着材は必ずしもフィルム状である必要はなく、ワニス状の樹脂を塗布したものであってもよい。マスク材は、上述した樹脂フィルムやPET,PENなどのプラスチックフィルムの他、UV照射によって接着や剥離が可能な各種フィルムを用いることができる。
その後、図6(d)に示すように、貼り付けたマスク材7側から、信号用配線42及びサーマル配線43に向かってマスク材7、接着材9a及び第4樹脂基材41を貫通するビアホール6を所定箇所に形成し(ステップS106)、ビアホール6内に例えばプラズマデスミア処理を施す。
ステップS106にて形成されるビアホール6は、直径φ100μm程度であり、UVレーザを使用して所定箇所に形成される。ビアホール6は、その他、炭酸ガスレーザやエキシマレーザなどで形成してもよいし、ドリル加工や化学的なエッチングなどにより形成してもよい。また、プラズマデスミア処理は、CF及びO(四フッ化メタン+酸素)の混合ガスにより行うことができるが、Ar(アルゴン)などのその他の不活性ガスを用いることもでき、いわゆるドライ処理ではなく、薬液を用いたウェットデスミア処理としてもよい。
そして、図6(e)に示すように、形成したビアホール6内に、例えばスクリーン印刷により導電ペーストを充填して信号用ビア45及びサーマルビア44の各種ビアを形成し(ステップS108)、マスク材7を剥離して、接着層9が備えられた第4樹脂基材41を有する第4プリント配線基材40を形成する。なお、サーマルビア44は、熱伝導率の向上を図るため、導電ペーストではなくめっきにより形成するようにしてもよい。このような処理を行って、第3プリント配線基材30や、更に多層の場合はその他のプリント配線基材を形成して準備しておく。
次に、図3を参照しながら第2プリント配線基材20の製造工程について説明する。なお、既に説明した箇所には同一の符号を附して説明を割愛する場合があり、各ステップの具体的な処理内容については上述した内容を適用可能であるとする。まず、図7(a)に示すように、第2樹脂基材21の両面に全面に亘って(ベタ状態で)導体層8が形成された両面銅張積層板(両面CCL)を準備し(ステップS110)、図7(b)に示すように、所定箇所にビアホール6を形成して(ステップS112)、プラズマデスミア処理を行う。
次に、図7(c)に示すように、第2樹脂基材21の全面にパネルめっき処理を施して(ステップS114)、導体層8上及びビアホール6内にめっき層23aを形成する。なお、ビアホール6内のめっき層23aは後にサーマルビア24として用いられるめっきビアであり、第2樹脂基材21の両面の導体層8を電気的に導通している。
そして、図7(d)に示すように、第2樹脂基材21の両面にエッチング等により導体層8及びめっき層23aからなる導熱層23Aやサーマル配線23及びサーマルビア24などの配線パターンを形成すると共に、電子部品90を接着するための孔部23Bを導熱層23Aに形成する(ステップS116)。
なお、このステップS116にて導熱層23Aに形成される孔部23Bは、例えば図10に示すように、開口部29となる領域よりも狭く、且つ電子部品90の面積よりも狭い範囲内に矩形状且つメッシュ状に複数個パターン形成される。孔部23Bが離散的に配され、孔部23B内に入り込んだ接着材と電子部品90の裏面91aとが接着されるため、密着力の弱い電子部品90の裏面91aと導熱層23Aとの間で、水分が留まり、実装時のリフロー等による加熱や電子部品チップの発熱等で水分が蒸発して、これらの間で隙間が生じ、部品内蔵基板の信頼性を低下させてしまうことを防止できる。その他、孔部23Bは、図11に示すように、円形状且つメッシュ状に形成されたり、図12に示すように、一つの矩形状に形成されたりしてもよい。更に、図示は省略するが、孔部23Bは、複数個のそれぞれのサイズが異なるパターンや、格子状パターンなど、電子部品90の裏面91aと導熱層23Aとが密着する面積を残すように種々のパターンで形成されてもよい。
最後に、図7(e)に示すように、電子部品90が内蔵される部分の第2樹脂基材21をUVレーザなどにより除去し、開口部29を形成して(ステップS118)、第2プリント配線基材20を形成する。
なお、このように形成された第2プリント配線基材20の開口部29に内蔵される電子部品90は、例えば次のように製造される。図4を参照しながら電子部品90の製造工程について説明する。まず、図8(a)に示すように、酸化ケイ素や窒化ケイ素などの無機絶縁層が形成されたダイシング前のウェハ92を準備する(ステップS120)。
次に、図8(b)に示すように、準備したウェハ92の表面に、例えばセミアディティブ法によって、電子部品90のパッド91c上及び無機絶縁層上に導体回路(図示せず)やパッド91cを覆う再配線電極91を形成する(ステップS122)。
そして、図8(c)に示すように、例えば液状の感光性ポリイミド前駆体をスピンコートし、フォトリソグラフィによってコンタクトホールを形成した後に、焼成することで絶縁層91dを形成する(ステップS124)。最後に、プロービングにより検査を行って、図8(d)に示すように、薄型化及びダイシングにより電子部品90を個片化して作製する(ステップS126)。
なお、ステップS124にて形成される絶縁層91dの樹脂は、例えばベンゾシクロブテン(BCB)や、ポリベンゾオキサゾール(PBO)などを用いることができる。また、感光性樹脂は必ずしもスピンコートによって塗布される必要はなく、カーテンコートやスクリーン印刷、或いはスプレーコートなどによって塗布されてもよい。このようにして作製された電子部品90には、通常の導電用回路の他、インダクタ、キャパシタ、抵抗などの各機能を付与させることもできる。
こうして、第2〜第4プリント配線基材20〜40及び電子部品90を作製したら、図9に示すように、電子部品90の再配線電極91と第3プリント配線基材30の信号用ビア35を、電子部品用実装機で位置合わせして、第3プリント配線基材30の接着層9及び信号用ビア35の導電ペーストが硬化していない状態で、電子部品90を第3プリント配線基材30に仮留め接着する。
その後、図5に示すように、各プリント配線基材20〜40、電子部品90及び接着層9が形成されたカバーレイフィルム3を位置決めし、積層する(ステップS130)。例えば真空プレス機を用いて、1kPa以下の減圧雰囲気中にて加熱加圧することで熱圧着により一括積層し(ステップS132)、まず、図1に示すような部品内蔵基板1を製造する。このとき、層間の各接着層9や各樹脂基材21,31等の硬化と同時に、ビアホール6に充填された導電ペーストの硬化及び合金化が行われる。従って、導電ペーストと接する配線等との間には、金属間化合物の合金層が形成される。
そして、部品内蔵基板1における第4プリント配線基材40の信号用配線42及びサーマル配線43側の第4樹脂基材41上に、ソルダーレジスト48をパターン形成する(ステップS134)。ソルダーレジスト48を形成したら、各配線42,43上に半田などによりバンプ49を形成して(ステップS136)、部品内蔵基板1を実装基板2の実装面2a上に実装することで(ステップS138)、図1に示すような第1の実施形態に係る部品内蔵基板実装体100を製造する。
[第2の実施形態]
図13は、本発明の第2の実施形態に係る部品内蔵基板実装体の構造を示す断面図である。図13に示すように、第2の実施形態に係る部品内蔵基板実装体100Aは、カバーレイフィルム3の代わりに第1プリント配線基材10が積層され、電子部品90の放熱が実装基板2のみならず第1プリント配線基材10側からも行われる点が、第1の実施形態に係る部品内蔵基板実装体100と相違している。
具体的には、第1プリント配線基材10は、基本的には図2及び図6を用いて説明した第4プリント配線基材40と同様の工程で製造することができ、第1樹脂基材11の片面にベタパターンの導体層8を形成した構造からなる。第4プリント配線基材40との相違点としては、ステップS102にて配線パターンを形成することなく、片面CCLの導体層8をそのまま利用し、積層態様が表裏逆になる点である。
このように構成された第1プリント配線基材10は、導体層8と接続するサーマルビア14が複数形成され、各サーマルビア14が第2プリント配線基材20の導熱層23Aと接続された状態で積層される。また、導体層8上には、別途形成された熱伝導率が高い部材からなる放熱用フィン80が全面にわたって密着接続される。
従って、電子部品90で発生した熱は、導熱層23Aを通って実装基板2から放熱されると共に、サーマルビア14及び導体層8を通って放熱用フィン80からも放熱される。これにより、放熱特性をより向上させることができる。
1 部品内蔵基板
2 実装基板
2a 実装面
3 カバーレイフィルム
6 ビアホール
7 マスク材
8 導体層
9 接着層
9a 接着材
10 第1プリント配線基材
11 第1樹脂基材
14 サーマルビア
20 第2プリント配線基材
21 第2樹脂基材
23 サーマル配線
23a めっき層
23A 導熱層
23B 孔部
24 サーマルビア
29 開口部
30 第3プリント配線基材
31 第3樹脂基材
32 信号用配線
33 サーマル配線
34 サーマルビア
35 信号用ビア
40 第4プリント配線基材
41 第4樹脂基材
42 信号用配線
43 サーマル配線
44 サーマルビア
45 信号用ビア
48 ソルダーレジスト
49 バンプ
80 放熱用フィン
90 電子部品
91 再配線電極
91a 裏面
91b 電極形成面
91c パッド
91d 絶縁層
100 部品内蔵基板実装体

Claims (5)

  1. 樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板であって、
    前記複数のプリント配線基材の少なくとも一部が、前記配線パターンにサーマル配線を含み、前記ビアにサーマルビアを含み、
    前記複数のプリント配線基材のうちの少なくとも一つには、前記電子部品が内蔵される開口部が形成されると共に、この開口部に内蔵される前記電子部品の電極形成面と反対側の面と密着する金属部材からなる導熱層が形成され、
    前記電子部品は、前記導熱層の前記開口部に臨む領域に形成された孔部を介して、前記導熱層上に積層された接着層により前記開口部内に固定されている
    ことを特徴とする部品内蔵基板。
  2. 前記孔部は、前記領域内で離散的に形成されていることを特徴とする請求項1記載の部品内蔵基板。
  3. 前記導熱層は、前記サーマルビア及び前記サーマル配線を介して表層に形成されたバンプに接続されていることを特徴とする請求項1又は2記載の部品内蔵基板。
  4. 請求項3記載の部品内蔵基板を、前記バンプを介して実装基板に実装してなることを特徴とする部品内蔵基板実装体。
  5. 樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板の製造方法であって、
    複数の樹脂基材にサーマル配線を含む前記配線パターン及びサーマルビアを含む前記ビアを形成すると共に、前記複数の樹脂基材のうちの少なくとも一つに前記電子部品を内蔵する開口部及びこの開口部に内蔵される前記電子部品の電極形成面と反対側の面と密着し前記開口部に臨む領域に孔部を有する金属部材からなる導熱層を形成して複数のプリント配線基材を形成する工程と、
    前記電子部品の電極形成面と反対側の面が、前記孔部を介して前記導熱層上に積層される接着層により前記開口部内に固定されて前記導熱層と密着するように前記複数のプリント配線基材を熱圧着して一括積層する工程とを備えた
    ことを特徴とする部品内蔵基板の製造方法。
JP2011262217A 2011-11-30 2011-11-30 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体 Active JP5167516B1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2011262217A JP5167516B1 (ja) 2011-11-30 2011-11-30 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
EP12854222.2A EP2787799B1 (en) 2011-11-30 2012-11-14 Board with embedded component and method for manufacturing same, and package with board with embedded component
DK12854222.2T DK2787799T3 (da) 2011-11-30 2012-11-14 Plade med indlejret komponent og fremgangsmåde til fremstilling af samme og pakke med plade med indlejret komponent
PCT/JP2012/079463 WO2013080790A1 (ja) 2011-11-30 2012-11-14 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
US14/290,173 US9591767B2 (en) 2011-11-30 2014-05-29 Component built-in board and method of manufacturing the same, and component built-in board mounting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011262217A JP5167516B1 (ja) 2011-11-30 2011-11-30 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体

Publications (2)

Publication Number Publication Date
JP5167516B1 JP5167516B1 (ja) 2013-03-21
JP2013115345A true JP2013115345A (ja) 2013-06-10

Family

ID=48134659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011262217A Active JP5167516B1 (ja) 2011-11-30 2011-11-30 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体

Country Status (5)

Country Link
US (1) US9591767B2 (ja)
EP (1) EP2787799B1 (ja)
JP (1) JP5167516B1 (ja)
DK (1) DK2787799T3 (ja)
WO (1) WO2013080790A1 (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015146346A (ja) * 2014-01-31 2015-08-13 イビデン株式会社 多層配線板
JP6317989B2 (ja) * 2014-04-24 2018-04-25 新光電気工業株式会社 配線基板
EP2940729A1 (en) * 2014-04-28 2015-11-04 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic assembly comprising a carrier structure made from a printed circuit board
JP6582669B2 (ja) * 2015-07-22 2019-10-02 Tdk株式会社 薄膜キャパシタ及び半導体装置
US9823691B2 (en) * 2015-07-23 2017-11-21 Toshiba Memory Corporation Semiconductor storage device
KR20170066843A (ko) * 2015-12-07 2017-06-15 삼성전자주식회사 적층형 반도체 장치 및 적층형 반도체 장치의 제조 방법
JP6770331B2 (ja) * 2016-05-02 2020-10-14 ローム株式会社 電子部品およびその製造方法
JP6662716B2 (ja) * 2016-06-08 2020-03-11 新光電気工業株式会社 光センサ、光センサの製造方法
US10057989B1 (en) * 2017-04-10 2018-08-21 Tactotek Oy Multilayer structure and related method of manufacture for electronics
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
EP3917291A3 (en) 2020-05-27 2022-02-09 Hamilton Sundstrand Corporation Systems for thermal control of a generator control unit
US11497112B2 (en) * 2020-12-11 2022-11-08 Toyota Motor Engineering & Manufacturing North America, Inc. Driver board assemblies and methods of forming a driver board assembly
WO2022222015A1 (en) * 2021-04-20 2022-10-27 Huawei Technologies Co., Ltd. Semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058735A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
JP2008159682A (ja) * 2006-12-21 2008-07-10 Fujikura Ltd 多層プリント配線板およびその製造方法
JP2008205124A (ja) * 2007-02-19 2008-09-04 Fujikura Ltd 電子部品内蔵型配線基板及びその製造方法
JP2010157663A (ja) * 2009-01-05 2010-07-15 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400573B1 (en) * 1993-02-09 2002-06-04 Texas Instruments Incorporated Multi-chip integrated circuit module
JP3709882B2 (ja) * 2003-07-22 2005-10-26 松下電器産業株式会社 回路モジュールとその製造方法
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP2008305937A (ja) 2007-06-07 2008-12-18 Panasonic Corp 電子部品内蔵モジュールおよびその製造方法
US7843056B2 (en) * 2009-02-20 2010-11-30 National Semiconductor Corporation Integrated circuit micro-module
JP5330184B2 (ja) * 2009-10-06 2013-10-30 新光電気工業株式会社 電子部品装置
US8472190B2 (en) * 2010-09-24 2013-06-25 Ati Technologies Ulc Stacked semiconductor chip device with thermal management

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058735A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
JP2008159682A (ja) * 2006-12-21 2008-07-10 Fujikura Ltd 多層プリント配線板およびその製造方法
JP2008205124A (ja) * 2007-02-19 2008-09-04 Fujikura Ltd 電子部品内蔵型配線基板及びその製造方法
JP2010157663A (ja) * 2009-01-05 2010-07-15 Dainippon Printing Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法

Also Published As

Publication number Publication date
WO2013080790A1 (ja) 2013-06-06
EP2787799A1 (en) 2014-10-08
DK2787799T3 (da) 2020-05-11
US9591767B2 (en) 2017-03-07
JP5167516B1 (ja) 2013-03-21
US20140268574A1 (en) 2014-09-18
EP2787799A4 (en) 2015-07-29
EP2787799B1 (en) 2020-02-12

Similar Documents

Publication Publication Date Title
JP5167516B1 (ja) 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体
JP5406389B2 (ja) 部品内蔵基板及びその製造方法
US8941016B2 (en) Laminated wiring board and manufacturing method for same
US9560770B2 (en) Component built-in board and method of manufacturing the same, and mounting body
JP5100878B1 (ja) 部品内蔵基板実装体及びその製造方法並びに部品内蔵基板
JP2013211480A (ja) 部品内蔵基板
JP2008103640A (ja) 多層配線基板
US9699921B2 (en) Multi-layer wiring board
JP5007164B2 (ja) 多層配線板及び多層配線板製造方法
JP2009016377A (ja) 多層配線板及び多層配線板製造方法
US20240090140A1 (en) Component-incorporated substrate and method for manufacturing same
US20150351218A1 (en) Component built-in board and method of manufacturing the same, and mounting body
JP2013135113A (ja) 部品内蔵基板の製造方法
JP6028256B2 (ja) 部品内蔵基板及びその製造方法
JP6315681B2 (ja) 部品内蔵基板及びその製造方法並びに実装体
JP5836019B2 (ja) 部品内蔵基板およびその製造方法
US9826646B2 (en) Component built-in board and method of manufacturing the same, and mounting body
JP2014045092A (ja) 部品内蔵基板
JP6062884B2 (ja) 部品内蔵基板及びその製造方法並びに実装体
JP6020943B2 (ja) 部品内蔵基板の製造方法
JP5920716B2 (ja) 部品内蔵基板の製造方法
JP3979404B2 (ja) 半導体装置
KR101231443B1 (ko) 인쇄회로기판 및 그의 제조 방법
JP5906520B2 (ja) 電子部品の製造方法及び電子部品内蔵プリント回路基板の製造方法
JP2012186279A (ja) 電子部品を内蔵した積層プリント配線板及びその製造方法

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121204

R150 Certificate of patent or registration of utility model

Ref document number: 5167516

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250