JP2013058989A - 半導体装置及びマイクロフォン - Google Patents
半導体装置及びマイクロフォン Download PDFInfo
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- JP2013058989A JP2013058989A JP2011197288A JP2011197288A JP2013058989A JP 2013058989 A JP2013058989 A JP 2013058989A JP 2011197288 A JP2011197288 A JP 2011197288A JP 2011197288 A JP2011197288 A JP 2011197288A JP 2013058989 A JP2013058989 A JP 2013058989A
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- bonding
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- B81—MICROSTRUCTURAL TECHNOLOGY
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
【解決手段】カバー44と基板45を上下に重ね合わせることによってパッケージを形成する。カバー44に設けた凹部46の天面にはマイクチップ42が実装され、基板45の上面には回路素子43が実装される。マイクチップ42はボンディングワイヤ50によってカバー下面のパッド48に接続され、回路素子43はボンディングワイヤによって基板上面のパッドに接続される。カバー下面のパッド48に導通したカバー側接合部49と基板上面のパッドに導通した基板側接合部69は、導電性材料86によって接合される。ボンディング用パッド48及びカバー側接合部49の近傍において、カバー44内には電磁シールド用の導電層55が埋め込まれている。
【選択図】図6
Description
図4−図10を参照して本発明の実施形態1によるトップポート型のマイクロフォン41を説明する。マイクロフォン41は、MEMS技術を用いて製造されるMEMSマイクロフォンであって、カバー44(第1の部材)と基板45(第2の部材)からなるパッケージ内にマイクチップ42(センサ)と回路素子43を納めたものである。また、実施形態1のマイクロフォン41は、カバー44に音響孔53を開口されていてトップポート型となっている。図4(A)はマイクチップ42を実装したカバー44の下面図であり、図4(B)は回路素子43を実装した基板45の平面図である。図5(A)はソルダーレジストを除去したカバー44の下面図であり、図5(B)はソルダーレジストを除去した基板45の平面図である。また、図6は、図4のX1−X1線に相当する箇所におけるマイクロフォン41の断面図である。図7は、図4のY1−Y1線に相当する箇所におけるマイクロフォン41の断面図である。図8は、図4のZ1−Z1線に相当する箇所におけるマイクロフォン41の断面図である。図9(A)は図6のH1−H1線に沿ったカバーの断面図、図9(B)は図6のH2−H2線に沿ったカバーの断面図、図9(C)は図6のH3−H3線に沿ったカバーの断面図、図9(D)は図6のH4−H4線に沿ったカバーの断面図である。図10(A)−(D)はカバーの製造工程を示す概略図である。
図11は、本発明の実施形態2によるトップボトム型のマイクロフォン91を示す断面図である。図12は、マイクロフォン91のカバー44の構成を示す断面図である。図13(A)−(D)は、図11のH5−H5線に沿ったカバーの断面図、図11のH6−H6線に沿ったカバーの断面図、図11のH7−H7線に沿ったカバーの断面図、及び図11のH8−H8線に沿ったカバーの断面図である。
つぎに、本発明の実施形態3によるトップポート型のマイクロフォン92を説明する。図14(A)はマイクチップ42を実装したカバー44の下面図であり、図14(B)は回路素子43を実装した基板45の平面図である。図15(A)はソルダーレジストを除去したカバー44の下面図であり、図15(B)はソルダーレジストを除去した基板45の平面図である。また、図16は、図14のX2−X2線に相当する箇所におけるマイクロフォン92の断面図である。図17は、図14のY2−Y2線に相当する箇所におけるマイクロフォン92の断面図である。図18は、図14のZ2−Z2線に相当する箇所におけるマイクロフォン92の断面図である。
実施形態3のマイクロフォン92のように基板45が凹部66を有している場合には、基板45の外周部の斜め下方からノイズが飛来すると、ボンディング用パッド68、カバー側接合部69や高インピーダンスのボンディングワイヤ80がノイズを拾うおそれがある。
つぎに、本発明の実施形態5によるマイクロフォン94を説明する。図20(A)はマイクチップ42を実装したカバー44の下面図であり、図20(B)は回路素子43を実装した基板45の平面図である。図21(A)は、図20のX3−X3線に相当する箇所におけるマイクロフォン94の断面図である。図21(B)は、図20のY3−Y3線に相当する箇所におけるマイクロフォン94の断面図である。
図22に示すものは実施形態6によるマイクロフォン95である。このマイクロフォン95では、カバー44の下面に回路素子43を実装し、基板45の上面にマイクチップ42を実装したものである。図22では、音響孔53を基板45に設けてあってボトムポート型となっているが、音響孔をカバー44に設けてトップポート型としていてもよい。このようなマイクロフォン95おいても、カバー44内に水平に電磁シールド用の導電層55を設けたり、基板45内に水平に電磁シールド用の導電層85を設けたりすることで、マイクロフォン95の耐ノイズ性を向上させることができる。
図23、図24及び図25により本発明の実施形態7によるマイクロフォン96を説明する。図23(A)はマイクチップ42を実装したカバー44の下面図であり、図23(B)は回路素子43を実装した基板45の平面図である。図24(A)は、ソルダーレジストを除去した実施形態7のカバー44の下面図である。図24(B)は、ソルダーレジストを除去した実施形態7の基板45の平面図である。図25は、図23のX4−X4線に相当する箇所におけるマイクロフォン96の断面図である。
図26及び図27により本発明の実施形態8によるマイクロフォン97を説明する。図26(A)は、本発明の実施形態8におけるマイクチップ42を実装したカバー44の下面図である。図26(B)は、実施形態8における回路素子43を実装した基板45の平面図である。図27は、実施形態8のマイクロフォン97の断面図であって、図26のX5−X5線に相当する箇所における断面を表している。
本発明は、上記実施形態以外にも、特願2010−125527に記載された種々の実施形態に適用することができる。たとえば、上記トップポート型のマイクロフォンでは、マイクチップ42の位置でカバー44に音響孔53が開口されていたが、マイクチップ42から外れた位置でカバー44に音響孔53を設けていてもよい(たとえば、特願2010−125527の図9−11に記載されたマイクロフォン)。また、基板45にマイクチップ42を実装し、カバー44に音響孔53を開口したトップポート型のマイクロフォンでもよい。
42 マイクチップ
43 回路素子
44 カバー
45 基板
46 凹部
47 導電層
48 ボンディング用パッド
49 カバー側接合部
50 ボンディングワイヤ
51 グランド接合部
53 音響孔
55 導電層
56 導電層
59 導電層
60 カバー本体
61 補助プレート
62 導電性接合材
63 バイアホール
65 接合面
66 凹部
67 導電層
68 ボンディング用パッド
69 基板側接合部
70 導電層
71 グランド接合部
85 導電層
Claims (13)
- 第1の部材及び第2の部材からなり、前記第1の部材及び第2の部材のうち少なくとも一方の部材の内面に凹部を形成されたパッケージと、
前記第1の部材の内面に実装されたセンサと、
前記第2の部材の内面に実装された回路素子と、
前記第1の部材と前記第2の部材との接合部分を経由して前記センサと前記回路素子を電気的に接続する電気的接続手段とを備えた半導体装置において、
前記第1の部材と前記第2の部材との接合部分のうち前記電気的接続手段が経由する箇所の近傍に電磁シールド用の導電層を設けたことを特徴とする半導体装置。 - 電磁シールド用の前記導電層は、前記第1の部材と前記第2の部材のうち少なくとも一方の部材において、他方の部材との接合部分の表面と平行に設けられていることを特徴とする、請求項1に記載の半導体装置。
- 電磁シールド用の前記導電層は、前記第1の部材と前記第2の部材のうち少なくとも一方の部材において、他方の部材との接合部分よりも他方の部材から遠い側に設けられていることを特徴とする、請求項1に記載の半導体装置。
- 電磁シールド用の前記導電層は、前記第1の部材と前記第2の部材のうち少なくとも一方の部材に埋め込まれていることを特徴とする、請求項1に記載の半導体装置。
- 電磁シールド用の前記導電層は、前記第1の部材と前記第2の部材のうち前記凹部を有する部材において、凹部の周囲に設けられていることを特徴とする、請求項1に記載の半導体装置。
- 前記凹部の天面又は底面に第1の導電層が形成され、前記凹部の内周壁面に第2の導電層が形成され、
前記第1の導電層、前記第2の導電層及び電磁シールド用の前記導電層が互いに導通していることを特徴とする、請求項5に記載の半導体装置。 - 前記第1の部材と前記第2の部材のうち前記凹部を有する部材は、主部材と補助部材を貼合わせて構成されており、
前記主部材は凹所を有するとともに、前記補助部材との貼合わせ面に電磁シールド用の前記導電層を有し、
前記補助部材は開口を有するとともに、電磁シールド用の前記導電層に重ねるようにして前記主部材に貼合わされ、
前記凹所及び前記開口によって前記凹部が構成されていることを特徴とする、請求項1に記載の半導体装置。 - 前記第1の部材の、前記第2の部材と向き合う部分に第1のボンディング用パッドを設け、前記センサと前記第1のボンディング用パッドとを第1のワイヤ配線によって接続し、
前記第2の部材の、前記第1の部材と向き合う部分に第2のボンディング用パッドを設け、前記回路素子と前記第2のボンディング用パッドとを第2のワイヤ配線によって接続し、
前記第1の部材と前記第2の部材を接合させてパッケージを形成する際に、前記第1のボンディング用パッドと前記第2のボンディング用パッドとを導電性材料で接合させたことを特徴とする、請求項1に記載の半導体装置。 - 前記第1の部材に第1のボンディング用パッドを設けるとともに、前記第1の部材の、前記第2の部材と向き合う部分に前記第1のボンディング用パッドに導通したセンサ側接合部を設け、前記センサと前記第1のボンディング用パッドとを第1のワイヤ配線によって接続し、
前記第2の部材に第2のボンディング用パッドを設けるとともに、前記第2の部材の、前記第1の部材に向き合う部分に前記第2のボンディング用パッドに導通した回路素子側接合部を設け、前記回路素子と前記第2のボンディング用パッドとを第2のワイヤ配線によって接続し、
前記第1の部材と前記第2の部材を接合させてパッケージを形成する際に、前記センサ側接合部と前記回路素子側接合部とを導電性材料で接合させたことを特徴とする、請求項1に記載の半導体装置。 - 前記第1のボンディング用パッドと前記センサ側接合部とは連続した金属膜によって形成され、前記金属膜の表面を部分的に絶縁膜で覆うことによって前記第1のボンディング用パッドと前記センサ側接合部が区分され、
前記第2のボンディング用パッドと前記回路素子側接合部とは連続した金属膜によって形成され、前記金属膜の表面を部分的に絶縁膜で覆うことによって前記第2のボンディング用パッドと前記回路素子側接合部が区分されていることを特徴とする、請求項9に記載の半導体装置。 - 前記第1の部材の、前記第2の部材と向き合う部分にボンディング用パッドを設け、前記センサと前記ボンディング用パッドとをワイヤ配線によって接続し、
前記第2の部材にバンプ用パッドを設けるとともに、前記第2の部材の、前記第1の部材に向き合う部分に前記バンプ用パッドに導通した回路素子側接合部を設け、前記回路素子に設けたバンプを前記バンプ用パッドに接続し、
前記第1の部材と前記第2の部材を接合させてパッケージを形成する際に、前記ボンディング用パッドと前記回路素子側接合部とを導電性材料で接合させたことを特徴とする、請求項1に記載の半導体装置。 - 前記第1の部材にボンディング用パッドを設けるとともに、前記第1の部材の、前記第2の部材と向き合う部分に前記ボンディング用パッドに導通したセンサ側接合部を設け、前記センサと前記ボンディング用パッドとをワイヤ配線によって接続し、
前記第2の部材にバンプ用パッドを設けるとともに、前記第2の部材の、前記第1の部材に向き合う部分に前記バンプ用パッドに導通した回路素子側接合部を設け、前記回路素子に設けたバンプを前記バンプ用パッドに接続し、
前記第1の部材と前記第2の部材を接合させてパッケージを形成する際に、前記センサ側接合部と前記回路素子側接合部とを導電性材料で接合させたことを特徴とする、請求項1に記載の半導体装置。 - 請求項1の半導体装置において前記センサとしてマイクチップを用い、前記第1の部材又は第2の部材のいずれかの部材に音響孔が開口された、マイクロフォン。
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CN201846473U (zh) * | 2010-10-11 | 2011-05-25 | 歌尔声学股份有限公司 | 硅麦克风 |
CN201846474U (zh) * | 2010-10-12 | 2011-05-25 | 歌尔声学股份有限公司 | 硅麦克风 |
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JP2008099271A (ja) * | 2000-11-28 | 2008-04-24 | Knowles Electronics Llc | 小型シリコンコンデンサマイクロフォンおよびその製造方法 |
JP2005340961A (ja) * | 2004-05-24 | 2005-12-08 | Matsushita Electric Works Ltd | 音波受信装置 |
JP2009289924A (ja) * | 2008-05-28 | 2009-12-10 | Yamaha Corp | 半導体装置用パッケージ本体及びその製造方法、パッケージ、半導体装置、並びにマイクロフォンパッケージ |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20150002264A (ko) * | 2013-06-28 | 2015-01-07 | 삼성전기주식회사 | 반도체 패키지 |
KR101983142B1 (ko) * | 2013-06-28 | 2019-08-28 | 삼성전기주식회사 | 반도체 패키지 |
Also Published As
Publication number | Publication date |
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US8890265B2 (en) | 2014-11-18 |
CN103548361A (zh) | 2014-01-29 |
EP2755401A4 (en) | 2015-04-08 |
WO2013035596A1 (ja) | 2013-03-14 |
JP5327299B2 (ja) | 2013-10-30 |
US20140183671A1 (en) | 2014-07-03 |
CN103548361B (zh) | 2016-12-14 |
EP2755401B1 (en) | 2018-12-26 |
EP2755401A1 (en) | 2014-07-16 |
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